1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/Support/Debug.h"
30 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
31 : AMDGPUInstrInfo(st), RI() {}
33 //===----------------------------------------------------------------------===//
34 // TargetInstrInfo callbacks
35 //===----------------------------------------------------------------------===//
37 static unsigned getNumOperandsNoGlue(SDNode *Node) {
38 unsigned N = Node->getNumOperands();
39 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
44 static SDValue findChainOperand(SDNode *Load) {
45 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1);
46 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
50 /// \brief Returns true if both nodes have the same value for the given
51 /// operand \p Op, or if both nodes do not have this operand.
52 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
53 unsigned Opc0 = N0->getMachineOpcode();
54 unsigned Opc1 = N1->getMachineOpcode();
56 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
57 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
59 if (Op0Idx == -1 && Op1Idx == -1)
63 if ((Op0Idx == -1 && Op1Idx != -1) ||
64 (Op1Idx == -1 && Op0Idx != -1))
67 // getNamedOperandIdx returns the index for the MachineInstr's operands,
68 // which includes the result as the first operand. We are indexing into the
69 // MachineSDNode's operands, so we need to skip the result operand to get
74 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
77 bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
78 AliasAnalysis *AA) const {
79 // TODO: The generic check fails for VALU instructions that should be
80 // rematerializable due to implicit reads of exec. We really want all of the
81 // generic logic for this except for this.
82 switch (MI->getOpcode()) {
83 case AMDGPU::V_MOV_B32_e32:
84 case AMDGPU::V_MOV_B32_e64:
85 case AMDGPU::V_MOV_B64_PSEUDO:
92 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
94 int64_t &Offset1) const {
95 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
98 unsigned Opc0 = Load0->getMachineOpcode();
99 unsigned Opc1 = Load1->getMachineOpcode();
101 // Make sure both are actually loads.
102 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
105 if (isDS(Opc0) && isDS(Opc1)) {
107 // FIXME: Handle this case:
108 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
112 if (Load0->getOperand(1) != Load1->getOperand(1))
116 if (findChainOperand(Load0) != findChainOperand(Load1))
119 // Skip read2 / write2 variants for simplicity.
120 // TODO: We should report true if the used offsets are adjacent (excluded
122 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
123 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
126 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
127 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
131 if (isSMRD(Opc0) && isSMRD(Opc1)) {
132 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
135 if (Load0->getOperand(0) != Load1->getOperand(0))
138 const ConstantSDNode *Load0Offset =
139 dyn_cast<ConstantSDNode>(Load0->getOperand(1));
140 const ConstantSDNode *Load1Offset =
141 dyn_cast<ConstantSDNode>(Load1->getOperand(1));
143 if (!Load0Offset || !Load1Offset)
147 if (findChainOperand(Load0) != findChainOperand(Load1))
150 Offset0 = Load0Offset->getZExtValue();
151 Offset1 = Load1Offset->getZExtValue();
155 // MUBUF and MTBUF can access the same addresses.
156 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
158 // MUBUF and MTBUF have vaddr at different indices.
159 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
160 findChainOperand(Load0) != findChainOperand(Load1) ||
161 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
162 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
165 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
166 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
168 if (OffIdx0 == -1 || OffIdx1 == -1)
171 // getNamedOperandIdx returns the index for MachineInstrs. Since they
172 // inlcude the output in the operand list, but SDNodes don't, we need to
173 // subtract the index by one.
177 SDValue Off0 = Load0->getOperand(OffIdx0);
178 SDValue Off1 = Load1->getOperand(OffIdx1);
180 // The offset might be a FrameIndexSDNode.
181 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
184 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
185 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
192 static bool isStride64(unsigned Opc) {
194 case AMDGPU::DS_READ2ST64_B32:
195 case AMDGPU::DS_READ2ST64_B64:
196 case AMDGPU::DS_WRITE2ST64_B32:
197 case AMDGPU::DS_WRITE2ST64_B64:
204 bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
206 const TargetRegisterInfo *TRI) const {
207 unsigned Opc = LdSt->getOpcode();
210 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
211 AMDGPU::OpName::offset);
213 // Normal, single offset LDS instruction.
214 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
215 AMDGPU::OpName::addr);
217 BaseReg = AddrReg->getReg();
218 Offset = OffsetImm->getImm();
222 // The 2 offset instructions use offset0 and offset1 instead. We can treat
223 // these as a load with a single offset if the 2 offsets are consecutive. We
224 // will use this for some partially aligned loads.
225 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
226 AMDGPU::OpName::offset0);
227 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
228 AMDGPU::OpName::offset1);
230 uint8_t Offset0 = Offset0Imm->getImm();
231 uint8_t Offset1 = Offset1Imm->getImm();
233 if (Offset1 > Offset0 && Offset1 - Offset0 == 1) {
234 // Each of these offsets is in element sized units, so we need to convert
235 // to bytes of the individual reads.
239 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
241 assert(LdSt->mayStore());
242 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
243 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
249 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
250 AMDGPU::OpName::addr);
251 BaseReg = AddrReg->getReg();
252 Offset = EltSize * Offset0;
259 if (isMUBUF(*LdSt) || isMTBUF(*LdSt)) {
260 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
263 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
264 AMDGPU::OpName::vaddr);
268 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
269 AMDGPU::OpName::offset);
270 BaseReg = AddrReg->getReg();
271 Offset = OffsetImm->getImm();
276 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
277 AMDGPU::OpName::offset);
281 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
282 AMDGPU::OpName::sbase);
283 BaseReg = SBaseReg->getReg();
284 Offset = OffsetImm->getImm();
291 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
292 MachineInstr *SecondLdSt,
293 unsigned NumLoads) const {
294 // TODO: This needs finer tuning
298 if (isDS(*FirstLdSt) && isDS(*SecondLdSt))
301 if (isSMRD(*FirstLdSt) && isSMRD(*SecondLdSt))
304 if ((isMUBUF(*FirstLdSt) || isMTBUF(*FirstLdSt)) &&
305 (isMUBUF(*SecondLdSt) || isMTBUF(*SecondLdSt)))
312 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
313 MachineBasicBlock::iterator MI, DebugLoc DL,
314 unsigned DestReg, unsigned SrcReg,
315 bool KillSrc) const {
317 // If we are trying to copy to or from SCC, there is a bug somewhere else in
318 // the backend. While it may be theoretically possible to do this, it should
319 // never be necessary.
320 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
322 static const int16_t Sub0_15[] = {
323 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
324 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
325 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
326 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
329 static const int16_t Sub0_7[] = {
330 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
331 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
334 static const int16_t Sub0_3[] = {
335 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
338 static const int16_t Sub0_2[] = {
339 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
342 static const int16_t Sub0_1[] = {
343 AMDGPU::sub0, AMDGPU::sub1, 0
347 const int16_t *SubIndices;
349 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
350 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
351 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
352 .addReg(SrcReg, getKillRegState(KillSrc));
355 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
356 if (DestReg == AMDGPU::VCC) {
357 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
358 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
359 .addReg(SrcReg, getKillRegState(KillSrc));
361 // FIXME: Hack until VReg_1 removed.
362 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
363 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32))
365 .addReg(SrcReg, getKillRegState(KillSrc));
371 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
372 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
373 .addReg(SrcReg, getKillRegState(KillSrc));
376 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
377 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
378 Opcode = AMDGPU::S_MOV_B32;
381 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
382 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
383 Opcode = AMDGPU::S_MOV_B32;
386 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
387 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
388 Opcode = AMDGPU::S_MOV_B32;
389 SubIndices = Sub0_15;
391 } else if (AMDGPU::VGPR_32RegClass.contains(DestReg)) {
392 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
393 AMDGPU::SReg_32RegClass.contains(SrcReg));
394 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
395 .addReg(SrcReg, getKillRegState(KillSrc));
398 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
399 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
400 AMDGPU::SReg_64RegClass.contains(SrcReg));
401 Opcode = AMDGPU::V_MOV_B32_e32;
404 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
405 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
406 Opcode = AMDGPU::V_MOV_B32_e32;
409 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
410 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
411 AMDGPU::SReg_128RegClass.contains(SrcReg));
412 Opcode = AMDGPU::V_MOV_B32_e32;
415 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
416 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
417 AMDGPU::SReg_256RegClass.contains(SrcReg));
418 Opcode = AMDGPU::V_MOV_B32_e32;
421 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
422 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
423 AMDGPU::SReg_512RegClass.contains(SrcReg));
424 Opcode = AMDGPU::V_MOV_B32_e32;
425 SubIndices = Sub0_15;
428 llvm_unreachable("Can't copy register!");
431 while (unsigned SubIdx = *SubIndices++) {
432 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
433 get(Opcode), RI.getSubReg(DestReg, SubIdx));
435 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
438 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
442 int SIInstrInfo::commuteOpcode(const MachineInstr &MI) const {
443 const unsigned Opcode = MI.getOpcode();
447 // Try to map original to commuted opcode
448 NewOpc = AMDGPU::getCommuteRev(Opcode);
450 // Check if the commuted (REV) opcode exists on the target.
451 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
453 // Try to map commuted to original opcode
454 NewOpc = AMDGPU::getCommuteOrig(Opcode);
456 // Check if the original (non-REV) opcode exists on the target.
457 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
462 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
464 if (DstRC->getSize() == 4) {
465 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
466 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) {
467 return AMDGPU::S_MOV_B64;
468 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) {
469 return AMDGPU::V_MOV_B64_PSEUDO;
474 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
475 MachineBasicBlock::iterator MI,
476 unsigned SrcReg, bool isKill,
478 const TargetRegisterClass *RC,
479 const TargetRegisterInfo *TRI) const {
480 MachineFunction *MF = MBB.getParent();
481 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
482 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
483 DebugLoc DL = MBB.findDebugLoc(MI);
486 if (RI.isSGPRClass(RC)) {
487 MFI->setHasSpilledSGPRs();
489 // We are only allowed to create one new instruction when spilling
490 // registers, so we need to use pseudo instruction for spilling
492 switch (RC->getSize() * 8) {
493 case 32: Opcode = AMDGPU::SI_SPILL_S32_SAVE; break;
494 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
495 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
496 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
497 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
499 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
500 MFI->setHasSpilledVGPRs();
502 switch(RC->getSize() * 8) {
503 case 32: Opcode = AMDGPU::SI_SPILL_V32_SAVE; break;
504 case 64: Opcode = AMDGPU::SI_SPILL_V64_SAVE; break;
505 case 96: Opcode = AMDGPU::SI_SPILL_V96_SAVE; break;
506 case 128: Opcode = AMDGPU::SI_SPILL_V128_SAVE; break;
507 case 256: Opcode = AMDGPU::SI_SPILL_V256_SAVE; break;
508 case 512: Opcode = AMDGPU::SI_SPILL_V512_SAVE; break;
513 MachinePointerInfo PtrInfo
514 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
515 unsigned Size = FrameInfo->getObjectSize(FrameIndex);
516 unsigned Align = FrameInfo->getObjectAlignment(FrameIndex);
517 MachineMemOperand *MMO
518 = MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
521 FrameInfo->setObjectAlignment(FrameIndex, 4);
522 BuildMI(MBB, MI, DL, get(Opcode))
524 .addFrameIndex(FrameIndex)
525 // Place-holder registers, these will be filled in by
526 // SIPrepareScratchRegs.
527 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
528 .addReg(AMDGPU::SGPR0, RegState::Undef)
531 LLVMContext &Ctx = MF->getFunction()->getContext();
532 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
534 BuildMI(MBB, MI, DL, get(AMDGPU::KILL))
539 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
540 MachineBasicBlock::iterator MI,
541 unsigned DestReg, int FrameIndex,
542 const TargetRegisterClass *RC,
543 const TargetRegisterInfo *TRI) const {
544 MachineFunction *MF = MBB.getParent();
545 const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
546 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
547 DebugLoc DL = MBB.findDebugLoc(MI);
550 if (RI.isSGPRClass(RC)){
551 switch(RC->getSize() * 8) {
552 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
553 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
554 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
555 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
556 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
558 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
559 switch(RC->getSize() * 8) {
560 case 32: Opcode = AMDGPU::SI_SPILL_V32_RESTORE; break;
561 case 64: Opcode = AMDGPU::SI_SPILL_V64_RESTORE; break;
562 case 96: Opcode = AMDGPU::SI_SPILL_V96_RESTORE; break;
563 case 128: Opcode = AMDGPU::SI_SPILL_V128_RESTORE; break;
564 case 256: Opcode = AMDGPU::SI_SPILL_V256_RESTORE; break;
565 case 512: Opcode = AMDGPU::SI_SPILL_V512_RESTORE; break;
570 unsigned Align = FrameInfo->getObjectAlignment(FrameIndex);
571 unsigned Size = FrameInfo->getObjectSize(FrameIndex);
573 MachinePointerInfo PtrInfo
574 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
575 MachineMemOperand *MMO = MF->getMachineMemOperand(
576 PtrInfo, MachineMemOperand::MOLoad, Size, Align);
578 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
579 .addFrameIndex(FrameIndex)
580 // Place-holder registers, these will be filled in by
581 // SIPrepareScratchRegs.
582 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
583 .addReg(AMDGPU::SGPR0, RegState::Undef)
586 LLVMContext &Ctx = MF->getFunction()->getContext();
587 Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"
588 " restore register");
589 BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg);
593 /// \param @Offset Offset in bytes of the FrameIndex being spilled
594 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
595 MachineBasicBlock::iterator MI,
596 RegScavenger *RS, unsigned TmpReg,
597 unsigned FrameOffset,
598 unsigned Size) const {
599 MachineFunction *MF = MBB.getParent();
600 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
601 const AMDGPUSubtarget &ST = MF->getSubtarget<AMDGPUSubtarget>();
602 const SIRegisterInfo *TRI =
603 static_cast<const SIRegisterInfo*>(ST.getRegisterInfo());
604 DebugLoc DL = MBB.findDebugLoc(MI);
605 unsigned WorkGroupSize = MFI->getMaximumWorkGroupSize(*MF);
606 unsigned WavefrontSize = ST.getWavefrontSize();
608 unsigned TIDReg = MFI->getTIDReg();
609 if (!MFI->hasCalculatedTID()) {
610 MachineBasicBlock &Entry = MBB.getParent()->front();
611 MachineBasicBlock::iterator Insert = Entry.front();
612 DebugLoc DL = Insert->getDebugLoc();
614 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);
615 if (TIDReg == AMDGPU::NoRegister)
619 if (MFI->getShaderType() == ShaderType::COMPUTE &&
620 WorkGroupSize > WavefrontSize) {
622 unsigned TIDIGXReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_X);
623 unsigned TIDIGYReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Y);
624 unsigned TIDIGZReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Z);
625 unsigned InputPtrReg =
626 TRI->getPreloadedValue(*MF, SIRegisterInfo::INPUT_PTR);
627 for (unsigned Reg : {TIDIGXReg, TIDIGYReg, TIDIGZReg}) {
628 if (!Entry.isLiveIn(Reg))
629 Entry.addLiveIn(Reg);
632 RS->enterBasicBlock(&Entry);
633 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
634 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
635 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
637 .addImm(SI::KernelInputOffsets::NGROUPS_Z);
638 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
640 .addImm(SI::KernelInputOffsets::NGROUPS_Y);
642 // NGROUPS.X * NGROUPS.Y
643 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
646 // (NGROUPS.X * NGROUPS.Y) * TIDIG.X
647 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
650 // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)
651 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
655 // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z
656 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg)
661 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
666 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64),
672 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
676 MFI->setTIDReg(TIDReg);
679 // Add FrameIndex to LDS offset
680 unsigned LDSOffset = MFI->LDSSize + (FrameOffset * WorkGroupSize);
681 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg)
688 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
697 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
702 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
703 MachineBasicBlock &MBB = *MI->getParent();
704 DebugLoc DL = MBB.findDebugLoc(MI);
705 switch (MI->getOpcode()) {
706 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
708 case AMDGPU::SI_CONSTDATA_PTR: {
709 unsigned Reg = MI->getOperand(0).getReg();
710 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
711 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
713 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg);
715 // Add 32-bit offset from this instruction to the start of the constant data.
716 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_U32), RegLo)
718 .addTargetIndex(AMDGPU::TI_CONSTDATA_START)
719 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit);
720 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi)
723 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit)
724 .addReg(AMDGPU::SCC, RegState::Implicit);
725 MI->eraseFromParent();
728 case AMDGPU::SGPR_USE:
729 // This is just a placeholder for register allocation.
730 MI->eraseFromParent();
733 case AMDGPU::V_MOV_B64_PSEUDO: {
734 unsigned Dst = MI->getOperand(0).getReg();
735 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
736 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
738 const MachineOperand &SrcOp = MI->getOperand(1);
739 // FIXME: Will this work for 64-bit floating point immediates?
740 assert(!SrcOp.isFPImm());
742 APInt Imm(64, SrcOp.getImm());
743 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
744 .addImm(Imm.getLoBits(32).getZExtValue())
745 .addReg(Dst, RegState::Implicit);
746 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
747 .addImm(Imm.getHiBits(32).getZExtValue())
748 .addReg(Dst, RegState::Implicit);
750 assert(SrcOp.isReg());
751 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
752 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
753 .addReg(Dst, RegState::Implicit);
754 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
755 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
756 .addReg(Dst, RegState::Implicit);
758 MI->eraseFromParent();
762 case AMDGPU::V_CNDMASK_B64_PSEUDO: {
763 unsigned Dst = MI->getOperand(0).getReg();
764 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
765 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
766 unsigned Src0 = MI->getOperand(1).getReg();
767 unsigned Src1 = MI->getOperand(2).getReg();
768 const MachineOperand &SrcCond = MI->getOperand(3);
770 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
771 .addReg(RI.getSubReg(Src0, AMDGPU::sub0))
772 .addReg(RI.getSubReg(Src1, AMDGPU::sub0))
773 .addOperand(SrcCond);
774 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
775 .addReg(RI.getSubReg(Src0, AMDGPU::sub1))
776 .addReg(RI.getSubReg(Src1, AMDGPU::sub1))
777 .addOperand(SrcCond);
778 MI->eraseFromParent();
785 /// Commutes the operands in the given instruction.
786 /// The commutable operands are specified by their indices OpIdx0 and OpIdx1.
788 /// Do not call this method for a non-commutable instruction or for
789 /// non-commutable pair of operand indices OpIdx0 and OpIdx1.
790 /// Even though the instruction is commutable, the method may still
791 /// fail to commute the operands, null pointer is returned in such cases.
792 MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr *MI,
795 unsigned OpIdx1) const {
796 int CommutedOpcode = commuteOpcode(*MI);
797 if (CommutedOpcode == -1)
800 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
801 AMDGPU::OpName::src0);
802 MachineOperand &Src0 = MI->getOperand(Src0Idx);
806 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
807 AMDGPU::OpName::src1);
809 if ((OpIdx0 != static_cast<unsigned>(Src0Idx) ||
810 OpIdx1 != static_cast<unsigned>(Src1Idx)) &&
811 (OpIdx0 != static_cast<unsigned>(Src1Idx) ||
812 OpIdx1 != static_cast<unsigned>(Src0Idx)))
815 MachineOperand &Src1 = MI->getOperand(Src1Idx);
817 // Make sure it's legal to commute operands for VOP2.
819 (!isOperandLegal(MI, Src0Idx, &Src1) ||
820 !isOperandLegal(MI, Src1Idx, &Src0))) {
825 // Allow commuting instructions with Imm operands.
826 if (NewMI || !Src1.isImm() ||
827 (!isVOP2(*MI) && !isVOP3(*MI))) {
831 // Be sure to copy the source modifiers to the right place.
832 if (MachineOperand *Src0Mods
833 = getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) {
834 MachineOperand *Src1Mods
835 = getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers);
837 int Src0ModsVal = Src0Mods->getImm();
838 if (!Src1Mods && Src0ModsVal != 0)
841 // XXX - This assert might be a lie. It might be useful to have a neg
842 // modifier with 0.0.
843 int Src1ModsVal = Src1Mods->getImm();
844 assert((Src1ModsVal == 0) && "Not expecting modifiers with immediates");
846 Src1Mods->setImm(Src0ModsVal);
847 Src0Mods->setImm(Src1ModsVal);
850 unsigned Reg = Src0.getReg();
851 unsigned SubReg = Src0.getSubReg();
853 Src0.ChangeToImmediate(Src1.getImm());
855 llvm_unreachable("Should only have immediates");
857 Src1.ChangeToRegister(Reg, false);
858 Src1.setSubReg(SubReg);
860 MI = TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx0, OpIdx1);
864 MI->setDesc(get(CommutedOpcode));
869 // This needs to be implemented because the source modifiers may be inserted
870 // between the true commutable operands, and the base
871 // TargetInstrInfo::commuteInstruction uses it.
872 bool SIInstrInfo::findCommutedOpIndices(MachineInstr *MI,
874 unsigned &SrcOpIdx1) const {
875 const MCInstrDesc &MCID = MI->getDesc();
876 if (!MCID.isCommutable())
879 unsigned Opc = MI->getOpcode();
880 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
884 // FIXME: Workaround TargetInstrInfo::commuteInstruction asserting on
885 // immediate. Also, immediate src0 operand is not handled in
886 // SIInstrInfo::commuteInstruction();
887 if (!MI->getOperand(Src0Idx).isReg())
890 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
894 MachineOperand &Src1 = MI->getOperand(Src1Idx);
896 // SIInstrInfo::commuteInstruction() does support commuting the immediate
897 // operand src1 in 2 and 3 operand instructions.
898 if (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))
900 } else if (Src1.isReg()) {
901 // If any source modifiers are set, the generic instruction commuting won't
902 // understand how to copy the source modifiers.
903 if (hasModifiersSet(*MI, AMDGPU::OpName::src0_modifiers) ||
904 hasModifiersSet(*MI, AMDGPU::OpName::src1_modifiers))
909 return fixCommutedOpIndices(SrcOpIdx0, SrcOpIdx1, Src0Idx, Src1Idx);
912 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
913 MachineBasicBlock::iterator I,
915 unsigned SrcReg) const {
916 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
917 DstReg) .addReg(SrcReg);
920 bool SIInstrInfo::isMov(unsigned Opcode) const {
922 default: return false;
923 case AMDGPU::S_MOV_B32:
924 case AMDGPU::S_MOV_B64:
925 case AMDGPU::V_MOV_B32_e32:
926 case AMDGPU::V_MOV_B32_e64:
931 static void removeModOperands(MachineInstr &MI) {
932 unsigned Opc = MI.getOpcode();
933 int Src0ModIdx = AMDGPU::getNamedOperandIdx(Opc,
934 AMDGPU::OpName::src0_modifiers);
935 int Src1ModIdx = AMDGPU::getNamedOperandIdx(Opc,
936 AMDGPU::OpName::src1_modifiers);
937 int Src2ModIdx = AMDGPU::getNamedOperandIdx(Opc,
938 AMDGPU::OpName::src2_modifiers);
940 MI.RemoveOperand(Src2ModIdx);
941 MI.RemoveOperand(Src1ModIdx);
942 MI.RemoveOperand(Src0ModIdx);
945 bool SIInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
946 unsigned Reg, MachineRegisterInfo *MRI) const {
947 if (!MRI->hasOneNonDBGUse(Reg))
950 unsigned Opc = UseMI->getOpcode();
951 if (Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64) {
952 // Don't fold if we are using source modifiers. The new VOP2 instructions
954 if (hasModifiersSet(*UseMI, AMDGPU::OpName::src0_modifiers) ||
955 hasModifiersSet(*UseMI, AMDGPU::OpName::src1_modifiers) ||
956 hasModifiersSet(*UseMI, AMDGPU::OpName::src2_modifiers)) {
960 MachineOperand *Src0 = getNamedOperand(*UseMI, AMDGPU::OpName::src0);
961 MachineOperand *Src1 = getNamedOperand(*UseMI, AMDGPU::OpName::src1);
962 MachineOperand *Src2 = getNamedOperand(*UseMI, AMDGPU::OpName::src2);
964 // Multiplied part is the constant: Use v_madmk_f32
965 // We should only expect these to be on src0 due to canonicalizations.
966 if (Src0->isReg() && Src0->getReg() == Reg) {
967 if (!Src1->isReg() ||
968 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
971 if (!Src2->isReg() ||
972 (Src2->isReg() && RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))))
975 // We need to do some weird looking operand shuffling since the madmk
976 // operands are out of the normal expected order with the multiplied
977 // constant as the last operand.
979 // v_mad_f32 src0, src1, src2 -> v_madmk_f32 src0 * src2K + src1
984 const int64_t Imm = DefMI->getOperand(1).getImm();
986 // FIXME: This would be a lot easier if we could return a new instruction
987 // instead of having to modify in place.
989 // Remove these first since they are at the end.
990 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
991 AMDGPU::OpName::omod));
992 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
993 AMDGPU::OpName::clamp));
995 unsigned Src1Reg = Src1->getReg();
996 unsigned Src1SubReg = Src1->getSubReg();
997 unsigned Src2Reg = Src2->getReg();
998 unsigned Src2SubReg = Src2->getSubReg();
999 Src0->setReg(Src1Reg);
1000 Src0->setSubReg(Src1SubReg);
1001 Src0->setIsKill(Src1->isKill());
1003 Src1->setReg(Src2Reg);
1004 Src1->setSubReg(Src2SubReg);
1005 Src1->setIsKill(Src2->isKill());
1007 if (Opc == AMDGPU::V_MAC_F32_e64) {
1008 UseMI->untieRegOperand(
1009 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
1012 Src2->ChangeToImmediate(Imm);
1014 removeModOperands(*UseMI);
1015 UseMI->setDesc(get(AMDGPU::V_MADMK_F32));
1017 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1019 DefMI->eraseFromParent();
1024 // Added part is the constant: Use v_madak_f32
1025 if (Src2->isReg() && Src2->getReg() == Reg) {
1026 // Not allowed to use constant bus for another operand.
1027 // We can however allow an inline immediate as src0.
1028 if (!Src0->isImm() &&
1029 (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg()))))
1032 if (!Src1->isReg() ||
1033 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
1036 const int64_t Imm = DefMI->getOperand(1).getImm();
1038 // FIXME: This would be a lot easier if we could return a new instruction
1039 // instead of having to modify in place.
1041 // Remove these first since they are at the end.
1042 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1043 AMDGPU::OpName::omod));
1044 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1045 AMDGPU::OpName::clamp));
1047 if (Opc == AMDGPU::V_MAC_F32_e64) {
1048 UseMI->untieRegOperand(
1049 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
1052 // ChangingToImmediate adds Src2 back to the instruction.
1053 Src2->ChangeToImmediate(Imm);
1055 // These come before src2.
1056 removeModOperands(*UseMI);
1057 UseMI->setDesc(get(AMDGPU::V_MADAK_F32));
1059 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1061 DefMI->eraseFromParent();
1070 static bool offsetsDoNotOverlap(int WidthA, int OffsetA,
1071 int WidthB, int OffsetB) {
1072 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
1073 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
1074 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
1075 return LowOffset + LowWidth <= HighOffset;
1078 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
1079 MachineInstr *MIb) const {
1080 unsigned BaseReg0, Offset0;
1081 unsigned BaseReg1, Offset1;
1083 if (getMemOpBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) &&
1084 getMemOpBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) {
1085 assert(MIa->hasOneMemOperand() && MIb->hasOneMemOperand() &&
1086 "read2 / write2 not expected here yet");
1087 unsigned Width0 = (*MIa->memoperands_begin())->getSize();
1088 unsigned Width1 = (*MIb->memoperands_begin())->getSize();
1089 if (BaseReg0 == BaseReg1 &&
1090 offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) {
1098 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
1100 AliasAnalysis *AA) const {
1101 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
1102 "MIa must load from or modify a memory location");
1103 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
1104 "MIb must load from or modify a memory location");
1106 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects())
1109 // XXX - Can we relax this between address spaces?
1110 if (MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
1113 // TODO: Should we check the address space from the MachineMemOperand? That
1114 // would allow us to distinguish objects we know don't alias based on the
1115 // underlying address space, even if it was lowered to a different one,
1116 // e.g. private accesses lowered to use MUBUF instructions on a scratch
1120 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1122 return !isFLAT(*MIb);
1125 if (isMUBUF(*MIa) || isMTBUF(*MIa)) {
1126 if (isMUBUF(*MIb) || isMTBUF(*MIb))
1127 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1129 return !isFLAT(*MIb) && !isSMRD(*MIb);
1134 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1136 return !isFLAT(*MIb) && !isMUBUF(*MIa) && !isMTBUF(*MIa);
1141 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1149 MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB,
1150 MachineBasicBlock::iterator &MI,
1151 LiveVariables *LV) const {
1153 switch (MI->getOpcode()) {
1154 default: return nullptr;
1155 case AMDGPU::V_MAC_F32_e64: break;
1156 case AMDGPU::V_MAC_F32_e32: {
1157 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
1158 if (Src0->isImm() && !isInlineConstant(*Src0, 4))
1164 const MachineOperand *Dst = getNamedOperand(*MI, AMDGPU::OpName::dst);
1165 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
1166 const MachineOperand *Src1 = getNamedOperand(*MI, AMDGPU::OpName::src1);
1167 const MachineOperand *Src2 = getNamedOperand(*MI, AMDGPU::OpName::src2);
1169 return BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_MAD_F32))
1171 .addImm(0) // Src0 mods
1173 .addImm(0) // Src1 mods
1175 .addImm(0) // Src mods
1181 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
1182 int64_t SVal = Imm.getSExtValue();
1183 if (SVal >= -16 && SVal <= 64)
1186 if (Imm.getBitWidth() == 64) {
1187 uint64_t Val = Imm.getZExtValue();
1188 return (DoubleToBits(0.0) == Val) ||
1189 (DoubleToBits(1.0) == Val) ||
1190 (DoubleToBits(-1.0) == Val) ||
1191 (DoubleToBits(0.5) == Val) ||
1192 (DoubleToBits(-0.5) == Val) ||
1193 (DoubleToBits(2.0) == Val) ||
1194 (DoubleToBits(-2.0) == Val) ||
1195 (DoubleToBits(4.0) == Val) ||
1196 (DoubleToBits(-4.0) == Val);
1199 // The actual type of the operand does not seem to matter as long
1200 // as the bits match one of the inline immediate values. For example:
1202 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
1203 // so it is a legal inline immediate.
1205 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
1206 // floating-point, so it is a legal inline immediate.
1207 uint32_t Val = Imm.getZExtValue();
1209 return (FloatToBits(0.0f) == Val) ||
1210 (FloatToBits(1.0f) == Val) ||
1211 (FloatToBits(-1.0f) == Val) ||
1212 (FloatToBits(0.5f) == Val) ||
1213 (FloatToBits(-0.5f) == Val) ||
1214 (FloatToBits(2.0f) == Val) ||
1215 (FloatToBits(-2.0f) == Val) ||
1216 (FloatToBits(4.0f) == Val) ||
1217 (FloatToBits(-4.0f) == Val);
1220 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,
1221 unsigned OpSize) const {
1223 // MachineOperand provides no way to tell the true operand size, since it
1224 // only records a 64-bit value. We need to know the size to determine if a
1225 // 32-bit floating point immediate bit pattern is legal for an integer
1226 // immediate. It would be for any 32-bit integer operand, but would not be
1227 // for a 64-bit one.
1229 unsigned BitSize = 8 * OpSize;
1230 return isInlineConstant(APInt(BitSize, MO.getImm(), true));
1236 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO,
1237 unsigned OpSize) const {
1238 return MO.isImm() && !isInlineConstant(MO, OpSize);
1241 static bool compareMachineOp(const MachineOperand &Op0,
1242 const MachineOperand &Op1) {
1243 if (Op0.getType() != Op1.getType())
1246 switch (Op0.getType()) {
1247 case MachineOperand::MO_Register:
1248 return Op0.getReg() == Op1.getReg();
1249 case MachineOperand::MO_Immediate:
1250 return Op0.getImm() == Op1.getImm();
1252 llvm_unreachable("Didn't expect to be comparing these operand types");
1256 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
1257 const MachineOperand &MO) const {
1258 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
1260 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
1262 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
1265 if (OpInfo.RegClass < 0)
1268 unsigned OpSize = RI.getRegClass(OpInfo.RegClass)->getSize();
1269 if (isLiteralConstant(MO, OpSize))
1270 return RI.opCanUseLiteralConstant(OpInfo.OperandType);
1272 return RI.opCanUseInlineConstant(OpInfo.OperandType);
1275 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
1276 int Op32 = AMDGPU::getVOPe32(Opcode);
1280 return pseudoToMCOpcode(Op32) != -1;
1283 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
1284 // The src0_modifier operand is present on all instructions
1285 // that have modifiers.
1287 return AMDGPU::getNamedOperandIdx(Opcode,
1288 AMDGPU::OpName::src0_modifiers) != -1;
1291 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,
1292 unsigned OpName) const {
1293 const MachineOperand *Mods = getNamedOperand(MI, OpName);
1294 return Mods && Mods->getImm();
1297 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
1298 const MachineOperand &MO,
1299 unsigned OpSize) const {
1300 // Literal constants use the constant bus.
1301 if (isLiteralConstant(MO, OpSize))
1304 if (!MO.isReg() || !MO.isUse())
1307 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1308 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
1310 // FLAT_SCR is just an SGPR pair.
1311 if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
1314 // EXEC register uses the constant bus.
1315 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
1318 // SGPRs use the constant bus
1319 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
1320 (!MO.isImplicit() &&
1321 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
1322 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
1329 static unsigned findImplicitSGPRRead(const MachineInstr &MI) {
1330 for (const MachineOperand &MO : MI.implicit_operands()) {
1331 // We only care about reads.
1335 switch (MO.getReg()) {
1338 case AMDGPU::FLAT_SCR:
1346 return AMDGPU::NoRegister;
1349 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
1350 StringRef &ErrInfo) const {
1351 uint16_t Opcode = MI->getOpcode();
1352 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1353 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
1354 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
1355 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
1357 // Make sure the number of operands is correct.
1358 const MCInstrDesc &Desc = get(Opcode);
1359 if (!Desc.isVariadic() &&
1360 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
1361 ErrInfo = "Instruction has wrong number of operands.";
1365 // Make sure the register classes are correct
1366 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
1367 if (MI->getOperand(i).isFPImm()) {
1368 ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast "
1369 "all fp values to integers.";
1373 int RegClass = Desc.OpInfo[i].RegClass;
1375 switch (Desc.OpInfo[i].OperandType) {
1376 case MCOI::OPERAND_REGISTER:
1377 if (MI->getOperand(i).isImm()) {
1378 ErrInfo = "Illegal immediate value for operand.";
1382 case AMDGPU::OPERAND_REG_IMM32:
1384 case AMDGPU::OPERAND_REG_INLINE_C:
1385 if (isLiteralConstant(MI->getOperand(i),
1386 RI.getRegClass(RegClass)->getSize())) {
1387 ErrInfo = "Illegal immediate value for operand.";
1391 case MCOI::OPERAND_IMMEDIATE:
1392 // Check if this operand is an immediate.
1393 // FrameIndex operands will be replaced by immediates, so they are
1395 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFI()) {
1396 ErrInfo = "Expected immediate, but got non-immediate";
1404 if (!MI->getOperand(i).isReg())
1407 if (RegClass != -1) {
1408 unsigned Reg = MI->getOperand(i).getReg();
1409 if (TargetRegisterInfo::isVirtualRegister(Reg))
1412 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
1413 if (!RC->contains(Reg)) {
1414 ErrInfo = "Operand has incorrect register class.";
1422 if (isVOP1(*MI) || isVOP2(*MI) || isVOP3(*MI) || isVOPC(*MI)) {
1423 // Only look at the true operands. Only a real operand can use the constant
1424 // bus, and we don't want to check pseudo-operands like the source modifier
1426 const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
1428 unsigned ConstantBusCount = 0;
1429 unsigned SGPRUsed = findImplicitSGPRRead(*MI);
1430 if (SGPRUsed != AMDGPU::NoRegister)
1433 for (int OpIdx : OpIndices) {
1436 const MachineOperand &MO = MI->getOperand(OpIdx);
1437 if (usesConstantBus(MRI, MO, getOpSize(Opcode, OpIdx))) {
1439 if (MO.getReg() != SGPRUsed)
1441 SGPRUsed = MO.getReg();
1447 if (ConstantBusCount > 1) {
1448 ErrInfo = "VOP* instruction uses the constant bus more than once";
1453 // Verify misc. restrictions on specific instructions.
1454 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
1455 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
1456 const MachineOperand &Src0 = MI->getOperand(Src0Idx);
1457 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1458 const MachineOperand &Src2 = MI->getOperand(Src2Idx);
1459 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
1460 if (!compareMachineOp(Src0, Src1) &&
1461 !compareMachineOp(Src0, Src2)) {
1462 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
1468 // Make sure we aren't losing exec uses in the td files. This mostly requires
1469 // being careful when using let Uses to try to add other use registers.
1470 if (!isGenericOpcode(Opcode) && !isSALU(Opcode) && !isSMRD(Opcode)) {
1471 const MachineOperand *Exec = MI->findRegisterUseOperand(AMDGPU::EXEC);
1472 if (!Exec || !Exec->isImplicit()) {
1473 ErrInfo = "VALU instruction does not implicitly read exec mask";
1481 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
1482 switch (MI.getOpcode()) {
1483 default: return AMDGPU::INSTRUCTION_LIST_END;
1484 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
1485 case AMDGPU::COPY: return AMDGPU::COPY;
1486 case AMDGPU::PHI: return AMDGPU::PHI;
1487 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
1488 case AMDGPU::S_MOV_B32:
1489 return MI.getOperand(1).isReg() ?
1490 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
1491 case AMDGPU::S_ADD_I32:
1492 case AMDGPU::S_ADD_U32: return AMDGPU::V_ADD_I32_e32;
1493 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
1494 case AMDGPU::S_SUB_I32:
1495 case AMDGPU::S_SUB_U32: return AMDGPU::V_SUB_I32_e32;
1496 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
1497 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32;
1498 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
1499 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
1500 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
1501 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
1502 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
1503 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
1504 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
1505 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
1506 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
1507 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
1508 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
1509 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
1510 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
1511 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
1512 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
1513 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
1514 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
1515 case AMDGPU::S_BFM_B32: return AMDGPU::V_BFM_B32_e64;
1516 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
1517 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
1518 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
1519 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
1520 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
1521 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
1522 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
1523 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
1524 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
1525 case AMDGPU::S_LOAD_DWORD_IMM:
1526 case AMDGPU::S_LOAD_DWORD_SGPR:
1527 case AMDGPU::S_LOAD_DWORD_IMM_ci:
1528 return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1529 case AMDGPU::S_LOAD_DWORDX2_IMM:
1530 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1531 case AMDGPU::S_LOAD_DWORDX2_IMM_ci:
1532 return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1533 case AMDGPU::S_LOAD_DWORDX4_IMM:
1534 case AMDGPU::S_LOAD_DWORDX4_SGPR:
1535 case AMDGPU::S_LOAD_DWORDX4_IMM_ci:
1536 return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1537 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
1538 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
1539 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
1540 case AMDGPU::S_FLBIT_I32: return AMDGPU::V_FFBH_I32_e64;
1544 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
1545 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
1548 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
1549 unsigned OpNo) const {
1550 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1551 const MCInstrDesc &Desc = get(MI.getOpcode());
1552 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
1553 Desc.OpInfo[OpNo].RegClass == -1) {
1554 unsigned Reg = MI.getOperand(OpNo).getReg();
1556 if (TargetRegisterInfo::isVirtualRegister(Reg))
1557 return MRI.getRegClass(Reg);
1558 return RI.getPhysRegClass(Reg);
1561 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
1562 return RI.getRegClass(RCID);
1565 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
1566 switch (MI.getOpcode()) {
1568 case AMDGPU::REG_SEQUENCE:
1570 case AMDGPU::INSERT_SUBREG:
1571 return RI.hasVGPRs(getOpRegClass(MI, 0));
1573 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
1577 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
1578 MachineBasicBlock::iterator I = MI;
1579 MachineBasicBlock *MBB = MI->getParent();
1580 MachineOperand &MO = MI->getOperand(OpIdx);
1581 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1582 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
1583 const TargetRegisterClass *RC = RI.getRegClass(RCID);
1584 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1586 Opcode = AMDGPU::COPY;
1587 else if (RI.isSGPRClass(RC))
1588 Opcode = AMDGPU::S_MOV_B32;
1591 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
1592 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC))
1593 VRC = &AMDGPU::VReg_64RegClass;
1595 VRC = &AMDGPU::VGPR_32RegClass;
1597 unsigned Reg = MRI.createVirtualRegister(VRC);
1598 DebugLoc DL = MBB->findDebugLoc(I);
1599 BuildMI(*MI->getParent(), I, DL, get(Opcode), Reg)
1601 MO.ChangeToRegister(Reg, false);
1604 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
1605 MachineRegisterInfo &MRI,
1606 MachineOperand &SuperReg,
1607 const TargetRegisterClass *SuperRC,
1609 const TargetRegisterClass *SubRC)
1611 MachineBasicBlock *MBB = MI->getParent();
1612 DebugLoc DL = MI->getDebugLoc();
1613 unsigned SubReg = MRI.createVirtualRegister(SubRC);
1615 if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) {
1616 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1617 .addReg(SuperReg.getReg(), 0, SubIdx);
1621 // Just in case the super register is itself a sub-register, copy it to a new
1622 // value so we don't need to worry about merging its subreg index with the
1623 // SubIdx passed to this function. The register coalescer should be able to
1624 // eliminate this extra copy.
1625 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
1627 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
1628 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
1630 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1631 .addReg(NewSuperReg, 0, SubIdx);
1636 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
1637 MachineBasicBlock::iterator MII,
1638 MachineRegisterInfo &MRI,
1640 const TargetRegisterClass *SuperRC,
1642 const TargetRegisterClass *SubRC) const {
1644 // XXX - Is there a better way to do this?
1645 if (SubIdx == AMDGPU::sub0)
1646 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
1647 if (SubIdx == AMDGPU::sub1)
1648 return MachineOperand::CreateImm(Op.getImm() >> 32);
1650 llvm_unreachable("Unhandled register index for immediate");
1653 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
1655 return MachineOperand::CreateReg(SubReg, false);
1658 // Change the order of operands from (0, 1, 2) to (0, 2, 1)
1659 void SIInstrInfo::swapOperands(MachineBasicBlock::iterator Inst) const {
1660 assert(Inst->getNumExplicitOperands() == 3);
1661 MachineOperand Op1 = Inst->getOperand(1);
1662 Inst->RemoveOperand(1);
1663 Inst->addOperand(Op1);
1666 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1667 const MachineOperand *MO) const {
1668 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1669 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1670 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
1671 const TargetRegisterClass *DefinedRC =
1672 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
1674 MO = &MI->getOperand(OpIdx);
1677 usesConstantBus(MRI, *MO, DefinedRC->getSize())) {
1679 MO->isReg() ? MO->getReg() : (unsigned)AMDGPU::NoRegister;
1680 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1683 const MachineOperand &Op = MI->getOperand(i);
1684 if (Op.isReg() && Op.getReg() != SGPRUsed &&
1685 usesConstantBus(MRI, Op, getOpSize(*MI, i))) {
1693 const TargetRegisterClass *RC =
1694 TargetRegisterInfo::isVirtualRegister(MO->getReg()) ?
1695 MRI.getRegClass(MO->getReg()) :
1696 RI.getPhysRegClass(MO->getReg());
1698 // In order to be legal, the common sub-class must be equal to the
1699 // class of the current operand. For example:
1701 // v_mov_b32 s0 ; Operand defined as vsrc_32
1702 // ; RI.getCommonSubClass(s0,vsrc_32) = sgpr ; LEGAL
1704 // s_sendmsg 0, s0 ; Operand defined as m0reg
1705 // ; RI.getCommonSubClass(s0,m0reg) = m0reg ; NOT LEGAL
1707 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC;
1711 // Handle non-register types that are treated like immediates.
1712 assert(MO->isImm() || MO->isTargetIndex() || MO->isFI());
1715 // This operand expects an immediate.
1719 return isImmOperandLegal(MI, OpIdx, *MO);
1722 // Legalize VOP3 operands. Because all operand types are supported for any
1723 // operand, and since literal constants are not allowed and should never be
1724 // seen, we only need to worry about inserting copies if we use multiple SGPR
1726 void SIInstrInfo::legalizeOperandsVOP3(
1727 MachineRegisterInfo &MRI,
1728 MachineInstr *MI) const {
1729 unsigned Opc = MI->getOpcode();
1732 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0),
1733 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1),
1734 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)
1737 // Find the one SGPR operand we are allowed to use.
1738 unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx);
1740 for (unsigned i = 0; i < 3; ++i) {
1741 int Idx = VOP3Idx[i];
1744 MachineOperand &MO = MI->getOperand(Idx);
1746 // We should never see a VOP3 instruction with an illegal immediate operand.
1750 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1751 continue; // VGPRs are legal
1753 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1754 SGPRReg = MO.getReg();
1755 // We can use one SGPR in each VOP3 instruction.
1759 // If we make it this far, then the operand is not legal and we must
1761 legalizeOpWithMove(MI, Idx);
1765 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1766 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1767 unsigned Opc = MI->getOpcode();
1771 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
1772 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
1775 if (!isOperandLegal(MI, Src0Idx))
1776 legalizeOpWithMove(MI, Src0Idx);
1779 if (isOperandLegal(MI, Src1Idx))
1782 // Usually src0 of VOP2 instructions allow more types of inputs
1783 // than src1, so try to commute the instruction to decrease our
1784 // chances of having to insert a MOV instruction to legalize src1.
1785 if (MI->isCommutable()) {
1786 if (commuteInstruction(MI))
1787 // If we are successful in commuting, then we know MI is legal, so
1792 legalizeOpWithMove(MI, Src1Idx);
1798 legalizeOperandsVOP3(MRI, MI);
1802 // Legalize REG_SEQUENCE and PHI
1803 // The register class of the operands much be the same type as the register
1804 // class of the output.
1805 if (MI->getOpcode() == AMDGPU::PHI) {
1806 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1807 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1808 if (!MI->getOperand(i).isReg() ||
1809 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1811 const TargetRegisterClass *OpRC =
1812 MRI.getRegClass(MI->getOperand(i).getReg());
1813 if (RI.hasVGPRs(OpRC)) {
1820 // If any of the operands are VGPR registers, then they all most be
1821 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1823 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1826 VRC = RI.getEquivalentVGPRClass(SRC);
1833 // Update all the operands so they have the same type.
1834 for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
1835 MachineOperand &Op = MI->getOperand(I);
1836 if (!Op.isReg() || !TargetRegisterInfo::isVirtualRegister(Op.getReg()))
1838 unsigned DstReg = MRI.createVirtualRegister(RC);
1840 // MI is a PHI instruction.
1841 MachineBasicBlock *InsertBB = MI->getOperand(I + 1).getMBB();
1842 MachineBasicBlock::iterator Insert = InsertBB->getFirstTerminator();
1844 BuildMI(*InsertBB, Insert, MI->getDebugLoc(), get(AMDGPU::COPY), DstReg)
1850 // REG_SEQUENCE doesn't really require operand legalization, but if one has a
1851 // VGPR dest type and SGPR sources, insert copies so all operands are
1852 // VGPRs. This seems to help operand folding / the register coalescer.
1853 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1854 MachineBasicBlock *MBB = MI->getParent();
1855 const TargetRegisterClass *DstRC = getOpRegClass(*MI, 0);
1856 if (RI.hasVGPRs(DstRC)) {
1857 // Update all the operands so they are VGPR register classes. These may
1858 // not be the same register class because REG_SEQUENCE supports mixing
1859 // subregister index types e.g. sub0_sub1 + sub2 + sub3
1860 for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
1861 MachineOperand &Op = MI->getOperand(I);
1862 if (!Op.isReg() || !TargetRegisterInfo::isVirtualRegister(Op.getReg()))
1865 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg());
1866 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC);
1870 unsigned DstReg = MRI.createVirtualRegister(VRC);
1872 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), DstReg)
1883 // Legalize INSERT_SUBREG
1884 // src0 must have the same register class as dst
1885 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
1886 unsigned Dst = MI->getOperand(0).getReg();
1887 unsigned Src0 = MI->getOperand(1).getReg();
1888 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1889 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1890 if (DstRC != Src0RC) {
1891 MachineBasicBlock &MBB = *MI->getParent();
1892 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
1893 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
1895 MI->getOperand(1).setReg(NewSrc0);
1900 // Legalize MUBUF* instructions
1901 // FIXME: If we start using the non-addr64 instructions for compute, we
1902 // may need to legalize them here.
1904 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc);
1905 if (SRsrcIdx != -1) {
1906 // We have an MUBUF instruction
1907 MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx);
1908 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass;
1909 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()),
1910 RI.getRegClass(SRsrcRC))) {
1911 // The operands are legal.
1912 // FIXME: We may need to legalize operands besided srsrc.
1916 MachineBasicBlock &MBB = *MI->getParent();
1918 // Extract the ptr from the resource descriptor.
1919 unsigned SRsrcPtr = buildExtractSubReg(MI, MRI, *SRsrc,
1920 &AMDGPU::VReg_128RegClass, AMDGPU::sub0_sub1, &AMDGPU::VReg_64RegClass);
1922 // Create an empty resource descriptor
1923 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1924 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1925 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1926 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1927 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
1930 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1934 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1935 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1937 .addImm(RsrcDataFormat & 0xFFFFFFFF);
1939 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1940 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1942 .addImm(RsrcDataFormat >> 32);
1944 // NewSRsrc = {Zero64, SRsrcFormat}
1945 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewSRsrc)
1947 .addImm(AMDGPU::sub0_sub1)
1948 .addReg(SRsrcFormatLo)
1949 .addImm(AMDGPU::sub2)
1950 .addReg(SRsrcFormatHi)
1951 .addImm(AMDGPU::sub3);
1953 MachineOperand *VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1954 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
1956 // This is already an ADDR64 instruction so we need to add the pointer
1957 // extracted from the resource descriptor to the current value of VAddr.
1958 unsigned NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1959 unsigned NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1961 // NewVaddrLo = SRsrcPtr:sub0 + VAddr:sub0
1962 DebugLoc DL = MI->getDebugLoc();
1963 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), NewVAddrLo)
1964 .addReg(SRsrcPtr, 0, AMDGPU::sub0)
1965 .addReg(VAddr->getReg(), 0, AMDGPU::sub0);
1967 // NewVaddrHi = SRsrcPtr:sub1 + VAddr:sub1
1968 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADDC_U32_e32), NewVAddrHi)
1969 .addReg(SRsrcPtr, 0, AMDGPU::sub1)
1970 .addReg(VAddr->getReg(), 0, AMDGPU::sub1);
1972 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1973 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
1975 .addImm(AMDGPU::sub0)
1977 .addImm(AMDGPU::sub1);
1979 // This instructions is the _OFFSET variant, so we need to convert it to
1981 assert(MBB.getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration()
1982 < AMDGPUSubtarget::VOLCANIC_ISLANDS &&
1983 "FIXME: Need to emit flat atomics here");
1985 MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata);
1986 MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset);
1987 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset);
1988 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
1990 // Atomics rith return have have an additional tied operand and are
1991 // missing some of the special bits.
1992 MachineOperand *VDataIn = getNamedOperand(*MI, AMDGPU::OpName::vdata_in);
1993 MachineInstr *Addr64;
1996 // Regular buffer load / store.
1997 MachineInstrBuilder MIB
1998 = BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
2000 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
2001 // This will be replaced later
2002 // with the new value of vaddr.
2004 .addOperand(*SOffset)
2005 .addOperand(*Offset);
2007 // Atomics do not have this operand.
2008 if (const MachineOperand *GLC
2009 = getNamedOperand(*MI, AMDGPU::OpName::glc)) {
2010 MIB.addImm(GLC->getImm());
2013 MIB.addImm(getNamedImmOperand(*MI, AMDGPU::OpName::slc));
2015 if (const MachineOperand *TFE
2016 = getNamedOperand(*MI, AMDGPU::OpName::tfe)) {
2017 MIB.addImm(TFE->getImm());
2020 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
2023 // Atomics with return.
2024 Addr64 = BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
2026 .addOperand(*VDataIn)
2027 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
2028 // This will be replaced later
2029 // with the new value of vaddr.
2031 .addOperand(*SOffset)
2032 .addOperand(*Offset)
2033 .addImm(getNamedImmOperand(*MI, AMDGPU::OpName::slc))
2034 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
2037 MI->removeFromParent();
2040 // NewVaddr = {NewVaddrHi, NewVaddrLo}
2041 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
2042 .addReg(SRsrcPtr, 0, AMDGPU::sub0)
2043 .addImm(AMDGPU::sub0)
2044 .addReg(SRsrcPtr, 0, AMDGPU::sub1)
2045 .addImm(AMDGPU::sub1);
2047 VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
2048 SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc);
2051 // Update the instruction to use NewVaddr
2052 VAddr->setReg(NewVAddr);
2053 // Update the instruction to use NewSRsrc
2054 SRsrc->setReg(NewSRsrc);
2058 void SIInstrInfo::splitSMRD(MachineInstr *MI,
2059 const TargetRegisterClass *HalfRC,
2060 unsigned HalfImmOp, unsigned HalfSGPROp,
2061 MachineInstr *&Lo, MachineInstr *&Hi) const {
2063 DebugLoc DL = MI->getDebugLoc();
2064 MachineBasicBlock *MBB = MI->getParent();
2065 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2066 unsigned RegLo = MRI.createVirtualRegister(HalfRC);
2067 unsigned RegHi = MRI.createVirtualRegister(HalfRC);
2068 unsigned HalfSize = HalfRC->getSize();
2069 const MachineOperand *OffOp =
2070 getNamedOperand(*MI, AMDGPU::OpName::offset);
2071 const MachineOperand *SBase = getNamedOperand(*MI, AMDGPU::OpName::sbase);
2073 // The SMRD has an 8-bit offset in dwords on SI and a 20-bit offset in bytes
2076 bool IsKill = SBase->isKill();
2079 MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() >=
2080 AMDGPUSubtarget::VOLCANIC_ISLANDS;
2081 unsigned OffScale = isVI ? 1 : 4;
2082 // Handle the _IMM variant
2083 unsigned LoOffset = OffOp->getImm() * OffScale;
2084 unsigned HiOffset = LoOffset + HalfSize;
2085 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo)
2086 // Use addReg instead of addOperand
2087 // to make sure kill flag is cleared.
2088 .addReg(SBase->getReg(), 0, SBase->getSubReg())
2089 .addImm(LoOffset / OffScale);
2091 if (!isUInt<20>(HiOffset) || (!isVI && !isUInt<8>(HiOffset / OffScale))) {
2092 unsigned OffsetSGPR =
2093 MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
2094 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR)
2095 .addImm(HiOffset); // The offset in register is in bytes.
2096 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
2097 .addReg(SBase->getReg(), getKillRegState(IsKill),
2099 .addReg(OffsetSGPR);
2101 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi)
2102 .addReg(SBase->getReg(), getKillRegState(IsKill),
2104 .addImm(HiOffset / OffScale);
2107 // Handle the _SGPR variant
2108 MachineOperand *SOff = getNamedOperand(*MI, AMDGPU::OpName::soff);
2109 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo)
2110 .addReg(SBase->getReg(), 0, SBase->getSubReg())
2112 unsigned OffsetSGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
2113 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR)
2114 .addReg(SOff->getReg(), 0, SOff->getSubReg())
2116 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
2117 .addReg(SBase->getReg(), getKillRegState(IsKill),
2119 .addReg(OffsetSGPR);
2122 unsigned SubLo, SubHi;
2123 const TargetRegisterClass *NewDstRC;
2126 SubLo = AMDGPU::sub0;
2127 SubHi = AMDGPU::sub1;
2128 NewDstRC = &AMDGPU::VReg_64RegClass;
2131 SubLo = AMDGPU::sub0_sub1;
2132 SubHi = AMDGPU::sub2_sub3;
2133 NewDstRC = &AMDGPU::VReg_128RegClass;
2136 SubLo = AMDGPU::sub0_sub1_sub2_sub3;
2137 SubHi = AMDGPU::sub4_sub5_sub6_sub7;
2138 NewDstRC = &AMDGPU::VReg_256RegClass;
2141 SubLo = AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7;
2142 SubHi = AMDGPU::sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15;
2143 NewDstRC = &AMDGPU::VReg_512RegClass;
2146 llvm_unreachable("Unhandled HalfSize");
2149 unsigned OldDst = MI->getOperand(0).getReg();
2150 unsigned NewDst = MRI.createVirtualRegister(NewDstRC);
2152 MRI.replaceRegWith(OldDst, NewDst);
2154 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), NewDst)
2161 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI,
2162 MachineRegisterInfo &MRI,
2163 SmallVectorImpl<MachineInstr *> &Worklist) const {
2164 MachineBasicBlock *MBB = MI->getParent();
2165 int DstIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
2166 assert(DstIdx != -1);
2167 unsigned DstRCID = get(MI->getOpcode()).OpInfo[DstIdx].RegClass;
2168 switch(RI.getRegClass(DstRCID)->getSize()) {
2172 unsigned NewOpcode = getVALUOp(*MI);
2176 if (MI->getOperand(2).isReg()) {
2177 RegOffset = MI->getOperand(2).getReg();
2180 assert(MI->getOperand(2).isImm());
2181 // SMRD instructions take a dword offsets on SI and byte offset on VI
2182 // and MUBUF instructions always take a byte offset.
2183 ImmOffset = MI->getOperand(2).getImm();
2184 if (MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() <=
2185 AMDGPUSubtarget::SEA_ISLANDS)
2187 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2189 if (isUInt<12>(ImmOffset)) {
2190 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2194 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2201 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
2202 unsigned DWord0 = RegOffset;
2203 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2204 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2205 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2206 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
2208 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
2210 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
2211 .addImm(RsrcDataFormat & 0xFFFFFFFF);
2212 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
2213 .addImm(RsrcDataFormat >> 32);
2214 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
2216 .addImm(AMDGPU::sub0)
2218 .addImm(AMDGPU::sub1)
2220 .addImm(AMDGPU::sub2)
2222 .addImm(AMDGPU::sub3);
2224 const MCInstrDesc &NewInstDesc = get(NewOpcode);
2225 const TargetRegisterClass *NewDstRC
2226 = RI.getRegClass(NewInstDesc.OpInfo[0].RegClass);
2227 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2228 unsigned DstReg = MI->getOperand(0).getReg();
2229 MRI.replaceRegWith(DstReg, NewDstReg);
2231 MachineInstr *NewInst =
2232 BuildMI(*MBB, MI, MI->getDebugLoc(), NewInstDesc, NewDstReg)
2233 .addOperand(MI->getOperand(1)) // sbase
2240 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
2241 MI->eraseFromParent();
2243 legalizeOperands(NewInst);
2244 addUsersToMoveToVALUWorklist(NewDstReg, MRI, Worklist);
2248 MachineInstr *Lo, *Hi;
2249 splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
2250 AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
2251 MI->eraseFromParent();
2252 moveSMRDToVALU(Lo, MRI, Worklist);
2253 moveSMRDToVALU(Hi, MRI, Worklist);
2258 MachineInstr *Lo, *Hi;
2259 splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
2260 AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
2261 MI->eraseFromParent();
2262 moveSMRDToVALU(Lo, MRI, Worklist);
2263 moveSMRDToVALU(Hi, MRI, Worklist);
2269 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
2270 SmallVector<MachineInstr *, 128> Worklist;
2271 Worklist.push_back(&TopInst);
2273 while (!Worklist.empty()) {
2274 MachineInstr *Inst = Worklist.pop_back_val();
2275 MachineBasicBlock *MBB = Inst->getParent();
2276 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2278 unsigned Opcode = Inst->getOpcode();
2279 unsigned NewOpcode = getVALUOp(*Inst);
2281 // Handle some special cases
2284 if (isSMRD(*Inst)) {
2285 moveSMRDToVALU(Inst, MRI, Worklist);
2289 case AMDGPU::S_AND_B64:
2290 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_AND_B32_e64);
2291 Inst->eraseFromParent();
2294 case AMDGPU::S_OR_B64:
2295 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_OR_B32_e64);
2296 Inst->eraseFromParent();
2299 case AMDGPU::S_XOR_B64:
2300 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_XOR_B32_e64);
2301 Inst->eraseFromParent();
2304 case AMDGPU::S_NOT_B64:
2305 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::V_NOT_B32_e32);
2306 Inst->eraseFromParent();
2309 case AMDGPU::S_BCNT1_I32_B64:
2310 splitScalar64BitBCNT(Worklist, Inst);
2311 Inst->eraseFromParent();
2314 case AMDGPU::S_BFE_I64: {
2315 splitScalar64BitBFE(Worklist, Inst);
2316 Inst->eraseFromParent();
2320 case AMDGPU::S_LSHL_B32:
2321 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2322 NewOpcode = AMDGPU::V_LSHLREV_B32_e64;
2326 case AMDGPU::S_ASHR_I32:
2327 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2328 NewOpcode = AMDGPU::V_ASHRREV_I32_e64;
2332 case AMDGPU::S_LSHR_B32:
2333 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2334 NewOpcode = AMDGPU::V_LSHRREV_B32_e64;
2338 case AMDGPU::S_LSHL_B64:
2339 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2340 NewOpcode = AMDGPU::V_LSHLREV_B64;
2344 case AMDGPU::S_ASHR_I64:
2345 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2346 NewOpcode = AMDGPU::V_ASHRREV_I64;
2350 case AMDGPU::S_LSHR_B64:
2351 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2352 NewOpcode = AMDGPU::V_LSHRREV_B64;
2357 case AMDGPU::S_BFE_U64:
2358 case AMDGPU::S_BFM_B64:
2359 llvm_unreachable("Moving this op to VALU not implemented");
2362 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
2363 // We cannot move this instruction to the VALU, so we should try to
2364 // legalize its operands instead.
2365 legalizeOperands(Inst);
2369 // Use the new VALU Opcode.
2370 const MCInstrDesc &NewDesc = get(NewOpcode);
2371 Inst->setDesc(NewDesc);
2373 // Remove any references to SCC. Vector instructions can't read from it, and
2374 // We're just about to add the implicit use / defs of VCC, and we don't want
2376 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
2377 MachineOperand &Op = Inst->getOperand(i);
2378 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
2379 Inst->RemoveOperand(i);
2382 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
2383 // We are converting these to a BFE, so we need to add the missing
2384 // operands for the size and offset.
2385 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
2386 Inst->addOperand(MachineOperand::CreateImm(0));
2387 Inst->addOperand(MachineOperand::CreateImm(Size));
2389 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
2390 // The VALU version adds the second operand to the result, so insert an
2392 Inst->addOperand(MachineOperand::CreateImm(0));
2395 Inst->addImplicitDefUseOperands(*Inst->getParent()->getParent());
2397 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
2398 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
2399 // If we need to move this to VGPRs, we need to unpack the second operand
2400 // back into the 2 separate ones for bit offset and width.
2401 assert(OffsetWidthOp.isImm() &&
2402 "Scalar BFE is only implemented for constant width and offset");
2403 uint32_t Imm = OffsetWidthOp.getImm();
2405 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2406 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2407 Inst->RemoveOperand(2); // Remove old immediate.
2408 Inst->addOperand(MachineOperand::CreateImm(Offset));
2409 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
2412 // Update the destination register class.
2413 const TargetRegisterClass *NewDstRC = getDestEquivalentVGPRClass(*Inst);
2417 unsigned DstReg = Inst->getOperand(0).getReg();
2418 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2419 MRI.replaceRegWith(DstReg, NewDstReg);
2421 // Legalize the operands
2422 legalizeOperands(Inst);
2424 addUsersToMoveToVALUWorklist(NewDstReg, MRI, Worklist);
2428 //===----------------------------------------------------------------------===//
2429 // Indirect addressing callbacks
2430 //===----------------------------------------------------------------------===//
2432 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
2433 unsigned Channel) const {
2434 assert(Channel == 0);
2438 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
2439 return &AMDGPU::VGPR_32RegClass;
2442 void SIInstrInfo::splitScalar64BitUnaryOp(
2443 SmallVectorImpl<MachineInstr *> &Worklist,
2445 unsigned Opcode) const {
2446 MachineBasicBlock &MBB = *Inst->getParent();
2447 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2449 MachineOperand &Dest = Inst->getOperand(0);
2450 MachineOperand &Src0 = Inst->getOperand(1);
2451 DebugLoc DL = Inst->getDebugLoc();
2453 MachineBasicBlock::iterator MII = Inst;
2455 const MCInstrDesc &InstDesc = get(Opcode);
2456 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2457 MRI.getRegClass(Src0.getReg()) :
2458 &AMDGPU::SGPR_32RegClass;
2460 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2462 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2463 AMDGPU::sub0, Src0SubRC);
2465 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2466 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
2467 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
2469 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
2470 BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2471 .addOperand(SrcReg0Sub0);
2473 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2474 AMDGPU::sub1, Src0SubRC);
2476 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
2477 BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2478 .addOperand(SrcReg0Sub1);
2480 unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC);
2481 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2483 .addImm(AMDGPU::sub0)
2485 .addImm(AMDGPU::sub1);
2487 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2489 // We don't need to legalizeOperands here because for a single operand, src0
2490 // will support any kind of input.
2492 // Move all users of this moved value.
2493 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
2496 void SIInstrInfo::splitScalar64BitBinaryOp(
2497 SmallVectorImpl<MachineInstr *> &Worklist,
2499 unsigned Opcode) const {
2500 MachineBasicBlock &MBB = *Inst->getParent();
2501 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2503 MachineOperand &Dest = Inst->getOperand(0);
2504 MachineOperand &Src0 = Inst->getOperand(1);
2505 MachineOperand &Src1 = Inst->getOperand(2);
2506 DebugLoc DL = Inst->getDebugLoc();
2508 MachineBasicBlock::iterator MII = Inst;
2510 const MCInstrDesc &InstDesc = get(Opcode);
2511 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2512 MRI.getRegClass(Src0.getReg()) :
2513 &AMDGPU::SGPR_32RegClass;
2515 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2516 const TargetRegisterClass *Src1RC = Src1.isReg() ?
2517 MRI.getRegClass(Src1.getReg()) :
2518 &AMDGPU::SGPR_32RegClass;
2520 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
2522 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2523 AMDGPU::sub0, Src0SubRC);
2524 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2525 AMDGPU::sub0, Src1SubRC);
2527 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2528 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
2529 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
2531 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
2532 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2533 .addOperand(SrcReg0Sub0)
2534 .addOperand(SrcReg1Sub0);
2536 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2537 AMDGPU::sub1, Src0SubRC);
2538 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2539 AMDGPU::sub1, Src1SubRC);
2541 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
2542 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2543 .addOperand(SrcReg0Sub1)
2544 .addOperand(SrcReg1Sub1);
2546 unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC);
2547 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2549 .addImm(AMDGPU::sub0)
2551 .addImm(AMDGPU::sub1);
2553 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2555 // Try to legalize the operands in case we need to swap the order to keep it
2557 legalizeOperands(LoHalf);
2558 legalizeOperands(HiHalf);
2560 // Move all users of this moved vlaue.
2561 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
2564 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
2565 MachineInstr *Inst) const {
2566 MachineBasicBlock &MBB = *Inst->getParent();
2567 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2569 MachineBasicBlock::iterator MII = Inst;
2570 DebugLoc DL = Inst->getDebugLoc();
2572 MachineOperand &Dest = Inst->getOperand(0);
2573 MachineOperand &Src = Inst->getOperand(1);
2575 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
2576 const TargetRegisterClass *SrcRC = Src.isReg() ?
2577 MRI.getRegClass(Src.getReg()) :
2578 &AMDGPU::SGPR_32RegClass;
2580 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2581 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2583 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
2585 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2586 AMDGPU::sub0, SrcSubRC);
2587 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2588 AMDGPU::sub1, SrcSubRC);
2590 BuildMI(MBB, MII, DL, InstDesc, MidReg)
2591 .addOperand(SrcRegSub0)
2594 BuildMI(MBB, MII, DL, InstDesc, ResultReg)
2595 .addOperand(SrcRegSub1)
2598 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2600 // We don't need to legalize operands here. src0 for etiher instruction can be
2601 // an SGPR, and the second input is unused or determined here.
2602 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2605 void SIInstrInfo::splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
2606 MachineInstr *Inst) const {
2607 MachineBasicBlock &MBB = *Inst->getParent();
2608 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2609 MachineBasicBlock::iterator MII = Inst;
2610 DebugLoc DL = Inst->getDebugLoc();
2612 MachineOperand &Dest = Inst->getOperand(0);
2613 uint32_t Imm = Inst->getOperand(2).getImm();
2614 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2615 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2619 // Only sext_inreg cases handled.
2620 assert(Inst->getOpcode() == AMDGPU::S_BFE_I64 &&
2625 if (BitWidth < 32) {
2626 unsigned MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2627 unsigned MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2628 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2630 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo)
2631 .addReg(Inst->getOperand(1).getReg(), 0, AMDGPU::sub0)
2635 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi)
2639 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2641 .addImm(AMDGPU::sub0)
2643 .addImm(AMDGPU::sub1);
2645 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2646 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2650 MachineOperand &Src = Inst->getOperand(1);
2651 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2652 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2654 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
2656 .addReg(Src.getReg(), 0, AMDGPU::sub0);
2658 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2659 .addReg(Src.getReg(), 0, AMDGPU::sub0)
2660 .addImm(AMDGPU::sub0)
2662 .addImm(AMDGPU::sub1);
2664 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2665 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2668 void SIInstrInfo::addUsersToMoveToVALUWorklist(
2670 MachineRegisterInfo &MRI,
2671 SmallVectorImpl<MachineInstr *> &Worklist) const {
2672 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(DstReg),
2673 E = MRI.use_end(); I != E; ++I) {
2674 MachineInstr &UseMI = *I->getParent();
2675 if (!canReadVGPR(UseMI, I.getOperandNo())) {
2676 Worklist.push_back(&UseMI);
2681 const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass(
2682 const MachineInstr &Inst) const {
2683 const TargetRegisterClass *NewDstRC = getOpRegClass(Inst, 0);
2685 switch (Inst.getOpcode()) {
2686 // For target instructions, getOpRegClass just returns the virtual register
2687 // class associated with the operand, so we need to find an equivalent VGPR
2688 // register class in order to move the instruction to the VALU.
2691 case AMDGPU::REG_SEQUENCE:
2692 case AMDGPU::INSERT_SUBREG:
2693 if (RI.hasVGPRs(NewDstRC))
2696 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
2705 // Find the one SGPR operand we are allowed to use.
2706 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
2707 int OpIndices[3]) const {
2708 const MCInstrDesc &Desc = MI->getDesc();
2710 // Find the one SGPR operand we are allowed to use.
2712 // First we need to consider the instruction's operand requirements before
2713 // legalizing. Some operands are required to be SGPRs, such as implicit uses
2714 // of VCC, but we are still bound by the constant bus requirement to only use
2717 // If the operand's class is an SGPR, we can never move it.
2719 unsigned SGPRReg = findImplicitSGPRRead(*MI);
2720 if (SGPRReg != AMDGPU::NoRegister)
2723 unsigned UsedSGPRs[3] = { AMDGPU::NoRegister };
2724 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
2726 for (unsigned i = 0; i < 3; ++i) {
2727 int Idx = OpIndices[i];
2731 const MachineOperand &MO = MI->getOperand(Idx);
2735 // Is this operand statically required to be an SGPR based on the operand
2737 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass);
2738 bool IsRequiredSGPR = RI.isSGPRClass(OpRC);
2742 // If this could be a VGPR or an SGPR, Check the dynamic register class.
2743 unsigned Reg = MO.getReg();
2744 const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);
2745 if (RI.isSGPRClass(RegRC))
2749 // We don't have a required SGPR operand, so we have a bit more freedom in
2750 // selecting operands to move.
2752 // Try to select the most used SGPR. If an SGPR is equal to one of the
2753 // others, we choose that.
2756 // V_FMA_F32 v0, s0, s0, s0 -> No moves
2757 // V_FMA_F32 v0, s0, s1, s0 -> Move s1
2759 // TODO: If some of the operands are 64-bit SGPRs and some 32, we should
2762 if (UsedSGPRs[0] != AMDGPU::NoRegister) {
2763 if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2])
2764 SGPRReg = UsedSGPRs[0];
2767 if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) {
2768 if (UsedSGPRs[1] == UsedSGPRs[2])
2769 SGPRReg = UsedSGPRs[1];
2775 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
2776 MachineBasicBlock *MBB,
2777 MachineBasicBlock::iterator I,
2779 unsigned Address, unsigned OffsetReg) const {
2780 const DebugLoc &DL = MBB->findDebugLoc(I);
2781 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2782 getIndirectIndexBegin(*MBB->getParent()));
2784 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
2785 .addReg(IndirectBaseReg, RegState::Define)
2786 .addOperand(I->getOperand(0))
2787 .addReg(IndirectBaseReg)
2793 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
2794 MachineBasicBlock *MBB,
2795 MachineBasicBlock::iterator I,
2797 unsigned Address, unsigned OffsetReg) const {
2798 const DebugLoc &DL = MBB->findDebugLoc(I);
2799 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2800 getIndirectIndexBegin(*MBB->getParent()));
2802 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC_V1))
2803 .addOperand(I->getOperand(0))
2804 .addOperand(I->getOperand(1))
2805 .addReg(IndirectBaseReg)
2811 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
2812 const MachineFunction &MF) const {
2813 int End = getIndirectIndexEnd(MF);
2814 int Begin = getIndirectIndexBegin(MF);
2820 for (int Index = Begin; Index <= End; ++Index)
2821 Reserved.set(AMDGPU::VGPR_32RegClass.getRegister(Index));
2823 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
2824 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
2826 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
2827 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
2829 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
2830 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
2832 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
2833 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
2835 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
2836 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
2839 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
2840 unsigned OperandName) const {
2841 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
2845 return &MI.getOperand(Idx);
2848 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {
2849 uint64_t RsrcDataFormat = AMDGPU::RSRC_DATA_FORMAT;
2850 if (ST.isAmdHsaOS()) {
2851 RsrcDataFormat |= (1ULL << 56);
2853 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2855 RsrcDataFormat |= (2ULL << 59);
2858 return RsrcDataFormat;
2861 uint64_t SIInstrInfo::getScratchRsrcWords23() const {
2862 uint64_t Rsrc23 = getDefaultRsrcDataFormat() |
2863 AMDGPU::RSRC_TID_ENABLE |
2864 0xffffffff; // Size;
2866 // If TID_ENABLE is set, DATA_FORMAT specifies stride bits [14:17].
2867 // Clear them unless we want a huge stride.
2868 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2869 Rsrc23 &= ~AMDGPU::RSRC_DATA_FORMAT;