1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/Support/Debug.h"
30 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
31 : AMDGPUInstrInfo(st), RI() {}
33 //===----------------------------------------------------------------------===//
34 // TargetInstrInfo callbacks
35 //===----------------------------------------------------------------------===//
37 static unsigned getNumOperandsNoGlue(SDNode *Node) {
38 unsigned N = Node->getNumOperands();
39 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
44 static SDValue findChainOperand(SDNode *Load) {
45 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1);
46 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
50 /// \brief Returns true if both nodes have the same value for the given
51 /// operand \p Op, or if both nodes do not have this operand.
52 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
53 unsigned Opc0 = N0->getMachineOpcode();
54 unsigned Opc1 = N1->getMachineOpcode();
56 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
57 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
59 if (Op0Idx == -1 && Op1Idx == -1)
63 if ((Op0Idx == -1 && Op1Idx != -1) ||
64 (Op1Idx == -1 && Op0Idx != -1))
67 // getNamedOperandIdx returns the index for the MachineInstr's operands,
68 // which includes the result as the first operand. We are indexing into the
69 // MachineSDNode's operands, so we need to skip the result operand to get
74 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
77 bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
78 AliasAnalysis *AA) const {
79 // TODO: The generic check fails for VALU instructions that should be
80 // rematerializable due to implicit reads of exec. We really want all of the
81 // generic logic for this except for this.
82 switch (MI->getOpcode()) {
83 case AMDGPU::V_MOV_B32_e32:
84 case AMDGPU::V_MOV_B32_e64:
85 case AMDGPU::V_MOV_B64_PSEUDO:
92 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
94 int64_t &Offset1) const {
95 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
98 unsigned Opc0 = Load0->getMachineOpcode();
99 unsigned Opc1 = Load1->getMachineOpcode();
101 // Make sure both are actually loads.
102 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
105 if (isDS(Opc0) && isDS(Opc1)) {
107 // FIXME: Handle this case:
108 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
112 if (Load0->getOperand(1) != Load1->getOperand(1))
116 if (findChainOperand(Load0) != findChainOperand(Load1))
119 // Skip read2 / write2 variants for simplicity.
120 // TODO: We should report true if the used offsets are adjacent (excluded
122 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
123 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
126 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
127 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
131 if (isSMRD(Opc0) && isSMRD(Opc1)) {
132 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
135 if (Load0->getOperand(0) != Load1->getOperand(0))
138 const ConstantSDNode *Load0Offset =
139 dyn_cast<ConstantSDNode>(Load0->getOperand(1));
140 const ConstantSDNode *Load1Offset =
141 dyn_cast<ConstantSDNode>(Load1->getOperand(1));
143 if (!Load0Offset || !Load1Offset)
147 if (findChainOperand(Load0) != findChainOperand(Load1))
150 Offset0 = Load0Offset->getZExtValue();
151 Offset1 = Load1Offset->getZExtValue();
155 // MUBUF and MTBUF can access the same addresses.
156 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
158 // MUBUF and MTBUF have vaddr at different indices.
159 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
160 findChainOperand(Load0) != findChainOperand(Load1) ||
161 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
162 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
165 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
166 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
168 if (OffIdx0 == -1 || OffIdx1 == -1)
171 // getNamedOperandIdx returns the index for MachineInstrs. Since they
172 // inlcude the output in the operand list, but SDNodes don't, we need to
173 // subtract the index by one.
177 SDValue Off0 = Load0->getOperand(OffIdx0);
178 SDValue Off1 = Load1->getOperand(OffIdx1);
180 // The offset might be a FrameIndexSDNode.
181 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
184 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
185 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
192 static bool isStride64(unsigned Opc) {
194 case AMDGPU::DS_READ2ST64_B32:
195 case AMDGPU::DS_READ2ST64_B64:
196 case AMDGPU::DS_WRITE2ST64_B32:
197 case AMDGPU::DS_WRITE2ST64_B64:
204 bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
206 const TargetRegisterInfo *TRI) const {
207 unsigned Opc = LdSt->getOpcode();
209 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
210 AMDGPU::OpName::offset);
212 // Normal, single offset LDS instruction.
213 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
214 AMDGPU::OpName::addr);
216 BaseReg = AddrReg->getReg();
217 Offset = OffsetImm->getImm();
221 // The 2 offset instructions use offset0 and offset1 instead. We can treat
222 // these as a load with a single offset if the 2 offsets are consecutive. We
223 // will use this for some partially aligned loads.
224 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
225 AMDGPU::OpName::offset0);
226 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
227 AMDGPU::OpName::offset1);
229 uint8_t Offset0 = Offset0Imm->getImm();
230 uint8_t Offset1 = Offset1Imm->getImm();
232 if (Offset1 > Offset0 && Offset1 - Offset0 == 1) {
233 // Each of these offsets is in element sized units, so we need to convert
234 // to bytes of the individual reads.
238 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
240 assert(LdSt->mayStore());
241 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
242 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
248 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
249 AMDGPU::OpName::addr);
250 BaseReg = AddrReg->getReg();
251 Offset = EltSize * Offset0;
258 if (isMUBUF(Opc) || isMTBUF(Opc)) {
259 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
262 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
263 AMDGPU::OpName::vaddr);
267 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
268 AMDGPU::OpName::offset);
269 BaseReg = AddrReg->getReg();
270 Offset = OffsetImm->getImm();
275 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
276 AMDGPU::OpName::offset);
280 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
281 AMDGPU::OpName::sbase);
282 BaseReg = SBaseReg->getReg();
283 Offset = OffsetImm->getImm();
290 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
291 MachineInstr *SecondLdSt,
292 unsigned NumLoads) const {
293 unsigned Opc0 = FirstLdSt->getOpcode();
294 unsigned Opc1 = SecondLdSt->getOpcode();
296 // TODO: This needs finer tuning
300 if (isDS(Opc0) && isDS(Opc1))
303 if (isSMRD(Opc0) && isSMRD(Opc1))
306 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1)))
313 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
314 MachineBasicBlock::iterator MI, DebugLoc DL,
315 unsigned DestReg, unsigned SrcReg,
316 bool KillSrc) const {
318 // If we are trying to copy to or from SCC, there is a bug somewhere else in
319 // the backend. While it may be theoretically possible to do this, it should
320 // never be necessary.
321 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
323 static const int16_t Sub0_15[] = {
324 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
325 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
326 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
327 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
330 static const int16_t Sub0_7[] = {
331 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
332 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
335 static const int16_t Sub0_3[] = {
336 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
339 static const int16_t Sub0_2[] = {
340 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
343 static const int16_t Sub0_1[] = {
344 AMDGPU::sub0, AMDGPU::sub1, 0
348 const int16_t *SubIndices;
350 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
351 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
352 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
353 .addReg(SrcReg, getKillRegState(KillSrc));
356 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
357 if (DestReg == AMDGPU::VCC) {
358 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
359 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
360 .addReg(SrcReg, getKillRegState(KillSrc));
362 // FIXME: Hack until VReg_1 removed.
363 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
364 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32))
366 .addReg(SrcReg, getKillRegState(KillSrc));
372 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
373 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
374 .addReg(SrcReg, getKillRegState(KillSrc));
377 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
378 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
379 Opcode = AMDGPU::S_MOV_B32;
382 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
383 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
384 Opcode = AMDGPU::S_MOV_B32;
387 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
388 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
389 Opcode = AMDGPU::S_MOV_B32;
390 SubIndices = Sub0_15;
392 } else if (AMDGPU::VGPR_32RegClass.contains(DestReg)) {
393 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
394 AMDGPU::SReg_32RegClass.contains(SrcReg));
395 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
396 .addReg(SrcReg, getKillRegState(KillSrc));
399 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
400 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
401 AMDGPU::SReg_64RegClass.contains(SrcReg));
402 Opcode = AMDGPU::V_MOV_B32_e32;
405 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
406 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
407 Opcode = AMDGPU::V_MOV_B32_e32;
410 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
411 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
412 AMDGPU::SReg_128RegClass.contains(SrcReg));
413 Opcode = AMDGPU::V_MOV_B32_e32;
416 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
417 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
418 AMDGPU::SReg_256RegClass.contains(SrcReg));
419 Opcode = AMDGPU::V_MOV_B32_e32;
422 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
423 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
424 AMDGPU::SReg_512RegClass.contains(SrcReg));
425 Opcode = AMDGPU::V_MOV_B32_e32;
426 SubIndices = Sub0_15;
429 llvm_unreachable("Can't copy register!");
432 while (unsigned SubIdx = *SubIndices++) {
433 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
434 get(Opcode), RI.getSubReg(DestReg, SubIdx));
436 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
439 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
443 int SIInstrInfo::commuteOpcode(const MachineInstr &MI) const {
444 const unsigned Opcode = MI.getOpcode();
448 // Try to map original to commuted opcode
449 NewOpc = AMDGPU::getCommuteRev(Opcode);
451 // Check if the commuted (REV) opcode exists on the target.
452 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
454 // Try to map commuted to original opcode
455 NewOpc = AMDGPU::getCommuteOrig(Opcode);
457 // Check if the original (non-REV) opcode exists on the target.
458 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
463 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
465 if (DstRC->getSize() == 4) {
466 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
467 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) {
468 return AMDGPU::S_MOV_B64;
469 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) {
470 return AMDGPU::V_MOV_B64_PSEUDO;
475 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
476 MachineBasicBlock::iterator MI,
477 unsigned SrcReg, bool isKill,
479 const TargetRegisterClass *RC,
480 const TargetRegisterInfo *TRI) const {
481 MachineFunction *MF = MBB.getParent();
482 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
483 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
484 DebugLoc DL = MBB.findDebugLoc(MI);
487 if (RI.isSGPRClass(RC)) {
488 // We are only allowed to create one new instruction when spilling
489 // registers, so we need to use pseudo instruction for spilling
491 switch (RC->getSize() * 8) {
492 case 32: Opcode = AMDGPU::SI_SPILL_S32_SAVE; break;
493 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
494 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
495 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
496 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
498 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
499 MFI->setHasSpilledVGPRs();
501 switch(RC->getSize() * 8) {
502 case 32: Opcode = AMDGPU::SI_SPILL_V32_SAVE; break;
503 case 64: Opcode = AMDGPU::SI_SPILL_V64_SAVE; break;
504 case 96: Opcode = AMDGPU::SI_SPILL_V96_SAVE; break;
505 case 128: Opcode = AMDGPU::SI_SPILL_V128_SAVE; break;
506 case 256: Opcode = AMDGPU::SI_SPILL_V256_SAVE; break;
507 case 512: Opcode = AMDGPU::SI_SPILL_V512_SAVE; break;
512 MachinePointerInfo PtrInfo
513 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
514 unsigned Size = FrameInfo->getObjectSize(FrameIndex);
515 unsigned Align = FrameInfo->getObjectAlignment(FrameIndex);
516 MachineMemOperand *MMO
517 = MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
520 FrameInfo->setObjectAlignment(FrameIndex, 4);
521 BuildMI(MBB, MI, DL, get(Opcode))
523 .addFrameIndex(FrameIndex)
524 // Place-holder registers, these will be filled in by
525 // SIPrepareScratchRegs.
526 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
527 .addReg(AMDGPU::SGPR0, RegState::Undef)
530 LLVMContext &Ctx = MF->getFunction()->getContext();
531 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
533 BuildMI(MBB, MI, DL, get(AMDGPU::KILL))
538 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
539 MachineBasicBlock::iterator MI,
540 unsigned DestReg, int FrameIndex,
541 const TargetRegisterClass *RC,
542 const TargetRegisterInfo *TRI) const {
543 MachineFunction *MF = MBB.getParent();
544 const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
545 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
546 DebugLoc DL = MBB.findDebugLoc(MI);
549 if (RI.isSGPRClass(RC)){
550 switch(RC->getSize() * 8) {
551 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
552 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
553 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
554 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
555 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
557 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
558 switch(RC->getSize() * 8) {
559 case 32: Opcode = AMDGPU::SI_SPILL_V32_RESTORE; break;
560 case 64: Opcode = AMDGPU::SI_SPILL_V64_RESTORE; break;
561 case 96: Opcode = AMDGPU::SI_SPILL_V96_RESTORE; break;
562 case 128: Opcode = AMDGPU::SI_SPILL_V128_RESTORE; break;
563 case 256: Opcode = AMDGPU::SI_SPILL_V256_RESTORE; break;
564 case 512: Opcode = AMDGPU::SI_SPILL_V512_RESTORE; break;
570 FrameInfo->setObjectAlignment(FrameIndex, Align);
571 unsigned Size = FrameInfo->getObjectSize(FrameIndex);
573 MachinePointerInfo PtrInfo
574 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
575 MachineMemOperand *MMO = MF->getMachineMemOperand(
576 PtrInfo, MachineMemOperand::MOLoad, Size, Align);
578 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
579 .addFrameIndex(FrameIndex)
580 // Place-holder registers, these will be filled in by
581 // SIPrepareScratchRegs.
582 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
583 .addReg(AMDGPU::SGPR0, RegState::Undef)
586 LLVMContext &Ctx = MF->getFunction()->getContext();
587 Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"
588 " restore register");
589 BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg);
593 /// \param @Offset Offset in bytes of the FrameIndex being spilled
594 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
595 MachineBasicBlock::iterator MI,
596 RegScavenger *RS, unsigned TmpReg,
597 unsigned FrameOffset,
598 unsigned Size) const {
599 MachineFunction *MF = MBB.getParent();
600 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
601 const AMDGPUSubtarget &ST = MF->getSubtarget<AMDGPUSubtarget>();
602 const SIRegisterInfo *TRI =
603 static_cast<const SIRegisterInfo*>(ST.getRegisterInfo());
604 DebugLoc DL = MBB.findDebugLoc(MI);
605 unsigned WorkGroupSize = MFI->getMaximumWorkGroupSize(*MF);
606 unsigned WavefrontSize = ST.getWavefrontSize();
608 unsigned TIDReg = MFI->getTIDReg();
609 if (!MFI->hasCalculatedTID()) {
610 MachineBasicBlock &Entry = MBB.getParent()->front();
611 MachineBasicBlock::iterator Insert = Entry.front();
612 DebugLoc DL = Insert->getDebugLoc();
614 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);
615 if (TIDReg == AMDGPU::NoRegister)
619 if (MFI->getShaderType() == ShaderType::COMPUTE &&
620 WorkGroupSize > WavefrontSize) {
622 unsigned TIDIGXReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_X);
623 unsigned TIDIGYReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Y);
624 unsigned TIDIGZReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Z);
625 unsigned InputPtrReg =
626 TRI->getPreloadedValue(*MF, SIRegisterInfo::INPUT_PTR);
627 for (unsigned Reg : {TIDIGXReg, TIDIGYReg, TIDIGZReg}) {
628 if (!Entry.isLiveIn(Reg))
629 Entry.addLiveIn(Reg);
632 RS->enterBasicBlock(&Entry);
633 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
634 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
635 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
637 .addImm(SI::KernelInputOffsets::NGROUPS_Z);
638 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
640 .addImm(SI::KernelInputOffsets::NGROUPS_Y);
642 // NGROUPS.X * NGROUPS.Y
643 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
646 // (NGROUPS.X * NGROUPS.Y) * TIDIG.X
647 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
650 // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)
651 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
655 // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z
656 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg)
661 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
666 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64),
672 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
676 MFI->setTIDReg(TIDReg);
679 // Add FrameIndex to LDS offset
680 unsigned LDSOffset = MFI->LDSSize + (FrameOffset * WorkGroupSize);
681 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg)
688 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
697 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
702 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
703 MachineBasicBlock &MBB = *MI->getParent();
704 DebugLoc DL = MBB.findDebugLoc(MI);
705 switch (MI->getOpcode()) {
706 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
708 case AMDGPU::SI_CONSTDATA_PTR: {
709 unsigned Reg = MI->getOperand(0).getReg();
710 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
711 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
713 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg);
715 // Add 32-bit offset from this instruction to the start of the constant data.
716 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_U32), RegLo)
718 .addTargetIndex(AMDGPU::TI_CONSTDATA_START)
719 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit);
720 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi)
723 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit)
724 .addReg(AMDGPU::SCC, RegState::Implicit);
725 MI->eraseFromParent();
728 case AMDGPU::SGPR_USE:
729 // This is just a placeholder for register allocation.
730 MI->eraseFromParent();
733 case AMDGPU::V_MOV_B64_PSEUDO: {
734 unsigned Dst = MI->getOperand(0).getReg();
735 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
736 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
738 const MachineOperand &SrcOp = MI->getOperand(1);
739 // FIXME: Will this work for 64-bit floating point immediates?
740 assert(!SrcOp.isFPImm());
742 APInt Imm(64, SrcOp.getImm());
743 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
744 .addImm(Imm.getLoBits(32).getZExtValue())
745 .addReg(Dst, RegState::Implicit);
746 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
747 .addImm(Imm.getHiBits(32).getZExtValue())
748 .addReg(Dst, RegState::Implicit);
750 assert(SrcOp.isReg());
751 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
752 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
753 .addReg(Dst, RegState::Implicit);
754 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
755 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
756 .addReg(Dst, RegState::Implicit);
758 MI->eraseFromParent();
762 case AMDGPU::V_CNDMASK_B64_PSEUDO: {
763 unsigned Dst = MI->getOperand(0).getReg();
764 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
765 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
766 unsigned Src0 = MI->getOperand(1).getReg();
767 unsigned Src1 = MI->getOperand(2).getReg();
768 const MachineOperand &SrcCond = MI->getOperand(3);
770 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
771 .addReg(RI.getSubReg(Src0, AMDGPU::sub0))
772 .addReg(RI.getSubReg(Src1, AMDGPU::sub0))
773 .addOperand(SrcCond);
774 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
775 .addReg(RI.getSubReg(Src0, AMDGPU::sub1))
776 .addReg(RI.getSubReg(Src1, AMDGPU::sub1))
777 .addOperand(SrcCond);
778 MI->eraseFromParent();
785 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
787 int CommutedOpcode = commuteOpcode(*MI);
788 if (CommutedOpcode == -1)
791 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
792 AMDGPU::OpName::src0);
793 MachineOperand &Src0 = MI->getOperand(Src0Idx);
797 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
798 AMDGPU::OpName::src1);
799 MachineOperand &Src1 = MI->getOperand(Src1Idx);
801 // Make sure it's legal to commute operands for VOP2.
802 if (isVOP2(MI->getOpcode()) &&
803 (!isOperandLegal(MI, Src0Idx, &Src1) ||
804 !isOperandLegal(MI, Src1Idx, &Src0))) {
809 // Allow commuting instructions with Imm operands.
810 if (NewMI || !Src1.isImm() ||
811 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
815 // Be sure to copy the source modifiers to the right place.
816 if (MachineOperand *Src0Mods
817 = getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) {
818 MachineOperand *Src1Mods
819 = getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers);
821 int Src0ModsVal = Src0Mods->getImm();
822 if (!Src1Mods && Src0ModsVal != 0)
825 // XXX - This assert might be a lie. It might be useful to have a neg
826 // modifier with 0.0.
827 int Src1ModsVal = Src1Mods->getImm();
828 assert((Src1ModsVal == 0) && "Not expecting modifiers with immediates");
830 Src1Mods->setImm(Src0ModsVal);
831 Src0Mods->setImm(Src1ModsVal);
834 unsigned Reg = Src0.getReg();
835 unsigned SubReg = Src0.getSubReg();
837 Src0.ChangeToImmediate(Src1.getImm());
839 llvm_unreachable("Should only have immediates");
841 Src1.ChangeToRegister(Reg, false);
842 Src1.setSubReg(SubReg);
844 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
848 MI->setDesc(get(CommutedOpcode));
853 // This needs to be implemented because the source modifiers may be inserted
854 // between the true commutable operands, and the base
855 // TargetInstrInfo::commuteInstruction uses it.
856 bool SIInstrInfo::findCommutedOpIndices(MachineInstr *MI,
858 unsigned &SrcOpIdx2) const {
859 const MCInstrDesc &MCID = MI->getDesc();
860 if (!MCID.isCommutable())
863 unsigned Opc = MI->getOpcode();
864 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
868 // FIXME: Workaround TargetInstrInfo::commuteInstruction asserting on
870 if (!MI->getOperand(Src0Idx).isReg())
873 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
877 if (!MI->getOperand(Src1Idx).isReg())
880 // If any source modifiers are set, the generic instruction commuting won't
881 // understand how to copy the source modifiers.
882 if (hasModifiersSet(*MI, AMDGPU::OpName::src0_modifiers) ||
883 hasModifiersSet(*MI, AMDGPU::OpName::src1_modifiers))
891 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
892 MachineBasicBlock::iterator I,
894 unsigned SrcReg) const {
895 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
896 DstReg) .addReg(SrcReg);
899 bool SIInstrInfo::isMov(unsigned Opcode) const {
901 default: return false;
902 case AMDGPU::S_MOV_B32:
903 case AMDGPU::S_MOV_B64:
904 case AMDGPU::V_MOV_B32_e32:
905 case AMDGPU::V_MOV_B32_e64:
910 static void removeModOperands(MachineInstr &MI) {
911 unsigned Opc = MI.getOpcode();
912 int Src0ModIdx = AMDGPU::getNamedOperandIdx(Opc,
913 AMDGPU::OpName::src0_modifiers);
914 int Src1ModIdx = AMDGPU::getNamedOperandIdx(Opc,
915 AMDGPU::OpName::src1_modifiers);
916 int Src2ModIdx = AMDGPU::getNamedOperandIdx(Opc,
917 AMDGPU::OpName::src2_modifiers);
919 MI.RemoveOperand(Src2ModIdx);
920 MI.RemoveOperand(Src1ModIdx);
921 MI.RemoveOperand(Src0ModIdx);
924 bool SIInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
925 unsigned Reg, MachineRegisterInfo *MRI) const {
926 if (!MRI->hasOneNonDBGUse(Reg))
929 unsigned Opc = UseMI->getOpcode();
930 if (Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64) {
931 // Don't fold if we are using source modifiers. The new VOP2 instructions
933 if (hasModifiersSet(*UseMI, AMDGPU::OpName::src0_modifiers) ||
934 hasModifiersSet(*UseMI, AMDGPU::OpName::src1_modifiers) ||
935 hasModifiersSet(*UseMI, AMDGPU::OpName::src2_modifiers)) {
939 MachineOperand *Src0 = getNamedOperand(*UseMI, AMDGPU::OpName::src0);
940 MachineOperand *Src1 = getNamedOperand(*UseMI, AMDGPU::OpName::src1);
941 MachineOperand *Src2 = getNamedOperand(*UseMI, AMDGPU::OpName::src2);
943 // Multiplied part is the constant: Use v_madmk_f32
944 // We should only expect these to be on src0 due to canonicalizations.
945 if (Src0->isReg() && Src0->getReg() == Reg) {
946 if (!Src1->isReg() ||
947 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
950 if (!Src2->isReg() ||
951 (Src2->isReg() && RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))))
954 // We need to do some weird looking operand shuffling since the madmk
955 // operands are out of the normal expected order with the multiplied
956 // constant as the last operand.
958 // v_mad_f32 src0, src1, src2 -> v_madmk_f32 src0 * src2K + src1
963 const int64_t Imm = DefMI->getOperand(1).getImm();
965 // FIXME: This would be a lot easier if we could return a new instruction
966 // instead of having to modify in place.
968 // Remove these first since they are at the end.
969 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
970 AMDGPU::OpName::omod));
971 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
972 AMDGPU::OpName::clamp));
974 unsigned Src1Reg = Src1->getReg();
975 unsigned Src1SubReg = Src1->getSubReg();
976 unsigned Src2Reg = Src2->getReg();
977 unsigned Src2SubReg = Src2->getSubReg();
978 Src0->setReg(Src1Reg);
979 Src0->setSubReg(Src1SubReg);
980 Src0->setIsKill(Src1->isKill());
982 Src1->setReg(Src2Reg);
983 Src1->setSubReg(Src2SubReg);
984 Src1->setIsKill(Src2->isKill());
986 if (Opc == AMDGPU::V_MAC_F32_e64) {
987 UseMI->untieRegOperand(
988 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
991 Src2->ChangeToImmediate(Imm);
993 removeModOperands(*UseMI);
994 UseMI->setDesc(get(AMDGPU::V_MADMK_F32));
996 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
998 DefMI->eraseFromParent();
1003 // Added part is the constant: Use v_madak_f32
1004 if (Src2->isReg() && Src2->getReg() == Reg) {
1005 // Not allowed to use constant bus for another operand.
1006 // We can however allow an inline immediate as src0.
1007 if (!Src0->isImm() &&
1008 (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg()))))
1011 if (!Src1->isReg() ||
1012 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
1015 const int64_t Imm = DefMI->getOperand(1).getImm();
1017 // FIXME: This would be a lot easier if we could return a new instruction
1018 // instead of having to modify in place.
1020 // Remove these first since they are at the end.
1021 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1022 AMDGPU::OpName::omod));
1023 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1024 AMDGPU::OpName::clamp));
1026 if (Opc == AMDGPU::V_MAC_F32_e64) {
1027 UseMI->untieRegOperand(
1028 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
1031 // ChangingToImmediate adds Src2 back to the instruction.
1032 Src2->ChangeToImmediate(Imm);
1034 // These come before src2.
1035 removeModOperands(*UseMI);
1036 UseMI->setDesc(get(AMDGPU::V_MADAK_F32));
1038 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1040 DefMI->eraseFromParent();
1049 static bool offsetsDoNotOverlap(int WidthA, int OffsetA,
1050 int WidthB, int OffsetB) {
1051 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
1052 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
1053 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
1054 return LowOffset + LowWidth <= HighOffset;
1057 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
1058 MachineInstr *MIb) const {
1059 unsigned BaseReg0, Offset0;
1060 unsigned BaseReg1, Offset1;
1062 if (getMemOpBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) &&
1063 getMemOpBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) {
1064 assert(MIa->hasOneMemOperand() && MIb->hasOneMemOperand() &&
1065 "read2 / write2 not expected here yet");
1066 unsigned Width0 = (*MIa->memoperands_begin())->getSize();
1067 unsigned Width1 = (*MIb->memoperands_begin())->getSize();
1068 if (BaseReg0 == BaseReg1 &&
1069 offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) {
1077 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
1079 AliasAnalysis *AA) const {
1080 unsigned Opc0 = MIa->getOpcode();
1081 unsigned Opc1 = MIb->getOpcode();
1083 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
1084 "MIa must load from or modify a memory location");
1085 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
1086 "MIb must load from or modify a memory location");
1088 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects())
1091 // XXX - Can we relax this between address spaces?
1092 if (MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
1095 // TODO: Should we check the address space from the MachineMemOperand? That
1096 // would allow us to distinguish objects we know don't alias based on the
1097 // underlying address space, even if it was lowered to a different one,
1098 // e.g. private accesses lowered to use MUBUF instructions on a scratch
1102 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1104 return !isFLAT(Opc1);
1107 if (isMUBUF(Opc0) || isMTBUF(Opc0)) {
1108 if (isMUBUF(Opc1) || isMTBUF(Opc1))
1109 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1111 return !isFLAT(Opc1) && !isSMRD(Opc1);
1116 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1118 return !isFLAT(Opc1) && !isMUBUF(Opc0) && !isMTBUF(Opc0);
1123 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1131 MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB,
1132 MachineBasicBlock::iterator &MI,
1133 LiveVariables *LV) const {
1135 switch (MI->getOpcode()) {
1136 default: return nullptr;
1137 case AMDGPU::V_MAC_F32_e64: break;
1138 case AMDGPU::V_MAC_F32_e32: {
1139 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
1140 if (Src0->isImm() && !isInlineConstant(*Src0, 4))
1146 const MachineOperand *Dst = getNamedOperand(*MI, AMDGPU::OpName::dst);
1147 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
1148 const MachineOperand *Src1 = getNamedOperand(*MI, AMDGPU::OpName::src1);
1149 const MachineOperand *Src2 = getNamedOperand(*MI, AMDGPU::OpName::src2);
1151 return BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_MAD_F32))
1153 .addImm(0) // Src0 mods
1155 .addImm(0) // Src1 mods
1157 .addImm(0) // Src mods
1163 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
1164 int64_t SVal = Imm.getSExtValue();
1165 if (SVal >= -16 && SVal <= 64)
1168 if (Imm.getBitWidth() == 64) {
1169 uint64_t Val = Imm.getZExtValue();
1170 return (DoubleToBits(0.0) == Val) ||
1171 (DoubleToBits(1.0) == Val) ||
1172 (DoubleToBits(-1.0) == Val) ||
1173 (DoubleToBits(0.5) == Val) ||
1174 (DoubleToBits(-0.5) == Val) ||
1175 (DoubleToBits(2.0) == Val) ||
1176 (DoubleToBits(-2.0) == Val) ||
1177 (DoubleToBits(4.0) == Val) ||
1178 (DoubleToBits(-4.0) == Val);
1181 // The actual type of the operand does not seem to matter as long
1182 // as the bits match one of the inline immediate values. For example:
1184 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
1185 // so it is a legal inline immediate.
1187 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
1188 // floating-point, so it is a legal inline immediate.
1189 uint32_t Val = Imm.getZExtValue();
1191 return (FloatToBits(0.0f) == Val) ||
1192 (FloatToBits(1.0f) == Val) ||
1193 (FloatToBits(-1.0f) == Val) ||
1194 (FloatToBits(0.5f) == Val) ||
1195 (FloatToBits(-0.5f) == Val) ||
1196 (FloatToBits(2.0f) == Val) ||
1197 (FloatToBits(-2.0f) == Val) ||
1198 (FloatToBits(4.0f) == Val) ||
1199 (FloatToBits(-4.0f) == Val);
1202 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,
1203 unsigned OpSize) const {
1205 // MachineOperand provides no way to tell the true operand size, since it
1206 // only records a 64-bit value. We need to know the size to determine if a
1207 // 32-bit floating point immediate bit pattern is legal for an integer
1208 // immediate. It would be for any 32-bit integer operand, but would not be
1209 // for a 64-bit one.
1211 unsigned BitSize = 8 * OpSize;
1212 return isInlineConstant(APInt(BitSize, MO.getImm(), true));
1218 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO,
1219 unsigned OpSize) const {
1220 return MO.isImm() && !isInlineConstant(MO, OpSize);
1223 static bool compareMachineOp(const MachineOperand &Op0,
1224 const MachineOperand &Op1) {
1225 if (Op0.getType() != Op1.getType())
1228 switch (Op0.getType()) {
1229 case MachineOperand::MO_Register:
1230 return Op0.getReg() == Op1.getReg();
1231 case MachineOperand::MO_Immediate:
1232 return Op0.getImm() == Op1.getImm();
1234 llvm_unreachable("Didn't expect to be comparing these operand types");
1238 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
1239 const MachineOperand &MO) const {
1240 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
1242 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
1244 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
1247 if (OpInfo.RegClass < 0)
1250 unsigned OpSize = RI.getRegClass(OpInfo.RegClass)->getSize();
1251 if (isLiteralConstant(MO, OpSize))
1252 return RI.opCanUseLiteralConstant(OpInfo.OperandType);
1254 return RI.opCanUseInlineConstant(OpInfo.OperandType);
1257 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
1258 int Op32 = AMDGPU::getVOPe32(Opcode);
1262 return pseudoToMCOpcode(Op32) != -1;
1265 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
1266 // The src0_modifier operand is present on all instructions
1267 // that have modifiers.
1269 return AMDGPU::getNamedOperandIdx(Opcode,
1270 AMDGPU::OpName::src0_modifiers) != -1;
1273 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,
1274 unsigned OpName) const {
1275 const MachineOperand *Mods = getNamedOperand(MI, OpName);
1276 return Mods && Mods->getImm();
1279 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
1280 const MachineOperand &MO,
1281 unsigned OpSize) const {
1282 // Literal constants use the constant bus.
1283 if (isLiteralConstant(MO, OpSize))
1286 if (!MO.isReg() || !MO.isUse())
1289 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1290 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
1292 // FLAT_SCR is just an SGPR pair.
1293 if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
1296 // EXEC register uses the constant bus.
1297 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
1300 // SGPRs use the constant bus
1301 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
1302 (!MO.isImplicit() &&
1303 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
1304 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
1311 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
1312 StringRef &ErrInfo) const {
1313 uint16_t Opcode = MI->getOpcode();
1314 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1315 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
1316 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
1317 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
1319 // Make sure the number of operands is correct.
1320 const MCInstrDesc &Desc = get(Opcode);
1321 if (!Desc.isVariadic() &&
1322 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
1323 ErrInfo = "Instruction has wrong number of operands.";
1327 // Make sure the register classes are correct
1328 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
1329 if (MI->getOperand(i).isFPImm()) {
1330 ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast "
1331 "all fp values to integers.";
1335 int RegClass = Desc.OpInfo[i].RegClass;
1337 switch (Desc.OpInfo[i].OperandType) {
1338 case MCOI::OPERAND_REGISTER:
1339 if (MI->getOperand(i).isImm()) {
1340 ErrInfo = "Illegal immediate value for operand.";
1344 case AMDGPU::OPERAND_REG_IMM32:
1346 case AMDGPU::OPERAND_REG_INLINE_C:
1347 if (isLiteralConstant(MI->getOperand(i),
1348 RI.getRegClass(RegClass)->getSize())) {
1349 ErrInfo = "Illegal immediate value for operand.";
1353 case MCOI::OPERAND_IMMEDIATE:
1354 // Check if this operand is an immediate.
1355 // FrameIndex operands will be replaced by immediates, so they are
1357 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFI()) {
1358 ErrInfo = "Expected immediate, but got non-immediate";
1366 if (!MI->getOperand(i).isReg())
1369 if (RegClass != -1) {
1370 unsigned Reg = MI->getOperand(i).getReg();
1371 if (TargetRegisterInfo::isVirtualRegister(Reg))
1374 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
1375 if (!RC->contains(Reg)) {
1376 ErrInfo = "Operand has incorrect register class.";
1384 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
1385 // Only look at the true operands. Only a real operand can use the constant
1386 // bus, and we don't want to check pseudo-operands like the source modifier
1388 const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
1390 unsigned ConstantBusCount = 0;
1391 unsigned SGPRUsed = AMDGPU::NoRegister;
1392 for (int OpIdx : OpIndices) {
1395 const MachineOperand &MO = MI->getOperand(OpIdx);
1396 if (usesConstantBus(MRI, MO, getOpSize(Opcode, OpIdx))) {
1398 if (MO.getReg() != SGPRUsed)
1400 SGPRUsed = MO.getReg();
1406 if (ConstantBusCount > 1) {
1407 ErrInfo = "VOP* instruction uses the constant bus more than once";
1412 // Verify misc. restrictions on specific instructions.
1413 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
1414 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
1415 const MachineOperand &Src0 = MI->getOperand(Src0Idx);
1416 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1417 const MachineOperand &Src2 = MI->getOperand(Src2Idx);
1418 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
1419 if (!compareMachineOp(Src0, Src1) &&
1420 !compareMachineOp(Src0, Src2)) {
1421 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
1430 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
1431 switch (MI.getOpcode()) {
1432 default: return AMDGPU::INSTRUCTION_LIST_END;
1433 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
1434 case AMDGPU::COPY: return AMDGPU::COPY;
1435 case AMDGPU::PHI: return AMDGPU::PHI;
1436 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
1437 case AMDGPU::S_MOV_B32:
1438 return MI.getOperand(1).isReg() ?
1439 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
1440 case AMDGPU::S_ADD_I32:
1441 case AMDGPU::S_ADD_U32: return AMDGPU::V_ADD_I32_e32;
1442 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
1443 case AMDGPU::S_SUB_I32:
1444 case AMDGPU::S_SUB_U32: return AMDGPU::V_SUB_I32_e32;
1445 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
1446 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32;
1447 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
1448 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
1449 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
1450 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
1451 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
1452 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
1453 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
1454 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
1455 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
1456 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
1457 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
1458 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
1459 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
1460 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
1461 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
1462 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
1463 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
1464 case AMDGPU::S_BFM_B32: return AMDGPU::V_BFM_B32_e64;
1465 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
1466 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
1467 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
1468 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
1469 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
1470 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
1471 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
1472 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
1473 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
1474 case AMDGPU::S_LOAD_DWORD_IMM:
1475 case AMDGPU::S_LOAD_DWORD_SGPR: return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1476 case AMDGPU::S_LOAD_DWORDX2_IMM:
1477 case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1478 case AMDGPU::S_LOAD_DWORDX4_IMM:
1479 case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1480 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
1481 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
1482 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
1483 case AMDGPU::S_FLBIT_I32: return AMDGPU::V_FFBH_I32_e64;
1487 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
1488 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
1491 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
1492 unsigned OpNo) const {
1493 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1494 const MCInstrDesc &Desc = get(MI.getOpcode());
1495 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
1496 Desc.OpInfo[OpNo].RegClass == -1) {
1497 unsigned Reg = MI.getOperand(OpNo).getReg();
1499 if (TargetRegisterInfo::isVirtualRegister(Reg))
1500 return MRI.getRegClass(Reg);
1501 return RI.getPhysRegClass(Reg);
1504 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
1505 return RI.getRegClass(RCID);
1508 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
1509 switch (MI.getOpcode()) {
1511 case AMDGPU::REG_SEQUENCE:
1513 case AMDGPU::INSERT_SUBREG:
1514 return RI.hasVGPRs(getOpRegClass(MI, 0));
1516 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
1520 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
1521 MachineBasicBlock::iterator I = MI;
1522 MachineBasicBlock *MBB = MI->getParent();
1523 MachineOperand &MO = MI->getOperand(OpIdx);
1524 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1525 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
1526 const TargetRegisterClass *RC = RI.getRegClass(RCID);
1527 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1529 Opcode = AMDGPU::COPY;
1530 else if (RI.isSGPRClass(RC))
1531 Opcode = AMDGPU::S_MOV_B32;
1534 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
1535 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC))
1536 VRC = &AMDGPU::VReg_64RegClass;
1538 VRC = &AMDGPU::VGPR_32RegClass;
1540 unsigned Reg = MRI.createVirtualRegister(VRC);
1541 DebugLoc DL = MBB->findDebugLoc(I);
1542 BuildMI(*MI->getParent(), I, DL, get(Opcode), Reg)
1544 MO.ChangeToRegister(Reg, false);
1547 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
1548 MachineRegisterInfo &MRI,
1549 MachineOperand &SuperReg,
1550 const TargetRegisterClass *SuperRC,
1552 const TargetRegisterClass *SubRC)
1554 MachineBasicBlock *MBB = MI->getParent();
1555 DebugLoc DL = MI->getDebugLoc();
1556 unsigned SubReg = MRI.createVirtualRegister(SubRC);
1558 if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) {
1559 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1560 .addReg(SuperReg.getReg(), 0, SubIdx);
1564 // Just in case the super register is itself a sub-register, copy it to a new
1565 // value so we don't need to worry about merging its subreg index with the
1566 // SubIdx passed to this function. The register coalescer should be able to
1567 // eliminate this extra copy.
1568 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
1570 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
1571 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
1573 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1574 .addReg(NewSuperReg, 0, SubIdx);
1579 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
1580 MachineBasicBlock::iterator MII,
1581 MachineRegisterInfo &MRI,
1583 const TargetRegisterClass *SuperRC,
1585 const TargetRegisterClass *SubRC) const {
1587 // XXX - Is there a better way to do this?
1588 if (SubIdx == AMDGPU::sub0)
1589 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
1590 if (SubIdx == AMDGPU::sub1)
1591 return MachineOperand::CreateImm(Op.getImm() >> 32);
1593 llvm_unreachable("Unhandled register index for immediate");
1596 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
1598 return MachineOperand::CreateReg(SubReg, false);
1601 // Change the order of operands from (0, 1, 2) to (0, 2, 1)
1602 void SIInstrInfo::swapOperands(MachineBasicBlock::iterator Inst) const {
1603 assert(Inst->getNumExplicitOperands() == 3);
1604 MachineOperand Op1 = Inst->getOperand(1);
1605 Inst->RemoveOperand(1);
1606 Inst->addOperand(Op1);
1609 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1610 const MachineOperand *MO) const {
1611 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1612 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1613 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
1614 const TargetRegisterClass *DefinedRC =
1615 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
1617 MO = &MI->getOperand(OpIdx);
1619 if (isVALU(InstDesc.Opcode) &&
1620 usesConstantBus(MRI, *MO, DefinedRC->getSize())) {
1622 MO->isReg() ? MO->getReg() : (unsigned)AMDGPU::NoRegister;
1623 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1626 const MachineOperand &Op = MI->getOperand(i);
1627 if (Op.isReg() && Op.getReg() != SGPRUsed &&
1628 usesConstantBus(MRI, Op, getOpSize(*MI, i))) {
1636 const TargetRegisterClass *RC =
1637 TargetRegisterInfo::isVirtualRegister(MO->getReg()) ?
1638 MRI.getRegClass(MO->getReg()) :
1639 RI.getPhysRegClass(MO->getReg());
1641 // In order to be legal, the common sub-class must be equal to the
1642 // class of the current operand. For example:
1644 // v_mov_b32 s0 ; Operand defined as vsrc_32
1645 // ; RI.getCommonSubClass(s0,vsrc_32) = sgpr ; LEGAL
1647 // s_sendmsg 0, s0 ; Operand defined as m0reg
1648 // ; RI.getCommonSubClass(s0,m0reg) = m0reg ; NOT LEGAL
1650 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC;
1654 // Handle non-register types that are treated like immediates.
1655 assert(MO->isImm() || MO->isTargetIndex() || MO->isFI());
1658 // This operand expects an immediate.
1662 return isImmOperandLegal(MI, OpIdx, *MO);
1665 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1666 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1668 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1669 AMDGPU::OpName::src0);
1670 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1671 AMDGPU::OpName::src1);
1672 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1673 AMDGPU::OpName::src2);
1676 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
1678 if (!isOperandLegal(MI, Src0Idx))
1679 legalizeOpWithMove(MI, Src0Idx);
1682 if (isOperandLegal(MI, Src1Idx))
1685 // Usually src0 of VOP2 instructions allow more types of inputs
1686 // than src1, so try to commute the instruction to decrease our
1687 // chances of having to insert a MOV instruction to legalize src1.
1688 if (MI->isCommutable()) {
1689 if (commuteInstruction(MI))
1690 // If we are successful in commuting, then we know MI is legal, so
1695 legalizeOpWithMove(MI, Src1Idx);
1699 // XXX - Do any VOP3 instructions read VCC?
1701 if (isVOP3(MI->getOpcode())) {
1702 int VOP3Idx[3] = { Src0Idx, Src1Idx, Src2Idx };
1704 // Find the one SGPR operand we are allowed to use.
1705 unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx);
1707 for (unsigned i = 0; i < 3; ++i) {
1708 int Idx = VOP3Idx[i];
1711 MachineOperand &MO = MI->getOperand(Idx);
1714 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1715 continue; // VGPRs are legal
1717 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
1719 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1720 SGPRReg = MO.getReg();
1721 // We can use one SGPR in each VOP3 instruction.
1724 } else if (!isLiteralConstant(MO, getOpSize(MI->getOpcode(), Idx))) {
1725 // If it is not a register and not a literal constant, then it must be
1726 // an inline constant which is always legal.
1729 // If we make it this far, then the operand is not legal and we must
1731 legalizeOpWithMove(MI, Idx);
1737 // Legalize REG_SEQUENCE and PHI
1738 // The register class of the operands much be the same type as the register
1739 // class of the output.
1740 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE ||
1741 MI->getOpcode() == AMDGPU::PHI) {
1742 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1743 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1744 if (!MI->getOperand(i).isReg() ||
1745 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1747 const TargetRegisterClass *OpRC =
1748 MRI.getRegClass(MI->getOperand(i).getReg());
1749 if (RI.hasVGPRs(OpRC)) {
1756 // If any of the operands are VGPR registers, then they all most be
1757 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1759 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1762 VRC = RI.getEquivalentVGPRClass(SRC);
1769 // Update all the operands so they have the same type.
1770 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1771 if (!MI->getOperand(i).isReg() ||
1772 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1774 unsigned DstReg = MRI.createVirtualRegister(RC);
1775 MachineBasicBlock *InsertBB;
1776 MachineBasicBlock::iterator Insert;
1777 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1778 InsertBB = MI->getParent();
1781 // MI is a PHI instruction.
1782 InsertBB = MI->getOperand(i + 1).getMBB();
1783 Insert = InsertBB->getFirstTerminator();
1785 BuildMI(*InsertBB, Insert, MI->getDebugLoc(),
1786 get(AMDGPU::COPY), DstReg)
1787 .addOperand(MI->getOperand(i));
1788 MI->getOperand(i).setReg(DstReg);
1794 // Legalize INSERT_SUBREG
1795 // src0 must have the same register class as dst
1796 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
1797 unsigned Dst = MI->getOperand(0).getReg();
1798 unsigned Src0 = MI->getOperand(1).getReg();
1799 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1800 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1801 if (DstRC != Src0RC) {
1802 MachineBasicBlock &MBB = *MI->getParent();
1803 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
1804 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
1806 MI->getOperand(1).setReg(NewSrc0);
1811 // Legalize MUBUF* instructions
1812 // FIXME: If we start using the non-addr64 instructions for compute, we
1813 // may need to legalize them here.
1815 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc);
1816 if (SRsrcIdx != -1) {
1817 // We have an MUBUF instruction
1818 MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx);
1819 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass;
1820 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()),
1821 RI.getRegClass(SRsrcRC))) {
1822 // The operands are legal.
1823 // FIXME: We may need to legalize operands besided srsrc.
1827 MachineBasicBlock &MBB = *MI->getParent();
1829 // Extract the ptr from the resource descriptor.
1830 unsigned SRsrcPtr = buildExtractSubReg(MI, MRI, *SRsrc,
1831 &AMDGPU::VReg_128RegClass, AMDGPU::sub0_sub1, &AMDGPU::VReg_64RegClass);
1833 // Create an empty resource descriptor
1834 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1835 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1836 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1837 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1838 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
1841 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1845 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1846 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1848 .addImm(RsrcDataFormat & 0xFFFFFFFF);
1850 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1851 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1853 .addImm(RsrcDataFormat >> 32);
1855 // NewSRsrc = {Zero64, SRsrcFormat}
1856 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewSRsrc)
1858 .addImm(AMDGPU::sub0_sub1)
1859 .addReg(SRsrcFormatLo)
1860 .addImm(AMDGPU::sub2)
1861 .addReg(SRsrcFormatHi)
1862 .addImm(AMDGPU::sub3);
1864 MachineOperand *VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1865 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
1867 // This is already an ADDR64 instruction so we need to add the pointer
1868 // extracted from the resource descriptor to the current value of VAddr.
1869 unsigned NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1870 unsigned NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1872 // NewVaddrLo = SRsrcPtr:sub0 + VAddr:sub0
1873 DebugLoc DL = MI->getDebugLoc();
1874 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), NewVAddrLo)
1875 .addReg(SRsrcPtr, 0, AMDGPU::sub0)
1876 .addReg(VAddr->getReg(), 0, AMDGPU::sub0);
1878 // NewVaddrHi = SRsrcPtr:sub1 + VAddr:sub1
1879 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADDC_U32_e32), NewVAddrHi)
1880 .addReg(SRsrcPtr, 0, AMDGPU::sub1)
1881 .addReg(VAddr->getReg(), 0, AMDGPU::sub1);
1883 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1884 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
1886 .addImm(AMDGPU::sub0)
1888 .addImm(AMDGPU::sub1);
1890 // This instructions is the _OFFSET variant, so we need to convert it to
1892 MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata);
1893 MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset);
1894 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset);
1896 // Create the new instruction.
1897 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
1898 MachineInstr *Addr64 =
1899 BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
1901 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
1902 // This will be replaced later
1903 // with the new value of vaddr.
1905 .addOperand(*SOffset)
1906 .addOperand(*Offset)
1910 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1912 MI->removeFromParent();
1915 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1916 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
1917 .addReg(SRsrcPtr, 0, AMDGPU::sub0)
1918 .addImm(AMDGPU::sub0)
1919 .addReg(SRsrcPtr, 0, AMDGPU::sub1)
1920 .addImm(AMDGPU::sub1);
1922 VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1923 SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc);
1926 // Update the instruction to use NewVaddr
1927 VAddr->setReg(NewVAddr);
1928 // Update the instruction to use NewSRsrc
1929 SRsrc->setReg(NewSRsrc);
1933 void SIInstrInfo::splitSMRD(MachineInstr *MI,
1934 const TargetRegisterClass *HalfRC,
1935 unsigned HalfImmOp, unsigned HalfSGPROp,
1936 MachineInstr *&Lo, MachineInstr *&Hi) const {
1938 DebugLoc DL = MI->getDebugLoc();
1939 MachineBasicBlock *MBB = MI->getParent();
1940 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1941 unsigned RegLo = MRI.createVirtualRegister(HalfRC);
1942 unsigned RegHi = MRI.createVirtualRegister(HalfRC);
1943 unsigned HalfSize = HalfRC->getSize();
1944 const MachineOperand *OffOp =
1945 getNamedOperand(*MI, AMDGPU::OpName::offset);
1946 const MachineOperand *SBase = getNamedOperand(*MI, AMDGPU::OpName::sbase);
1948 // The SMRD has an 8-bit offset in dwords on SI and a 20-bit offset in bytes
1951 bool IsKill = SBase->isKill();
1954 MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() >=
1955 AMDGPUSubtarget::VOLCANIC_ISLANDS;
1956 unsigned OffScale = isVI ? 1 : 4;
1957 // Handle the _IMM variant
1958 unsigned LoOffset = OffOp->getImm() * OffScale;
1959 unsigned HiOffset = LoOffset + HalfSize;
1960 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo)
1961 // Use addReg instead of addOperand
1962 // to make sure kill flag is cleared.
1963 .addReg(SBase->getReg(), 0, SBase->getSubReg())
1964 .addImm(LoOffset / OffScale);
1966 if (!isUInt<20>(HiOffset) || (!isVI && !isUInt<8>(HiOffset / OffScale))) {
1967 unsigned OffsetSGPR =
1968 MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1969 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR)
1970 .addImm(HiOffset); // The offset in register is in bytes.
1971 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
1972 .addReg(SBase->getReg(), getKillRegState(IsKill),
1974 .addReg(OffsetSGPR);
1976 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi)
1977 .addReg(SBase->getReg(), getKillRegState(IsKill),
1979 .addImm(HiOffset / OffScale);
1982 // Handle the _SGPR variant
1983 MachineOperand *SOff = getNamedOperand(*MI, AMDGPU::OpName::soff);
1984 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo)
1985 .addReg(SBase->getReg(), 0, SBase->getSubReg())
1987 unsigned OffsetSGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1988 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR)
1991 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp))
1992 .addReg(SBase->getReg(), getKillRegState(IsKill),
1994 .addReg(OffsetSGPR);
1997 unsigned SubLo, SubHi;
1998 const TargetRegisterClass *NewDstRC;
2001 SubLo = AMDGPU::sub0;
2002 SubHi = AMDGPU::sub1;
2003 NewDstRC = &AMDGPU::VReg_64RegClass;
2006 SubLo = AMDGPU::sub0_sub1;
2007 SubHi = AMDGPU::sub2_sub3;
2008 NewDstRC = &AMDGPU::VReg_128RegClass;
2011 SubLo = AMDGPU::sub0_sub1_sub2_sub3;
2012 SubHi = AMDGPU::sub4_sub5_sub6_sub7;
2013 NewDstRC = &AMDGPU::VReg_256RegClass;
2016 SubLo = AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7;
2017 SubHi = AMDGPU::sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15;
2018 NewDstRC = &AMDGPU::VReg_512RegClass;
2021 llvm_unreachable("Unhandled HalfSize");
2024 unsigned OldDst = MI->getOperand(0).getReg();
2025 unsigned NewDst = MRI.createVirtualRegister(NewDstRC);
2027 MRI.replaceRegWith(OldDst, NewDst);
2029 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), NewDst)
2036 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
2037 MachineBasicBlock *MBB = MI->getParent();
2038 int DstIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
2039 assert(DstIdx != -1);
2040 unsigned DstRCID = get(MI->getOpcode()).OpInfo[DstIdx].RegClass;
2041 switch(RI.getRegClass(DstRCID)->getSize()) {
2045 unsigned NewOpcode = getVALUOp(*MI);
2049 if (MI->getOperand(2).isReg()) {
2050 RegOffset = MI->getOperand(2).getReg();
2053 assert(MI->getOperand(2).isImm());
2054 // SMRD instructions take a dword offsets on SI and byte offset on VI
2055 // and MUBUF instructions always take a byte offset.
2056 ImmOffset = MI->getOperand(2).getImm();
2057 if (MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() <=
2058 AMDGPUSubtarget::SEA_ISLANDS)
2060 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2062 if (isUInt<12>(ImmOffset)) {
2063 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2067 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2074 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
2075 unsigned DWord0 = RegOffset;
2076 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2077 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2078 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2079 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
2081 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
2083 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
2084 .addImm(RsrcDataFormat & 0xFFFFFFFF);
2085 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
2086 .addImm(RsrcDataFormat >> 32);
2087 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
2089 .addImm(AMDGPU::sub0)
2091 .addImm(AMDGPU::sub1)
2093 .addImm(AMDGPU::sub2)
2095 .addImm(AMDGPU::sub3);
2096 MI->setDesc(get(NewOpcode));
2097 if (MI->getOperand(2).isReg()) {
2098 MI->getOperand(2).setReg(SRsrc);
2100 MI->getOperand(2).ChangeToRegister(SRsrc, false);
2102 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0));
2103 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
2104 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0)); // glc
2105 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0)); // slc
2106 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0)); // tfe
2108 const TargetRegisterClass *NewDstRC =
2109 RI.getRegClass(get(NewOpcode).OpInfo[0].RegClass);
2111 unsigned DstReg = MI->getOperand(0).getReg();
2112 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2113 MRI.replaceRegWith(DstReg, NewDstReg);
2117 MachineInstr *Lo, *Hi;
2118 splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
2119 AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
2120 MI->eraseFromParent();
2121 moveSMRDToVALU(Lo, MRI);
2122 moveSMRDToVALU(Hi, MRI);
2127 MachineInstr *Lo, *Hi;
2128 splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
2129 AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
2130 MI->eraseFromParent();
2131 moveSMRDToVALU(Lo, MRI);
2132 moveSMRDToVALU(Hi, MRI);
2138 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
2139 SmallVector<MachineInstr *, 128> Worklist;
2140 Worklist.push_back(&TopInst);
2142 while (!Worklist.empty()) {
2143 MachineInstr *Inst = Worklist.pop_back_val();
2144 MachineBasicBlock *MBB = Inst->getParent();
2145 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2147 unsigned Opcode = Inst->getOpcode();
2148 unsigned NewOpcode = getVALUOp(*Inst);
2150 // Handle some special cases
2153 if (isSMRD(Inst->getOpcode())) {
2154 moveSMRDToVALU(Inst, MRI);
2157 case AMDGPU::S_AND_B64:
2158 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_AND_B32_e64);
2159 Inst->eraseFromParent();
2162 case AMDGPU::S_OR_B64:
2163 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_OR_B32_e64);
2164 Inst->eraseFromParent();
2167 case AMDGPU::S_XOR_B64:
2168 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_XOR_B32_e64);
2169 Inst->eraseFromParent();
2172 case AMDGPU::S_NOT_B64:
2173 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::V_NOT_B32_e32);
2174 Inst->eraseFromParent();
2177 case AMDGPU::S_BCNT1_I32_B64:
2178 splitScalar64BitBCNT(Worklist, Inst);
2179 Inst->eraseFromParent();
2182 case AMDGPU::S_BFE_I64: {
2183 splitScalar64BitBFE(Worklist, Inst);
2184 Inst->eraseFromParent();
2188 case AMDGPU::S_LSHL_B32:
2189 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2190 NewOpcode = AMDGPU::V_LSHLREV_B32_e64;
2194 case AMDGPU::S_ASHR_I32:
2195 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2196 NewOpcode = AMDGPU::V_ASHRREV_I32_e64;
2200 case AMDGPU::S_LSHR_B32:
2201 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2202 NewOpcode = AMDGPU::V_LSHRREV_B32_e64;
2206 case AMDGPU::S_LSHL_B64:
2207 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2208 NewOpcode = AMDGPU::V_LSHLREV_B64;
2212 case AMDGPU::S_ASHR_I64:
2213 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2214 NewOpcode = AMDGPU::V_ASHRREV_I64;
2218 case AMDGPU::S_LSHR_B64:
2219 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2220 NewOpcode = AMDGPU::V_LSHRREV_B64;
2225 case AMDGPU::S_BFE_U64:
2226 case AMDGPU::S_BFM_B64:
2227 llvm_unreachable("Moving this op to VALU not implemented");
2230 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
2231 // We cannot move this instruction to the VALU, so we should try to
2232 // legalize its operands instead.
2233 legalizeOperands(Inst);
2237 // Use the new VALU Opcode.
2238 const MCInstrDesc &NewDesc = get(NewOpcode);
2239 Inst->setDesc(NewDesc);
2241 // Remove any references to SCC. Vector instructions can't read from it, and
2242 // We're just about to add the implicit use / defs of VCC, and we don't want
2244 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
2245 MachineOperand &Op = Inst->getOperand(i);
2246 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
2247 Inst->RemoveOperand(i);
2250 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
2251 // We are converting these to a BFE, so we need to add the missing
2252 // operands for the size and offset.
2253 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
2254 Inst->addOperand(MachineOperand::CreateImm(0));
2255 Inst->addOperand(MachineOperand::CreateImm(Size));
2257 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
2258 // The VALU version adds the second operand to the result, so insert an
2260 Inst->addOperand(MachineOperand::CreateImm(0));
2263 Inst->addImplicitDefUseOperands(*Inst->getParent()->getParent());
2265 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
2266 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
2267 // If we need to move this to VGPRs, we need to unpack the second operand
2268 // back into the 2 separate ones for bit offset and width.
2269 assert(OffsetWidthOp.isImm() &&
2270 "Scalar BFE is only implemented for constant width and offset");
2271 uint32_t Imm = OffsetWidthOp.getImm();
2273 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2274 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2275 Inst->RemoveOperand(2); // Remove old immediate.
2276 Inst->addOperand(MachineOperand::CreateImm(Offset));
2277 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
2280 // Update the destination register class.
2282 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
2285 // For target instructions, getOpRegClass just returns the virtual
2286 // register class associated with the operand, so we need to find an
2287 // equivalent VGPR register class in order to move the instruction to the
2291 case AMDGPU::REG_SEQUENCE:
2292 case AMDGPU::INSERT_SUBREG:
2293 if (RI.hasVGPRs(NewDstRC))
2295 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
2303 unsigned DstReg = Inst->getOperand(0).getReg();
2304 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2305 MRI.replaceRegWith(DstReg, NewDstReg);
2307 // Legalize the operands
2308 legalizeOperands(Inst);
2310 addUsersToMoveToVALUWorklist(NewDstReg, MRI, Worklist);
2314 //===----------------------------------------------------------------------===//
2315 // Indirect addressing callbacks
2316 //===----------------------------------------------------------------------===//
2318 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
2319 unsigned Channel) const {
2320 assert(Channel == 0);
2324 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
2325 return &AMDGPU::VGPR_32RegClass;
2328 void SIInstrInfo::splitScalar64BitUnaryOp(
2329 SmallVectorImpl<MachineInstr *> &Worklist,
2331 unsigned Opcode) const {
2332 MachineBasicBlock &MBB = *Inst->getParent();
2333 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2335 MachineOperand &Dest = Inst->getOperand(0);
2336 MachineOperand &Src0 = Inst->getOperand(1);
2337 DebugLoc DL = Inst->getDebugLoc();
2339 MachineBasicBlock::iterator MII = Inst;
2341 const MCInstrDesc &InstDesc = get(Opcode);
2342 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2343 MRI.getRegClass(Src0.getReg()) :
2344 &AMDGPU::SGPR_32RegClass;
2346 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2348 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2349 AMDGPU::sub0, Src0SubRC);
2351 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2352 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
2353 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
2355 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
2356 BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2357 .addOperand(SrcReg0Sub0);
2359 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2360 AMDGPU::sub1, Src0SubRC);
2362 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
2363 BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2364 .addOperand(SrcReg0Sub1);
2366 unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC);
2367 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2369 .addImm(AMDGPU::sub0)
2371 .addImm(AMDGPU::sub1);
2373 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2375 // We don't need to legalizeOperands here because for a single operand, src0
2376 // will support any kind of input.
2378 // Move all users of this moved value.
2379 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
2382 void SIInstrInfo::splitScalar64BitBinaryOp(
2383 SmallVectorImpl<MachineInstr *> &Worklist,
2385 unsigned Opcode) const {
2386 MachineBasicBlock &MBB = *Inst->getParent();
2387 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2389 MachineOperand &Dest = Inst->getOperand(0);
2390 MachineOperand &Src0 = Inst->getOperand(1);
2391 MachineOperand &Src1 = Inst->getOperand(2);
2392 DebugLoc DL = Inst->getDebugLoc();
2394 MachineBasicBlock::iterator MII = Inst;
2396 const MCInstrDesc &InstDesc = get(Opcode);
2397 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2398 MRI.getRegClass(Src0.getReg()) :
2399 &AMDGPU::SGPR_32RegClass;
2401 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2402 const TargetRegisterClass *Src1RC = Src1.isReg() ?
2403 MRI.getRegClass(Src1.getReg()) :
2404 &AMDGPU::SGPR_32RegClass;
2406 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
2408 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2409 AMDGPU::sub0, Src0SubRC);
2410 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2411 AMDGPU::sub0, Src1SubRC);
2413 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2414 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
2415 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
2417 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
2418 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2419 .addOperand(SrcReg0Sub0)
2420 .addOperand(SrcReg1Sub0);
2422 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2423 AMDGPU::sub1, Src0SubRC);
2424 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2425 AMDGPU::sub1, Src1SubRC);
2427 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
2428 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2429 .addOperand(SrcReg0Sub1)
2430 .addOperand(SrcReg1Sub1);
2432 unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC);
2433 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2435 .addImm(AMDGPU::sub0)
2437 .addImm(AMDGPU::sub1);
2439 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2441 // Try to legalize the operands in case we need to swap the order to keep it
2443 legalizeOperands(LoHalf);
2444 legalizeOperands(HiHalf);
2446 // Move all users of this moved vlaue.
2447 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
2450 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
2451 MachineInstr *Inst) const {
2452 MachineBasicBlock &MBB = *Inst->getParent();
2453 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2455 MachineBasicBlock::iterator MII = Inst;
2456 DebugLoc DL = Inst->getDebugLoc();
2458 MachineOperand &Dest = Inst->getOperand(0);
2459 MachineOperand &Src = Inst->getOperand(1);
2461 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
2462 const TargetRegisterClass *SrcRC = Src.isReg() ?
2463 MRI.getRegClass(Src.getReg()) :
2464 &AMDGPU::SGPR_32RegClass;
2466 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2467 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2469 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
2471 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2472 AMDGPU::sub0, SrcSubRC);
2473 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2474 AMDGPU::sub1, SrcSubRC);
2476 BuildMI(MBB, MII, DL, InstDesc, MidReg)
2477 .addOperand(SrcRegSub0)
2480 BuildMI(MBB, MII, DL, InstDesc, ResultReg)
2481 .addOperand(SrcRegSub1)
2484 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2486 // We don't need to legalize operands here. src0 for etiher instruction can be
2487 // an SGPR, and the second input is unused or determined here.
2488 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2491 void SIInstrInfo::splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
2492 MachineInstr *Inst) const {
2493 MachineBasicBlock &MBB = *Inst->getParent();
2494 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2495 MachineBasicBlock::iterator MII = Inst;
2496 DebugLoc DL = Inst->getDebugLoc();
2498 MachineOperand &Dest = Inst->getOperand(0);
2499 uint32_t Imm = Inst->getOperand(2).getImm();
2500 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2501 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2505 // Only sext_inreg cases handled.
2506 assert(Inst->getOpcode() == AMDGPU::S_BFE_I64 &&
2511 if (BitWidth < 32) {
2512 unsigned MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2513 unsigned MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2514 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2516 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo)
2517 .addReg(Inst->getOperand(1).getReg(), 0, AMDGPU::sub0)
2521 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi)
2525 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2527 .addImm(AMDGPU::sub0)
2529 .addImm(AMDGPU::sub1);
2531 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2532 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2536 MachineOperand &Src = Inst->getOperand(1);
2537 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2538 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2540 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
2542 .addReg(Src.getReg(), 0, AMDGPU::sub0);
2544 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2545 .addReg(Src.getReg(), 0, AMDGPU::sub0)
2546 .addImm(AMDGPU::sub0)
2548 .addImm(AMDGPU::sub1);
2550 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2551 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2554 void SIInstrInfo::addUsersToMoveToVALUWorklist(
2556 MachineRegisterInfo &MRI,
2557 SmallVectorImpl<MachineInstr *> &Worklist) const {
2558 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(DstReg),
2559 E = MRI.use_end(); I != E; ++I) {
2560 MachineInstr &UseMI = *I->getParent();
2561 if (!canReadVGPR(UseMI, I.getOperandNo())) {
2562 Worklist.push_back(&UseMI);
2567 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
2568 int OpIndices[3]) const {
2569 const MCInstrDesc &Desc = get(MI->getOpcode());
2571 // Find the one SGPR operand we are allowed to use.
2572 unsigned SGPRReg = AMDGPU::NoRegister;
2574 // First we need to consider the instruction's operand requirements before
2575 // legalizing. Some operands are required to be SGPRs, such as implicit uses
2576 // of VCC, but we are still bound by the constant bus requirement to only use
2579 // If the operand's class is an SGPR, we can never move it.
2581 for (const MachineOperand &MO : MI->implicit_operands()) {
2582 // We only care about reads.
2586 if (MO.getReg() == AMDGPU::VCC)
2589 if (MO.getReg() == AMDGPU::FLAT_SCR)
2590 return AMDGPU::FLAT_SCR;
2593 unsigned UsedSGPRs[3] = { AMDGPU::NoRegister };
2594 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
2596 for (unsigned i = 0; i < 3; ++i) {
2597 int Idx = OpIndices[i];
2601 const MachineOperand &MO = MI->getOperand(Idx);
2602 if (RI.isSGPRClassID(Desc.OpInfo[Idx].RegClass))
2603 SGPRReg = MO.getReg();
2605 if (MO.isReg() && RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
2606 UsedSGPRs[i] = MO.getReg();
2609 if (SGPRReg != AMDGPU::NoRegister)
2612 // We don't have a required SGPR operand, so we have a bit more freedom in
2613 // selecting operands to move.
2615 // Try to select the most used SGPR. If an SGPR is equal to one of the
2616 // others, we choose that.
2619 // V_FMA_F32 v0, s0, s0, s0 -> No moves
2620 // V_FMA_F32 v0, s0, s1, s0 -> Move s1
2622 if (UsedSGPRs[0] != AMDGPU::NoRegister) {
2623 if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2])
2624 SGPRReg = UsedSGPRs[0];
2627 if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) {
2628 if (UsedSGPRs[1] == UsedSGPRs[2])
2629 SGPRReg = UsedSGPRs[1];
2635 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
2636 MachineBasicBlock *MBB,
2637 MachineBasicBlock::iterator I,
2639 unsigned Address, unsigned OffsetReg) const {
2640 const DebugLoc &DL = MBB->findDebugLoc(I);
2641 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2642 getIndirectIndexBegin(*MBB->getParent()));
2644 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
2645 .addReg(IndirectBaseReg, RegState::Define)
2646 .addOperand(I->getOperand(0))
2647 .addReg(IndirectBaseReg)
2653 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
2654 MachineBasicBlock *MBB,
2655 MachineBasicBlock::iterator I,
2657 unsigned Address, unsigned OffsetReg) const {
2658 const DebugLoc &DL = MBB->findDebugLoc(I);
2659 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2660 getIndirectIndexBegin(*MBB->getParent()));
2662 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
2663 .addOperand(I->getOperand(0))
2664 .addOperand(I->getOperand(1))
2665 .addReg(IndirectBaseReg)
2671 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
2672 const MachineFunction &MF) const {
2673 int End = getIndirectIndexEnd(MF);
2674 int Begin = getIndirectIndexBegin(MF);
2680 for (int Index = Begin; Index <= End; ++Index)
2681 Reserved.set(AMDGPU::VGPR_32RegClass.getRegister(Index));
2683 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
2684 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
2686 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
2687 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
2689 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
2690 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
2692 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
2693 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
2695 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
2696 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
2699 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
2700 unsigned OperandName) const {
2701 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
2705 return &MI.getOperand(Idx);
2708 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {
2709 uint64_t RsrcDataFormat = AMDGPU::RSRC_DATA_FORMAT;
2710 if (ST.isAmdHsaOS()) {
2711 RsrcDataFormat |= (1ULL << 56);
2713 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2715 RsrcDataFormat |= (2ULL << 59);
2718 return RsrcDataFormat;