1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/Support/Debug.h"
30 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
31 : AMDGPUInstrInfo(st), RI() {}
33 //===----------------------------------------------------------------------===//
34 // TargetInstrInfo callbacks
35 //===----------------------------------------------------------------------===//
37 static unsigned getNumOperandsNoGlue(SDNode *Node) {
38 unsigned N = Node->getNumOperands();
39 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
44 static SDValue findChainOperand(SDNode *Load) {
45 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1);
46 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
50 /// \brief Returns true if both nodes have the same value for the given
51 /// operand \p Op, or if both nodes do not have this operand.
52 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
53 unsigned Opc0 = N0->getMachineOpcode();
54 unsigned Opc1 = N1->getMachineOpcode();
56 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
57 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
59 if (Op0Idx == -1 && Op1Idx == -1)
63 if ((Op0Idx == -1 && Op1Idx != -1) ||
64 (Op1Idx == -1 && Op0Idx != -1))
67 // getNamedOperandIdx returns the index for the MachineInstr's operands,
68 // which includes the result as the first operand. We are indexing into the
69 // MachineSDNode's operands, so we need to skip the result operand to get
74 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
77 bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
78 AliasAnalysis *AA) const {
79 // TODO: The generic check fails for VALU instructions that should be
80 // rematerializable due to implicit reads of exec. We really want all of the
81 // generic logic for this except for this.
82 switch (MI->getOpcode()) {
83 case AMDGPU::V_MOV_B32_e32:
84 case AMDGPU::V_MOV_B32_e64:
85 case AMDGPU::V_MOV_B64_PSEUDO:
92 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
94 int64_t &Offset1) const {
95 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
98 unsigned Opc0 = Load0->getMachineOpcode();
99 unsigned Opc1 = Load1->getMachineOpcode();
101 // Make sure both are actually loads.
102 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
105 if (isDS(Opc0) && isDS(Opc1)) {
107 // FIXME: Handle this case:
108 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
112 if (Load0->getOperand(1) != Load1->getOperand(1))
116 if (findChainOperand(Load0) != findChainOperand(Load1))
119 // Skip read2 / write2 variants for simplicity.
120 // TODO: We should report true if the used offsets are adjacent (excluded
122 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
123 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
126 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
127 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
131 if (isSMRD(Opc0) && isSMRD(Opc1)) {
132 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
135 if (Load0->getOperand(0) != Load1->getOperand(0))
138 const ConstantSDNode *Load0Offset =
139 dyn_cast<ConstantSDNode>(Load0->getOperand(1));
140 const ConstantSDNode *Load1Offset =
141 dyn_cast<ConstantSDNode>(Load1->getOperand(1));
143 if (!Load0Offset || !Load1Offset)
147 if (findChainOperand(Load0) != findChainOperand(Load1))
150 Offset0 = Load0Offset->getZExtValue();
151 Offset1 = Load1Offset->getZExtValue();
155 // MUBUF and MTBUF can access the same addresses.
156 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
158 // MUBUF and MTBUF have vaddr at different indices.
159 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
160 findChainOperand(Load0) != findChainOperand(Load1) ||
161 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
162 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
165 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
166 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
168 if (OffIdx0 == -1 || OffIdx1 == -1)
171 // getNamedOperandIdx returns the index for MachineInstrs. Since they
172 // inlcude the output in the operand list, but SDNodes don't, we need to
173 // subtract the index by one.
177 SDValue Off0 = Load0->getOperand(OffIdx0);
178 SDValue Off1 = Load1->getOperand(OffIdx1);
180 // The offset might be a FrameIndexSDNode.
181 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
184 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
185 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
192 static bool isStride64(unsigned Opc) {
194 case AMDGPU::DS_READ2ST64_B32:
195 case AMDGPU::DS_READ2ST64_B64:
196 case AMDGPU::DS_WRITE2ST64_B32:
197 case AMDGPU::DS_WRITE2ST64_B64:
204 bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
206 const TargetRegisterInfo *TRI) const {
207 unsigned Opc = LdSt->getOpcode();
209 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
210 AMDGPU::OpName::offset);
212 // Normal, single offset LDS instruction.
213 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
214 AMDGPU::OpName::addr);
216 BaseReg = AddrReg->getReg();
217 Offset = OffsetImm->getImm();
221 // The 2 offset instructions use offset0 and offset1 instead. We can treat
222 // these as a load with a single offset if the 2 offsets are consecutive. We
223 // will use this for some partially aligned loads.
224 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
225 AMDGPU::OpName::offset0);
226 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
227 AMDGPU::OpName::offset1);
229 uint8_t Offset0 = Offset0Imm->getImm();
230 uint8_t Offset1 = Offset1Imm->getImm();
232 if (Offset1 > Offset0 && Offset1 - Offset0 == 1) {
233 // Each of these offsets is in element sized units, so we need to convert
234 // to bytes of the individual reads.
238 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
240 assert(LdSt->mayStore());
241 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
242 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
248 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
249 AMDGPU::OpName::addr);
250 BaseReg = AddrReg->getReg();
251 Offset = EltSize * Offset0;
258 if (isMUBUF(Opc) || isMTBUF(Opc)) {
259 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
262 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
263 AMDGPU::OpName::vaddr);
267 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
268 AMDGPU::OpName::offset);
269 BaseReg = AddrReg->getReg();
270 Offset = OffsetImm->getImm();
275 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
276 AMDGPU::OpName::offset);
280 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
281 AMDGPU::OpName::sbase);
282 BaseReg = SBaseReg->getReg();
283 Offset = OffsetImm->getImm();
290 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
291 MachineInstr *SecondLdSt,
292 unsigned NumLoads) const {
293 unsigned Opc0 = FirstLdSt->getOpcode();
294 unsigned Opc1 = SecondLdSt->getOpcode();
296 // TODO: This needs finer tuning
300 if (isDS(Opc0) && isDS(Opc1))
303 if (isSMRD(Opc0) && isSMRD(Opc1))
306 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1)))
313 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
314 MachineBasicBlock::iterator MI, DebugLoc DL,
315 unsigned DestReg, unsigned SrcReg,
316 bool KillSrc) const {
318 // If we are trying to copy to or from SCC, there is a bug somewhere else in
319 // the backend. While it may be theoretically possible to do this, it should
320 // never be necessary.
321 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
323 static const int16_t Sub0_15[] = {
324 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
325 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
326 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
327 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
330 static const int16_t Sub0_7[] = {
331 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
332 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
335 static const int16_t Sub0_3[] = {
336 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
339 static const int16_t Sub0_2[] = {
340 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
343 static const int16_t Sub0_1[] = {
344 AMDGPU::sub0, AMDGPU::sub1, 0
348 const int16_t *SubIndices;
350 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
351 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
352 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
353 .addReg(SrcReg, getKillRegState(KillSrc));
356 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
357 if (DestReg == AMDGPU::VCC) {
358 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
359 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
360 .addReg(SrcReg, getKillRegState(KillSrc));
362 // FIXME: Hack until VReg_1 removed.
363 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
364 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32))
366 .addReg(SrcReg, getKillRegState(KillSrc));
372 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
373 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
374 .addReg(SrcReg, getKillRegState(KillSrc));
377 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
378 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
379 Opcode = AMDGPU::S_MOV_B32;
382 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
383 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
384 Opcode = AMDGPU::S_MOV_B32;
387 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
388 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
389 Opcode = AMDGPU::S_MOV_B32;
390 SubIndices = Sub0_15;
392 } else if (AMDGPU::VGPR_32RegClass.contains(DestReg)) {
393 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
394 AMDGPU::SReg_32RegClass.contains(SrcReg));
395 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
396 .addReg(SrcReg, getKillRegState(KillSrc));
399 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
400 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
401 AMDGPU::SReg_64RegClass.contains(SrcReg));
402 Opcode = AMDGPU::V_MOV_B32_e32;
405 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
406 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
407 Opcode = AMDGPU::V_MOV_B32_e32;
410 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
411 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
412 AMDGPU::SReg_128RegClass.contains(SrcReg));
413 Opcode = AMDGPU::V_MOV_B32_e32;
416 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
417 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
418 AMDGPU::SReg_256RegClass.contains(SrcReg));
419 Opcode = AMDGPU::V_MOV_B32_e32;
422 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
423 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
424 AMDGPU::SReg_512RegClass.contains(SrcReg));
425 Opcode = AMDGPU::V_MOV_B32_e32;
426 SubIndices = Sub0_15;
429 llvm_unreachable("Can't copy register!");
432 while (unsigned SubIdx = *SubIndices++) {
433 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
434 get(Opcode), RI.getSubReg(DestReg, SubIdx));
436 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
439 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
443 int SIInstrInfo::commuteOpcode(const MachineInstr &MI) const {
444 const unsigned Opcode = MI.getOpcode();
448 // Try to map original to commuted opcode
449 NewOpc = AMDGPU::getCommuteRev(Opcode);
451 // Check if the commuted (REV) opcode exists on the target.
452 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
454 // Try to map commuted to original opcode
455 NewOpc = AMDGPU::getCommuteOrig(Opcode);
457 // Check if the original (non-REV) opcode exists on the target.
458 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
463 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
465 if (DstRC->getSize() == 4) {
466 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
467 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) {
468 return AMDGPU::S_MOV_B64;
469 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) {
470 return AMDGPU::V_MOV_B64_PSEUDO;
475 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
476 MachineBasicBlock::iterator MI,
477 unsigned SrcReg, bool isKill,
479 const TargetRegisterClass *RC,
480 const TargetRegisterInfo *TRI) const {
481 MachineFunction *MF = MBB.getParent();
482 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
483 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
484 DebugLoc DL = MBB.findDebugLoc(MI);
487 if (RI.isSGPRClass(RC)) {
488 // We are only allowed to create one new instruction when spilling
489 // registers, so we need to use pseudo instruction for spilling
491 switch (RC->getSize() * 8) {
492 case 32: Opcode = AMDGPU::SI_SPILL_S32_SAVE; break;
493 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
494 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
495 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
496 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
498 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
499 MFI->setHasSpilledVGPRs();
501 switch(RC->getSize() * 8) {
502 case 32: Opcode = AMDGPU::SI_SPILL_V32_SAVE; break;
503 case 64: Opcode = AMDGPU::SI_SPILL_V64_SAVE; break;
504 case 96: Opcode = AMDGPU::SI_SPILL_V96_SAVE; break;
505 case 128: Opcode = AMDGPU::SI_SPILL_V128_SAVE; break;
506 case 256: Opcode = AMDGPU::SI_SPILL_V256_SAVE; break;
507 case 512: Opcode = AMDGPU::SI_SPILL_V512_SAVE; break;
512 MachinePointerInfo PtrInfo
513 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
514 unsigned Size = FrameInfo->getObjectSize(FrameIndex);
515 unsigned Align = FrameInfo->getObjectAlignment(FrameIndex);
516 MachineMemOperand *MMO
517 = MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
520 FrameInfo->setObjectAlignment(FrameIndex, 4);
521 BuildMI(MBB, MI, DL, get(Opcode))
523 .addFrameIndex(FrameIndex)
524 // Place-holder registers, these will be filled in by
525 // SIPrepareScratchRegs.
526 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
527 .addReg(AMDGPU::SGPR0, RegState::Undef)
530 LLVMContext &Ctx = MF->getFunction()->getContext();
531 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
533 BuildMI(MBB, MI, DL, get(AMDGPU::KILL))
538 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
539 MachineBasicBlock::iterator MI,
540 unsigned DestReg, int FrameIndex,
541 const TargetRegisterClass *RC,
542 const TargetRegisterInfo *TRI) const {
543 MachineFunction *MF = MBB.getParent();
544 const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
545 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
546 DebugLoc DL = MBB.findDebugLoc(MI);
549 if (RI.isSGPRClass(RC)){
550 switch(RC->getSize() * 8) {
551 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
552 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
553 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
554 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
555 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
557 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
558 switch(RC->getSize() * 8) {
559 case 32: Opcode = AMDGPU::SI_SPILL_V32_RESTORE; break;
560 case 64: Opcode = AMDGPU::SI_SPILL_V64_RESTORE; break;
561 case 96: Opcode = AMDGPU::SI_SPILL_V96_RESTORE; break;
562 case 128: Opcode = AMDGPU::SI_SPILL_V128_RESTORE; break;
563 case 256: Opcode = AMDGPU::SI_SPILL_V256_RESTORE; break;
564 case 512: Opcode = AMDGPU::SI_SPILL_V512_RESTORE; break;
570 FrameInfo->setObjectAlignment(FrameIndex, Align);
571 unsigned Size = FrameInfo->getObjectSize(FrameIndex);
573 MachinePointerInfo PtrInfo
574 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
575 MachineMemOperand *MMO = MF->getMachineMemOperand(
576 PtrInfo, MachineMemOperand::MOLoad, Size, Align);
578 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
579 .addFrameIndex(FrameIndex)
580 // Place-holder registers, these will be filled in by
581 // SIPrepareScratchRegs.
582 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
583 .addReg(AMDGPU::SGPR0, RegState::Undef)
586 LLVMContext &Ctx = MF->getFunction()->getContext();
587 Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"
588 " restore register");
589 BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg);
593 /// \param @Offset Offset in bytes of the FrameIndex being spilled
594 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
595 MachineBasicBlock::iterator MI,
596 RegScavenger *RS, unsigned TmpReg,
597 unsigned FrameOffset,
598 unsigned Size) const {
599 MachineFunction *MF = MBB.getParent();
600 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
601 const AMDGPUSubtarget &ST = MF->getSubtarget<AMDGPUSubtarget>();
602 const SIRegisterInfo *TRI =
603 static_cast<const SIRegisterInfo*>(ST.getRegisterInfo());
604 DebugLoc DL = MBB.findDebugLoc(MI);
605 unsigned WorkGroupSize = MFI->getMaximumWorkGroupSize(*MF);
606 unsigned WavefrontSize = ST.getWavefrontSize();
608 unsigned TIDReg = MFI->getTIDReg();
609 if (!MFI->hasCalculatedTID()) {
610 MachineBasicBlock &Entry = MBB.getParent()->front();
611 MachineBasicBlock::iterator Insert = Entry.front();
612 DebugLoc DL = Insert->getDebugLoc();
614 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);
615 if (TIDReg == AMDGPU::NoRegister)
619 if (MFI->getShaderType() == ShaderType::COMPUTE &&
620 WorkGroupSize > WavefrontSize) {
622 unsigned TIDIGXReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_X);
623 unsigned TIDIGYReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Y);
624 unsigned TIDIGZReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Z);
625 unsigned InputPtrReg =
626 TRI->getPreloadedValue(*MF, SIRegisterInfo::INPUT_PTR);
627 for (unsigned Reg : {TIDIGXReg, TIDIGYReg, TIDIGZReg}) {
628 if (!Entry.isLiveIn(Reg))
629 Entry.addLiveIn(Reg);
632 RS->enterBasicBlock(&Entry);
633 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
634 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
635 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
637 .addImm(SI::KernelInputOffsets::NGROUPS_Z);
638 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
640 .addImm(SI::KernelInputOffsets::NGROUPS_Y);
642 // NGROUPS.X * NGROUPS.Y
643 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
646 // (NGROUPS.X * NGROUPS.Y) * TIDIG.X
647 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
650 // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)
651 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
655 // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z
656 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg)
661 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
666 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64),
672 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
676 MFI->setTIDReg(TIDReg);
679 // Add FrameIndex to LDS offset
680 unsigned LDSOffset = MFI->LDSSize + (FrameOffset * WorkGroupSize);
681 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg)
688 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
697 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
702 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
703 MachineBasicBlock &MBB = *MI->getParent();
704 DebugLoc DL = MBB.findDebugLoc(MI);
705 switch (MI->getOpcode()) {
706 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
708 case AMDGPU::SI_CONSTDATA_PTR: {
709 unsigned Reg = MI->getOperand(0).getReg();
710 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
711 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
713 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg);
715 // Add 32-bit offset from this instruction to the start of the constant data.
716 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_U32), RegLo)
718 .addTargetIndex(AMDGPU::TI_CONSTDATA_START)
719 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit);
720 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi)
723 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit)
724 .addReg(AMDGPU::SCC, RegState::Implicit);
725 MI->eraseFromParent();
728 case AMDGPU::SGPR_USE:
729 // This is just a placeholder for register allocation.
730 MI->eraseFromParent();
733 case AMDGPU::V_MOV_B64_PSEUDO: {
734 unsigned Dst = MI->getOperand(0).getReg();
735 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
736 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
738 const MachineOperand &SrcOp = MI->getOperand(1);
739 // FIXME: Will this work for 64-bit floating point immediates?
740 assert(!SrcOp.isFPImm());
742 APInt Imm(64, SrcOp.getImm());
743 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
744 .addImm(Imm.getLoBits(32).getZExtValue())
745 .addReg(Dst, RegState::Implicit);
746 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
747 .addImm(Imm.getHiBits(32).getZExtValue())
748 .addReg(Dst, RegState::Implicit);
750 assert(SrcOp.isReg());
751 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
752 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
753 .addReg(Dst, RegState::Implicit);
754 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
755 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
756 .addReg(Dst, RegState::Implicit);
758 MI->eraseFromParent();
762 case AMDGPU::V_CNDMASK_B64_PSEUDO: {
763 unsigned Dst = MI->getOperand(0).getReg();
764 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
765 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
766 unsigned Src0 = MI->getOperand(1).getReg();
767 unsigned Src1 = MI->getOperand(2).getReg();
768 const MachineOperand &SrcCond = MI->getOperand(3);
770 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
771 .addReg(RI.getSubReg(Src0, AMDGPU::sub0))
772 .addReg(RI.getSubReg(Src1, AMDGPU::sub0))
773 .addOperand(SrcCond);
774 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
775 .addReg(RI.getSubReg(Src0, AMDGPU::sub1))
776 .addReg(RI.getSubReg(Src1, AMDGPU::sub1))
777 .addOperand(SrcCond);
778 MI->eraseFromParent();
785 /// Commutes the operands in the given instruction.
786 /// The commutable operands are specified by their indices OpIdx0 and OpIdx1.
788 /// Do not call this method for a non-commutable instruction or for
789 /// non-commutable pair of operand indices OpIdx0 and OpIdx1.
790 /// Even though the instruction is commutable, the method may still
791 /// fail to commute the operands, null pointer is returned in such cases.
792 MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr *MI,
795 unsigned OpIdx1) const {
796 int CommutedOpcode = commuteOpcode(*MI);
797 if (CommutedOpcode == -1)
800 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
801 AMDGPU::OpName::src0);
802 MachineOperand &Src0 = MI->getOperand(Src0Idx);
806 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
807 AMDGPU::OpName::src1);
809 if ((OpIdx0 != static_cast<unsigned>(Src0Idx) ||
810 OpIdx1 != static_cast<unsigned>(Src1Idx)) &&
811 (OpIdx0 != static_cast<unsigned>(Src1Idx) ||
812 OpIdx1 != static_cast<unsigned>(Src0Idx)))
815 MachineOperand &Src1 = MI->getOperand(Src1Idx);
817 // Make sure it's legal to commute operands for VOP2.
818 if (isVOP2(MI->getOpcode()) &&
819 (!isOperandLegal(MI, Src0Idx, &Src1) ||
820 !isOperandLegal(MI, Src1Idx, &Src0))) {
825 // Allow commuting instructions with Imm operands.
826 if (NewMI || !Src1.isImm() ||
827 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
831 // Be sure to copy the source modifiers to the right place.
832 if (MachineOperand *Src0Mods
833 = getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) {
834 MachineOperand *Src1Mods
835 = getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers);
837 int Src0ModsVal = Src0Mods->getImm();
838 if (!Src1Mods && Src0ModsVal != 0)
841 // XXX - This assert might be a lie. It might be useful to have a neg
842 // modifier with 0.0.
843 int Src1ModsVal = Src1Mods->getImm();
844 assert((Src1ModsVal == 0) && "Not expecting modifiers with immediates");
846 Src1Mods->setImm(Src0ModsVal);
847 Src0Mods->setImm(Src1ModsVal);
850 unsigned Reg = Src0.getReg();
851 unsigned SubReg = Src0.getSubReg();
853 Src0.ChangeToImmediate(Src1.getImm());
855 llvm_unreachable("Should only have immediates");
857 Src1.ChangeToRegister(Reg, false);
858 Src1.setSubReg(SubReg);
860 MI = TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx0, OpIdx1);
864 MI->setDesc(get(CommutedOpcode));
869 // This needs to be implemented because the source modifiers may be inserted
870 // between the true commutable operands, and the base
871 // TargetInstrInfo::commuteInstruction uses it.
872 bool SIInstrInfo::findCommutedOpIndices(MachineInstr *MI,
874 unsigned &SrcOpIdx1) const {
875 const MCInstrDesc &MCID = MI->getDesc();
876 if (!MCID.isCommutable())
879 unsigned Opc = MI->getOpcode();
880 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
884 // FIXME: Workaround TargetInstrInfo::commuteInstruction asserting on
885 // immediate. Also, immediate src0 operand is not handled in
886 // SIInstrInfo::commuteInstruction();
887 if (!MI->getOperand(Src0Idx).isReg())
890 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
894 MachineOperand &Src1 = MI->getOperand(Src1Idx);
896 // SIInstrInfo::commuteInstruction() does support commuting the immediate
897 // operand src1 in 2 and 3 operand instructions.
898 if (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))
900 } else if (Src1.isReg()) {
901 // If any source modifiers are set, the generic instruction commuting won't
902 // understand how to copy the source modifiers.
903 if (hasModifiersSet(*MI, AMDGPU::OpName::src0_modifiers) ||
904 hasModifiersSet(*MI, AMDGPU::OpName::src1_modifiers))
909 return fixCommutedOpIndices(SrcOpIdx0, SrcOpIdx1, Src0Idx, Src1Idx);
912 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
913 MachineBasicBlock::iterator I,
915 unsigned SrcReg) const {
916 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
917 DstReg) .addReg(SrcReg);
920 bool SIInstrInfo::isMov(unsigned Opcode) const {
922 default: return false;
923 case AMDGPU::S_MOV_B32:
924 case AMDGPU::S_MOV_B64:
925 case AMDGPU::V_MOV_B32_e32:
926 case AMDGPU::V_MOV_B32_e64:
931 static void removeModOperands(MachineInstr &MI) {
932 unsigned Opc = MI.getOpcode();
933 int Src0ModIdx = AMDGPU::getNamedOperandIdx(Opc,
934 AMDGPU::OpName::src0_modifiers);
935 int Src1ModIdx = AMDGPU::getNamedOperandIdx(Opc,
936 AMDGPU::OpName::src1_modifiers);
937 int Src2ModIdx = AMDGPU::getNamedOperandIdx(Opc,
938 AMDGPU::OpName::src2_modifiers);
940 MI.RemoveOperand(Src2ModIdx);
941 MI.RemoveOperand(Src1ModIdx);
942 MI.RemoveOperand(Src0ModIdx);
945 bool SIInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
946 unsigned Reg, MachineRegisterInfo *MRI) const {
947 if (!MRI->hasOneNonDBGUse(Reg))
950 unsigned Opc = UseMI->getOpcode();
951 if (Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64) {
952 // Don't fold if we are using source modifiers. The new VOP2 instructions
954 if (hasModifiersSet(*UseMI, AMDGPU::OpName::src0_modifiers) ||
955 hasModifiersSet(*UseMI, AMDGPU::OpName::src1_modifiers) ||
956 hasModifiersSet(*UseMI, AMDGPU::OpName::src2_modifiers)) {
960 MachineOperand *Src0 = getNamedOperand(*UseMI, AMDGPU::OpName::src0);
961 MachineOperand *Src1 = getNamedOperand(*UseMI, AMDGPU::OpName::src1);
962 MachineOperand *Src2 = getNamedOperand(*UseMI, AMDGPU::OpName::src2);
964 // Multiplied part is the constant: Use v_madmk_f32
965 // We should only expect these to be on src0 due to canonicalizations.
966 if (Src0->isReg() && Src0->getReg() == Reg) {
967 if (!Src1->isReg() ||
968 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
971 if (!Src2->isReg() ||
972 (Src2->isReg() && RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))))
975 // We need to do some weird looking operand shuffling since the madmk
976 // operands are out of the normal expected order with the multiplied
977 // constant as the last operand.
979 // v_mad_f32 src0, src1, src2 -> v_madmk_f32 src0 * src2K + src1
984 const int64_t Imm = DefMI->getOperand(1).getImm();
986 // FIXME: This would be a lot easier if we could return a new instruction
987 // instead of having to modify in place.
989 // Remove these first since they are at the end.
990 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
991 AMDGPU::OpName::omod));
992 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
993 AMDGPU::OpName::clamp));
995 unsigned Src1Reg = Src1->getReg();
996 unsigned Src1SubReg = Src1->getSubReg();
997 unsigned Src2Reg = Src2->getReg();
998 unsigned Src2SubReg = Src2->getSubReg();
999 Src0->setReg(Src1Reg);
1000 Src0->setSubReg(Src1SubReg);
1001 Src0->setIsKill(Src1->isKill());
1003 Src1->setReg(Src2Reg);
1004 Src1->setSubReg(Src2SubReg);
1005 Src1->setIsKill(Src2->isKill());
1007 if (Opc == AMDGPU::V_MAC_F32_e64) {
1008 UseMI->untieRegOperand(
1009 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
1012 Src2->ChangeToImmediate(Imm);
1014 removeModOperands(*UseMI);
1015 UseMI->setDesc(get(AMDGPU::V_MADMK_F32));
1017 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1019 DefMI->eraseFromParent();
1024 // Added part is the constant: Use v_madak_f32
1025 if (Src2->isReg() && Src2->getReg() == Reg) {
1026 // Not allowed to use constant bus for another operand.
1027 // We can however allow an inline immediate as src0.
1028 if (!Src0->isImm() &&
1029 (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg()))))
1032 if (!Src1->isReg() ||
1033 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
1036 const int64_t Imm = DefMI->getOperand(1).getImm();
1038 // FIXME: This would be a lot easier if we could return a new instruction
1039 // instead of having to modify in place.
1041 // Remove these first since they are at the end.
1042 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1043 AMDGPU::OpName::omod));
1044 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1045 AMDGPU::OpName::clamp));
1047 if (Opc == AMDGPU::V_MAC_F32_e64) {
1048 UseMI->untieRegOperand(
1049 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
1052 // ChangingToImmediate adds Src2 back to the instruction.
1053 Src2->ChangeToImmediate(Imm);
1055 // These come before src2.
1056 removeModOperands(*UseMI);
1057 UseMI->setDesc(get(AMDGPU::V_MADAK_F32));
1059 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1061 DefMI->eraseFromParent();
1070 static bool offsetsDoNotOverlap(int WidthA, int OffsetA,
1071 int WidthB, int OffsetB) {
1072 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
1073 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
1074 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
1075 return LowOffset + LowWidth <= HighOffset;
1078 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
1079 MachineInstr *MIb) const {
1080 unsigned BaseReg0, Offset0;
1081 unsigned BaseReg1, Offset1;
1083 if (getMemOpBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) &&
1084 getMemOpBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) {
1085 assert(MIa->hasOneMemOperand() && MIb->hasOneMemOperand() &&
1086 "read2 / write2 not expected here yet");
1087 unsigned Width0 = (*MIa->memoperands_begin())->getSize();
1088 unsigned Width1 = (*MIb->memoperands_begin())->getSize();
1089 if (BaseReg0 == BaseReg1 &&
1090 offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) {
1098 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
1100 AliasAnalysis *AA) const {
1101 unsigned Opc0 = MIa->getOpcode();
1102 unsigned Opc1 = MIb->getOpcode();
1104 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
1105 "MIa must load from or modify a memory location");
1106 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
1107 "MIb must load from or modify a memory location");
1109 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects())
1112 // XXX - Can we relax this between address spaces?
1113 if (MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
1116 // TODO: Should we check the address space from the MachineMemOperand? That
1117 // would allow us to distinguish objects we know don't alias based on the
1118 // underlying address space, even if it was lowered to a different one,
1119 // e.g. private accesses lowered to use MUBUF instructions on a scratch
1123 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1125 return !isFLAT(Opc1);
1128 if (isMUBUF(Opc0) || isMTBUF(Opc0)) {
1129 if (isMUBUF(Opc1) || isMTBUF(Opc1))
1130 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1132 return !isFLAT(Opc1) && !isSMRD(Opc1);
1137 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1139 return !isFLAT(Opc1) && !isMUBUF(Opc0) && !isMTBUF(Opc0);
1144 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1152 MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB,
1153 MachineBasicBlock::iterator &MI,
1154 LiveVariables *LV) const {
1156 switch (MI->getOpcode()) {
1157 default: return nullptr;
1158 case AMDGPU::V_MAC_F32_e64: break;
1159 case AMDGPU::V_MAC_F32_e32: {
1160 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
1161 if (Src0->isImm() && !isInlineConstant(*Src0, 4))
1167 const MachineOperand *Dst = getNamedOperand(*MI, AMDGPU::OpName::dst);
1168 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
1169 const MachineOperand *Src1 = getNamedOperand(*MI, AMDGPU::OpName::src1);
1170 const MachineOperand *Src2 = getNamedOperand(*MI, AMDGPU::OpName::src2);
1172 return BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_MAD_F32))
1174 .addImm(0) // Src0 mods
1176 .addImm(0) // Src1 mods
1178 .addImm(0) // Src mods
1184 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
1185 int64_t SVal = Imm.getSExtValue();
1186 if (SVal >= -16 && SVal <= 64)
1189 if (Imm.getBitWidth() == 64) {
1190 uint64_t Val = Imm.getZExtValue();
1191 return (DoubleToBits(0.0) == Val) ||
1192 (DoubleToBits(1.0) == Val) ||
1193 (DoubleToBits(-1.0) == Val) ||
1194 (DoubleToBits(0.5) == Val) ||
1195 (DoubleToBits(-0.5) == Val) ||
1196 (DoubleToBits(2.0) == Val) ||
1197 (DoubleToBits(-2.0) == Val) ||
1198 (DoubleToBits(4.0) == Val) ||
1199 (DoubleToBits(-4.0) == Val);
1202 // The actual type of the operand does not seem to matter as long
1203 // as the bits match one of the inline immediate values. For example:
1205 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
1206 // so it is a legal inline immediate.
1208 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
1209 // floating-point, so it is a legal inline immediate.
1210 uint32_t Val = Imm.getZExtValue();
1212 return (FloatToBits(0.0f) == Val) ||
1213 (FloatToBits(1.0f) == Val) ||
1214 (FloatToBits(-1.0f) == Val) ||
1215 (FloatToBits(0.5f) == Val) ||
1216 (FloatToBits(-0.5f) == Val) ||
1217 (FloatToBits(2.0f) == Val) ||
1218 (FloatToBits(-2.0f) == Val) ||
1219 (FloatToBits(4.0f) == Val) ||
1220 (FloatToBits(-4.0f) == Val);
1223 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,
1224 unsigned OpSize) const {
1226 // MachineOperand provides no way to tell the true operand size, since it
1227 // only records a 64-bit value. We need to know the size to determine if a
1228 // 32-bit floating point immediate bit pattern is legal for an integer
1229 // immediate. It would be for any 32-bit integer operand, but would not be
1230 // for a 64-bit one.
1232 unsigned BitSize = 8 * OpSize;
1233 return isInlineConstant(APInt(BitSize, MO.getImm(), true));
1239 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO,
1240 unsigned OpSize) const {
1241 return MO.isImm() && !isInlineConstant(MO, OpSize);
1244 static bool compareMachineOp(const MachineOperand &Op0,
1245 const MachineOperand &Op1) {
1246 if (Op0.getType() != Op1.getType())
1249 switch (Op0.getType()) {
1250 case MachineOperand::MO_Register:
1251 return Op0.getReg() == Op1.getReg();
1252 case MachineOperand::MO_Immediate:
1253 return Op0.getImm() == Op1.getImm();
1255 llvm_unreachable("Didn't expect to be comparing these operand types");
1259 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
1260 const MachineOperand &MO) const {
1261 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
1263 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
1265 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
1268 if (OpInfo.RegClass < 0)
1271 unsigned OpSize = RI.getRegClass(OpInfo.RegClass)->getSize();
1272 if (isLiteralConstant(MO, OpSize))
1273 return RI.opCanUseLiteralConstant(OpInfo.OperandType);
1275 return RI.opCanUseInlineConstant(OpInfo.OperandType);
1278 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
1279 int Op32 = AMDGPU::getVOPe32(Opcode);
1283 return pseudoToMCOpcode(Op32) != -1;
1286 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
1287 // The src0_modifier operand is present on all instructions
1288 // that have modifiers.
1290 return AMDGPU::getNamedOperandIdx(Opcode,
1291 AMDGPU::OpName::src0_modifiers) != -1;
1294 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,
1295 unsigned OpName) const {
1296 const MachineOperand *Mods = getNamedOperand(MI, OpName);
1297 return Mods && Mods->getImm();
1300 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
1301 const MachineOperand &MO,
1302 unsigned OpSize) const {
1303 // Literal constants use the constant bus.
1304 if (isLiteralConstant(MO, OpSize))
1307 if (!MO.isReg() || !MO.isUse())
1310 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1311 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
1313 // FLAT_SCR is just an SGPR pair.
1314 if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
1317 // EXEC register uses the constant bus.
1318 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
1321 // SGPRs use the constant bus
1322 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
1323 (!MO.isImplicit() &&
1324 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
1325 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
1332 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
1333 StringRef &ErrInfo) const {
1334 uint16_t Opcode = MI->getOpcode();
1335 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1336 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
1337 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
1338 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
1340 // Make sure the number of operands is correct.
1341 const MCInstrDesc &Desc = get(Opcode);
1342 if (!Desc.isVariadic() &&
1343 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
1344 ErrInfo = "Instruction has wrong number of operands.";
1348 // Make sure the register classes are correct
1349 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
1350 if (MI->getOperand(i).isFPImm()) {
1351 ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast "
1352 "all fp values to integers.";
1356 int RegClass = Desc.OpInfo[i].RegClass;
1358 switch (Desc.OpInfo[i].OperandType) {
1359 case MCOI::OPERAND_REGISTER:
1360 if (MI->getOperand(i).isImm()) {
1361 ErrInfo = "Illegal immediate value for operand.";
1365 case AMDGPU::OPERAND_REG_IMM32:
1367 case AMDGPU::OPERAND_REG_INLINE_C:
1368 if (isLiteralConstant(MI->getOperand(i),
1369 RI.getRegClass(RegClass)->getSize())) {
1370 ErrInfo = "Illegal immediate value for operand.";
1374 case MCOI::OPERAND_IMMEDIATE:
1375 // Check if this operand is an immediate.
1376 // FrameIndex operands will be replaced by immediates, so they are
1378 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFI()) {
1379 ErrInfo = "Expected immediate, but got non-immediate";
1387 if (!MI->getOperand(i).isReg())
1390 if (RegClass != -1) {
1391 unsigned Reg = MI->getOperand(i).getReg();
1392 if (TargetRegisterInfo::isVirtualRegister(Reg))
1395 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
1396 if (!RC->contains(Reg)) {
1397 ErrInfo = "Operand has incorrect register class.";
1405 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
1406 // Only look at the true operands. Only a real operand can use the constant
1407 // bus, and we don't want to check pseudo-operands like the source modifier
1409 const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
1411 unsigned ConstantBusCount = 0;
1412 unsigned SGPRUsed = AMDGPU::NoRegister;
1413 for (int OpIdx : OpIndices) {
1416 const MachineOperand &MO = MI->getOperand(OpIdx);
1417 if (usesConstantBus(MRI, MO, getOpSize(Opcode, OpIdx))) {
1419 if (MO.getReg() != SGPRUsed)
1421 SGPRUsed = MO.getReg();
1427 if (ConstantBusCount > 1) {
1428 ErrInfo = "VOP* instruction uses the constant bus more than once";
1433 // Verify misc. restrictions on specific instructions.
1434 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
1435 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
1436 const MachineOperand &Src0 = MI->getOperand(Src0Idx);
1437 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1438 const MachineOperand &Src2 = MI->getOperand(Src2Idx);
1439 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
1440 if (!compareMachineOp(Src0, Src1) &&
1441 !compareMachineOp(Src0, Src2)) {
1442 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
1451 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
1452 switch (MI.getOpcode()) {
1453 default: return AMDGPU::INSTRUCTION_LIST_END;
1454 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
1455 case AMDGPU::COPY: return AMDGPU::COPY;
1456 case AMDGPU::PHI: return AMDGPU::PHI;
1457 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
1458 case AMDGPU::S_MOV_B32:
1459 return MI.getOperand(1).isReg() ?
1460 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
1461 case AMDGPU::S_ADD_I32:
1462 case AMDGPU::S_ADD_U32: return AMDGPU::V_ADD_I32_e32;
1463 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
1464 case AMDGPU::S_SUB_I32:
1465 case AMDGPU::S_SUB_U32: return AMDGPU::V_SUB_I32_e32;
1466 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
1467 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32;
1468 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
1469 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
1470 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
1471 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
1472 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
1473 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
1474 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
1475 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
1476 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
1477 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
1478 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
1479 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
1480 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
1481 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
1482 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
1483 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
1484 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
1485 case AMDGPU::S_BFM_B32: return AMDGPU::V_BFM_B32_e64;
1486 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
1487 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
1488 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
1489 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
1490 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
1491 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
1492 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
1493 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
1494 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
1495 case AMDGPU::S_LOAD_DWORD_IMM:
1496 case AMDGPU::S_LOAD_DWORD_SGPR: return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1497 case AMDGPU::S_LOAD_DWORDX2_IMM:
1498 case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1499 case AMDGPU::S_LOAD_DWORDX4_IMM:
1500 case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1501 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
1502 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
1503 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
1504 case AMDGPU::S_FLBIT_I32: return AMDGPU::V_FFBH_I32_e64;
1508 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
1509 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
1512 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
1513 unsigned OpNo) const {
1514 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1515 const MCInstrDesc &Desc = get(MI.getOpcode());
1516 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
1517 Desc.OpInfo[OpNo].RegClass == -1) {
1518 unsigned Reg = MI.getOperand(OpNo).getReg();
1520 if (TargetRegisterInfo::isVirtualRegister(Reg))
1521 return MRI.getRegClass(Reg);
1522 return RI.getPhysRegClass(Reg);
1525 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
1526 return RI.getRegClass(RCID);
1529 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
1530 switch (MI.getOpcode()) {
1532 case AMDGPU::REG_SEQUENCE:
1534 case AMDGPU::INSERT_SUBREG:
1535 return RI.hasVGPRs(getOpRegClass(MI, 0));
1537 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
1541 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
1542 MachineBasicBlock::iterator I = MI;
1543 MachineBasicBlock *MBB = MI->getParent();
1544 MachineOperand &MO = MI->getOperand(OpIdx);
1545 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1546 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
1547 const TargetRegisterClass *RC = RI.getRegClass(RCID);
1548 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1550 Opcode = AMDGPU::COPY;
1551 else if (RI.isSGPRClass(RC))
1552 Opcode = AMDGPU::S_MOV_B32;
1555 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
1556 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC))
1557 VRC = &AMDGPU::VReg_64RegClass;
1559 VRC = &AMDGPU::VGPR_32RegClass;
1561 unsigned Reg = MRI.createVirtualRegister(VRC);
1562 DebugLoc DL = MBB->findDebugLoc(I);
1563 BuildMI(*MI->getParent(), I, DL, get(Opcode), Reg)
1565 MO.ChangeToRegister(Reg, false);
1568 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
1569 MachineRegisterInfo &MRI,
1570 MachineOperand &SuperReg,
1571 const TargetRegisterClass *SuperRC,
1573 const TargetRegisterClass *SubRC)
1575 MachineBasicBlock *MBB = MI->getParent();
1576 DebugLoc DL = MI->getDebugLoc();
1577 unsigned SubReg = MRI.createVirtualRegister(SubRC);
1579 if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) {
1580 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1581 .addReg(SuperReg.getReg(), 0, SubIdx);
1585 // Just in case the super register is itself a sub-register, copy it to a new
1586 // value so we don't need to worry about merging its subreg index with the
1587 // SubIdx passed to this function. The register coalescer should be able to
1588 // eliminate this extra copy.
1589 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
1591 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
1592 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
1594 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1595 .addReg(NewSuperReg, 0, SubIdx);
1600 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
1601 MachineBasicBlock::iterator MII,
1602 MachineRegisterInfo &MRI,
1604 const TargetRegisterClass *SuperRC,
1606 const TargetRegisterClass *SubRC) const {
1608 // XXX - Is there a better way to do this?
1609 if (SubIdx == AMDGPU::sub0)
1610 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
1611 if (SubIdx == AMDGPU::sub1)
1612 return MachineOperand::CreateImm(Op.getImm() >> 32);
1614 llvm_unreachable("Unhandled register index for immediate");
1617 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
1619 return MachineOperand::CreateReg(SubReg, false);
1622 // Change the order of operands from (0, 1, 2) to (0, 2, 1)
1623 void SIInstrInfo::swapOperands(MachineBasicBlock::iterator Inst) const {
1624 assert(Inst->getNumExplicitOperands() == 3);
1625 MachineOperand Op1 = Inst->getOperand(1);
1626 Inst->RemoveOperand(1);
1627 Inst->addOperand(Op1);
1630 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1631 const MachineOperand *MO) const {
1632 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1633 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1634 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
1635 const TargetRegisterClass *DefinedRC =
1636 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
1638 MO = &MI->getOperand(OpIdx);
1640 if (isVALU(InstDesc.Opcode) &&
1641 usesConstantBus(MRI, *MO, DefinedRC->getSize())) {
1643 MO->isReg() ? MO->getReg() : (unsigned)AMDGPU::NoRegister;
1644 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1647 const MachineOperand &Op = MI->getOperand(i);
1648 if (Op.isReg() && Op.getReg() != SGPRUsed &&
1649 usesConstantBus(MRI, Op, getOpSize(*MI, i))) {
1657 const TargetRegisterClass *RC =
1658 TargetRegisterInfo::isVirtualRegister(MO->getReg()) ?
1659 MRI.getRegClass(MO->getReg()) :
1660 RI.getPhysRegClass(MO->getReg());
1662 // In order to be legal, the common sub-class must be equal to the
1663 // class of the current operand. For example:
1665 // v_mov_b32 s0 ; Operand defined as vsrc_32
1666 // ; RI.getCommonSubClass(s0,vsrc_32) = sgpr ; LEGAL
1668 // s_sendmsg 0, s0 ; Operand defined as m0reg
1669 // ; RI.getCommonSubClass(s0,m0reg) = m0reg ; NOT LEGAL
1671 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC;
1675 // Handle non-register types that are treated like immediates.
1676 assert(MO->isImm() || MO->isTargetIndex() || MO->isFI());
1679 // This operand expects an immediate.
1683 return isImmOperandLegal(MI, OpIdx, *MO);
1686 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1687 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1689 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1690 AMDGPU::OpName::src0);
1691 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1692 AMDGPU::OpName::src1);
1693 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1694 AMDGPU::OpName::src2);
1697 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
1699 if (!isOperandLegal(MI, Src0Idx))
1700 legalizeOpWithMove(MI, Src0Idx);
1703 if (isOperandLegal(MI, Src1Idx))
1706 // Usually src0 of VOP2 instructions allow more types of inputs
1707 // than src1, so try to commute the instruction to decrease our
1708 // chances of having to insert a MOV instruction to legalize src1.
1709 if (MI->isCommutable()) {
1710 if (commuteInstruction(MI))
1711 // If we are successful in commuting, then we know MI is legal, so
1716 legalizeOpWithMove(MI, Src1Idx);
1720 // XXX - Do any VOP3 instructions read VCC?
1722 if (isVOP3(MI->getOpcode())) {
1723 int VOP3Idx[3] = { Src0Idx, Src1Idx, Src2Idx };
1725 // Find the one SGPR operand we are allowed to use.
1726 unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx);
1728 for (unsigned i = 0; i < 3; ++i) {
1729 int Idx = VOP3Idx[i];
1732 MachineOperand &MO = MI->getOperand(Idx);
1735 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1736 continue; // VGPRs are legal
1738 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
1740 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1741 SGPRReg = MO.getReg();
1742 // We can use one SGPR in each VOP3 instruction.
1745 } else if (!isLiteralConstant(MO, getOpSize(MI->getOpcode(), Idx))) {
1746 // If it is not a register and not a literal constant, then it must be
1747 // an inline constant which is always legal.
1750 // If we make it this far, then the operand is not legal and we must
1752 legalizeOpWithMove(MI, Idx);
1758 // Legalize REG_SEQUENCE and PHI
1759 // The register class of the operands much be the same type as the register
1760 // class of the output.
1761 if (MI->getOpcode() == AMDGPU::PHI) {
1762 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1763 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1764 if (!MI->getOperand(i).isReg() ||
1765 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1767 const TargetRegisterClass *OpRC =
1768 MRI.getRegClass(MI->getOperand(i).getReg());
1769 if (RI.hasVGPRs(OpRC)) {
1776 // If any of the operands are VGPR registers, then they all most be
1777 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1779 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1782 VRC = RI.getEquivalentVGPRClass(SRC);
1789 // Update all the operands so they have the same type.
1790 for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
1791 MachineOperand &Op = MI->getOperand(I);
1792 if (!Op.isReg() || !TargetRegisterInfo::isVirtualRegister(Op.getReg()))
1794 unsigned DstReg = MRI.createVirtualRegister(RC);
1796 // MI is a PHI instruction.
1797 MachineBasicBlock *InsertBB = MI->getOperand(I + 1).getMBB();
1798 MachineBasicBlock::iterator Insert = InsertBB->getFirstTerminator();
1800 BuildMI(*InsertBB, Insert, MI->getDebugLoc(), get(AMDGPU::COPY), DstReg)
1806 // REG_SEQUENCE doesn't really require operand legalization, but if one has a
1807 // VGPR dest type and SGPR sources, insert copies so all operands are
1808 // VGPRs. This seems to help operand folding / the register coalescer.
1809 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1810 MachineBasicBlock *MBB = MI->getParent();
1811 const TargetRegisterClass *DstRC = getOpRegClass(*MI, 0);
1812 if (RI.hasVGPRs(DstRC)) {
1813 // Update all the operands so they are VGPR register classes. These may
1814 // not be the same register class because REG_SEQUENCE supports mixing
1815 // subregister index types e.g. sub0_sub1 + sub2 + sub3
1816 for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
1817 MachineOperand &Op = MI->getOperand(I);
1818 if (!Op.isReg() || !TargetRegisterInfo::isVirtualRegister(Op.getReg()))
1821 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg());
1822 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC);
1826 unsigned DstReg = MRI.createVirtualRegister(VRC);
1828 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), DstReg)
1839 // Legalize INSERT_SUBREG
1840 // src0 must have the same register class as dst
1841 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
1842 unsigned Dst = MI->getOperand(0).getReg();
1843 unsigned Src0 = MI->getOperand(1).getReg();
1844 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1845 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1846 if (DstRC != Src0RC) {
1847 MachineBasicBlock &MBB = *MI->getParent();
1848 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
1849 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
1851 MI->getOperand(1).setReg(NewSrc0);
1856 // Legalize MUBUF* instructions
1857 // FIXME: If we start using the non-addr64 instructions for compute, we
1858 // may need to legalize them here.
1860 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc);
1861 if (SRsrcIdx != -1) {
1862 // We have an MUBUF instruction
1863 MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx);
1864 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass;
1865 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()),
1866 RI.getRegClass(SRsrcRC))) {
1867 // The operands are legal.
1868 // FIXME: We may need to legalize operands besided srsrc.
1872 MachineBasicBlock &MBB = *MI->getParent();
1874 // Extract the ptr from the resource descriptor.
1875 unsigned SRsrcPtr = buildExtractSubReg(MI, MRI, *SRsrc,
1876 &AMDGPU::VReg_128RegClass, AMDGPU::sub0_sub1, &AMDGPU::VReg_64RegClass);
1878 // Create an empty resource descriptor
1879 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1880 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1881 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1882 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1883 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
1886 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1890 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1891 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1893 .addImm(RsrcDataFormat & 0xFFFFFFFF);
1895 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1896 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1898 .addImm(RsrcDataFormat >> 32);
1900 // NewSRsrc = {Zero64, SRsrcFormat}
1901 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewSRsrc)
1903 .addImm(AMDGPU::sub0_sub1)
1904 .addReg(SRsrcFormatLo)
1905 .addImm(AMDGPU::sub2)
1906 .addReg(SRsrcFormatHi)
1907 .addImm(AMDGPU::sub3);
1909 MachineOperand *VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1910 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
1912 // This is already an ADDR64 instruction so we need to add the pointer
1913 // extracted from the resource descriptor to the current value of VAddr.
1914 unsigned NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1915 unsigned NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1917 // NewVaddrLo = SRsrcPtr:sub0 + VAddr:sub0
1918 DebugLoc DL = MI->getDebugLoc();
1919 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), NewVAddrLo)
1920 .addReg(SRsrcPtr, 0, AMDGPU::sub0)
1921 .addReg(VAddr->getReg(), 0, AMDGPU::sub0);
1923 // NewVaddrHi = SRsrcPtr:sub1 + VAddr:sub1
1924 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADDC_U32_e32), NewVAddrHi)
1925 .addReg(SRsrcPtr, 0, AMDGPU::sub1)
1926 .addReg(VAddr->getReg(), 0, AMDGPU::sub1);
1928 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1929 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
1931 .addImm(AMDGPU::sub0)
1933 .addImm(AMDGPU::sub1);
1935 // This instructions is the _OFFSET variant, so we need to convert it to
1937 MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata);
1938 MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset);
1939 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset);
1941 // Create the new instruction.
1942 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
1943 MachineInstr *Addr64 =
1944 BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
1946 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
1947 // This will be replaced later
1948 // with the new value of vaddr.
1950 .addOperand(*SOffset)
1951 .addOperand(*Offset)
1955 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1957 MI->removeFromParent();
1960 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1961 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
1962 .addReg(SRsrcPtr, 0, AMDGPU::sub0)
1963 .addImm(AMDGPU::sub0)
1964 .addReg(SRsrcPtr, 0, AMDGPU::sub1)
1965 .addImm(AMDGPU::sub1);
1967 VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1968 SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc);
1971 // Update the instruction to use NewVaddr
1972 VAddr->setReg(NewVAddr);
1973 // Update the instruction to use NewSRsrc
1974 SRsrc->setReg(NewSRsrc);
1978 void SIInstrInfo::splitSMRD(MachineInstr *MI,
1979 const TargetRegisterClass *HalfRC,
1980 unsigned HalfImmOp, unsigned HalfSGPROp,
1981 MachineInstr *&Lo, MachineInstr *&Hi) const {
1983 DebugLoc DL = MI->getDebugLoc();
1984 MachineBasicBlock *MBB = MI->getParent();
1985 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1986 unsigned RegLo = MRI.createVirtualRegister(HalfRC);
1987 unsigned RegHi = MRI.createVirtualRegister(HalfRC);
1988 unsigned HalfSize = HalfRC->getSize();
1989 const MachineOperand *OffOp =
1990 getNamedOperand(*MI, AMDGPU::OpName::offset);
1991 const MachineOperand *SBase = getNamedOperand(*MI, AMDGPU::OpName::sbase);
1993 // The SMRD has an 8-bit offset in dwords on SI and a 20-bit offset in bytes
1996 bool IsKill = SBase->isKill();
1999 MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() >=
2000 AMDGPUSubtarget::VOLCANIC_ISLANDS;
2001 unsigned OffScale = isVI ? 1 : 4;
2002 // Handle the _IMM variant
2003 unsigned LoOffset = OffOp->getImm() * OffScale;
2004 unsigned HiOffset = LoOffset + HalfSize;
2005 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo)
2006 // Use addReg instead of addOperand
2007 // to make sure kill flag is cleared.
2008 .addReg(SBase->getReg(), 0, SBase->getSubReg())
2009 .addImm(LoOffset / OffScale);
2011 if (!isUInt<20>(HiOffset) || (!isVI && !isUInt<8>(HiOffset / OffScale))) {
2012 unsigned OffsetSGPR =
2013 MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
2014 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR)
2015 .addImm(HiOffset); // The offset in register is in bytes.
2016 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
2017 .addReg(SBase->getReg(), getKillRegState(IsKill),
2019 .addReg(OffsetSGPR);
2021 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi)
2022 .addReg(SBase->getReg(), getKillRegState(IsKill),
2024 .addImm(HiOffset / OffScale);
2027 // Handle the _SGPR variant
2028 MachineOperand *SOff = getNamedOperand(*MI, AMDGPU::OpName::soff);
2029 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo)
2030 .addReg(SBase->getReg(), 0, SBase->getSubReg())
2032 unsigned OffsetSGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
2033 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR)
2036 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
2037 .addReg(SBase->getReg(), getKillRegState(IsKill),
2039 .addReg(OffsetSGPR);
2042 unsigned SubLo, SubHi;
2043 const TargetRegisterClass *NewDstRC;
2046 SubLo = AMDGPU::sub0;
2047 SubHi = AMDGPU::sub1;
2048 NewDstRC = &AMDGPU::VReg_64RegClass;
2051 SubLo = AMDGPU::sub0_sub1;
2052 SubHi = AMDGPU::sub2_sub3;
2053 NewDstRC = &AMDGPU::VReg_128RegClass;
2056 SubLo = AMDGPU::sub0_sub1_sub2_sub3;
2057 SubHi = AMDGPU::sub4_sub5_sub6_sub7;
2058 NewDstRC = &AMDGPU::VReg_256RegClass;
2061 SubLo = AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7;
2062 SubHi = AMDGPU::sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15;
2063 NewDstRC = &AMDGPU::VReg_512RegClass;
2066 llvm_unreachable("Unhandled HalfSize");
2069 unsigned OldDst = MI->getOperand(0).getReg();
2070 unsigned NewDst = MRI.createVirtualRegister(NewDstRC);
2072 MRI.replaceRegWith(OldDst, NewDst);
2074 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), NewDst)
2081 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI,
2082 MachineRegisterInfo &MRI,
2083 SmallVectorImpl<MachineInstr *> &Worklist) const {
2084 MachineBasicBlock *MBB = MI->getParent();
2085 int DstIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
2086 assert(DstIdx != -1);
2087 unsigned DstRCID = get(MI->getOpcode()).OpInfo[DstIdx].RegClass;
2088 switch(RI.getRegClass(DstRCID)->getSize()) {
2092 unsigned NewOpcode = getVALUOp(*MI);
2096 if (MI->getOperand(2).isReg()) {
2097 RegOffset = MI->getOperand(2).getReg();
2100 assert(MI->getOperand(2).isImm());
2101 // SMRD instructions take a dword offsets on SI and byte offset on VI
2102 // and MUBUF instructions always take a byte offset.
2103 ImmOffset = MI->getOperand(2).getImm();
2104 if (MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() <=
2105 AMDGPUSubtarget::SEA_ISLANDS)
2107 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2109 if (isUInt<12>(ImmOffset)) {
2110 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2114 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2121 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
2122 unsigned DWord0 = RegOffset;
2123 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2124 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2125 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2126 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
2128 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
2130 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
2131 .addImm(RsrcDataFormat & 0xFFFFFFFF);
2132 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
2133 .addImm(RsrcDataFormat >> 32);
2134 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
2136 .addImm(AMDGPU::sub0)
2138 .addImm(AMDGPU::sub1)
2140 .addImm(AMDGPU::sub2)
2142 .addImm(AMDGPU::sub3);
2144 const MCInstrDesc &NewInstDesc = get(NewOpcode);
2145 const TargetRegisterClass *NewDstRC
2146 = RI.getRegClass(NewInstDesc.OpInfo[0].RegClass);
2147 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2148 unsigned DstReg = MI->getOperand(0).getReg();
2149 MRI.replaceRegWith(DstReg, NewDstReg);
2151 MachineInstr *NewInst =
2152 BuildMI(*MBB, MI, MI->getDebugLoc(), NewInstDesc, NewDstReg)
2153 .addOperand(MI->getOperand(1)) // sbase
2160 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
2161 MI->eraseFromParent();
2163 legalizeOperands(NewInst);
2164 addUsersToMoveToVALUWorklist(NewDstReg, MRI, Worklist);
2168 MachineInstr *Lo, *Hi;
2169 splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
2170 AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
2171 MI->eraseFromParent();
2172 moveSMRDToVALU(Lo, MRI, Worklist);
2173 moveSMRDToVALU(Hi, MRI, Worklist);
2178 MachineInstr *Lo, *Hi;
2179 splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
2180 AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
2181 MI->eraseFromParent();
2182 moveSMRDToVALU(Lo, MRI, Worklist);
2183 moveSMRDToVALU(Hi, MRI, Worklist);
2189 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
2190 SmallVector<MachineInstr *, 128> Worklist;
2191 Worklist.push_back(&TopInst);
2193 while (!Worklist.empty()) {
2194 MachineInstr *Inst = Worklist.pop_back_val();
2195 MachineBasicBlock *MBB = Inst->getParent();
2196 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2198 unsigned Opcode = Inst->getOpcode();
2199 unsigned NewOpcode = getVALUOp(*Inst);
2201 // Handle some special cases
2204 if (isSMRD(Inst->getOpcode())) {
2205 moveSMRDToVALU(Inst, MRI, Worklist);
2209 case AMDGPU::S_AND_B64:
2210 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_AND_B32_e64);
2211 Inst->eraseFromParent();
2214 case AMDGPU::S_OR_B64:
2215 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_OR_B32_e64);
2216 Inst->eraseFromParent();
2219 case AMDGPU::S_XOR_B64:
2220 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_XOR_B32_e64);
2221 Inst->eraseFromParent();
2224 case AMDGPU::S_NOT_B64:
2225 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::V_NOT_B32_e32);
2226 Inst->eraseFromParent();
2229 case AMDGPU::S_BCNT1_I32_B64:
2230 splitScalar64BitBCNT(Worklist, Inst);
2231 Inst->eraseFromParent();
2234 case AMDGPU::S_BFE_I64: {
2235 splitScalar64BitBFE(Worklist, Inst);
2236 Inst->eraseFromParent();
2240 case AMDGPU::S_LSHL_B32:
2241 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2242 NewOpcode = AMDGPU::V_LSHLREV_B32_e64;
2246 case AMDGPU::S_ASHR_I32:
2247 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2248 NewOpcode = AMDGPU::V_ASHRREV_I32_e64;
2252 case AMDGPU::S_LSHR_B32:
2253 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2254 NewOpcode = AMDGPU::V_LSHRREV_B32_e64;
2258 case AMDGPU::S_LSHL_B64:
2259 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2260 NewOpcode = AMDGPU::V_LSHLREV_B64;
2264 case AMDGPU::S_ASHR_I64:
2265 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2266 NewOpcode = AMDGPU::V_ASHRREV_I64;
2270 case AMDGPU::S_LSHR_B64:
2271 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2272 NewOpcode = AMDGPU::V_LSHRREV_B64;
2277 case AMDGPU::S_BFE_U64:
2278 case AMDGPU::S_BFM_B64:
2279 llvm_unreachable("Moving this op to VALU not implemented");
2282 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
2283 // We cannot move this instruction to the VALU, so we should try to
2284 // legalize its operands instead.
2285 legalizeOperands(Inst);
2289 // Use the new VALU Opcode.
2290 const MCInstrDesc &NewDesc = get(NewOpcode);
2291 Inst->setDesc(NewDesc);
2293 // Remove any references to SCC. Vector instructions can't read from it, and
2294 // We're just about to add the implicit use / defs of VCC, and we don't want
2296 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
2297 MachineOperand &Op = Inst->getOperand(i);
2298 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
2299 Inst->RemoveOperand(i);
2302 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
2303 // We are converting these to a BFE, so we need to add the missing
2304 // operands for the size and offset.
2305 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
2306 Inst->addOperand(MachineOperand::CreateImm(0));
2307 Inst->addOperand(MachineOperand::CreateImm(Size));
2309 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
2310 // The VALU version adds the second operand to the result, so insert an
2312 Inst->addOperand(MachineOperand::CreateImm(0));
2315 Inst->addImplicitDefUseOperands(*Inst->getParent()->getParent());
2317 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
2318 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
2319 // If we need to move this to VGPRs, we need to unpack the second operand
2320 // back into the 2 separate ones for bit offset and width.
2321 assert(OffsetWidthOp.isImm() &&
2322 "Scalar BFE is only implemented for constant width and offset");
2323 uint32_t Imm = OffsetWidthOp.getImm();
2325 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2326 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2327 Inst->RemoveOperand(2); // Remove old immediate.
2328 Inst->addOperand(MachineOperand::CreateImm(Offset));
2329 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
2332 // Update the destination register class.
2334 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
2337 // For target instructions, getOpRegClass just returns the virtual
2338 // register class associated with the operand, so we need to find an
2339 // equivalent VGPR register class in order to move the instruction to the
2343 case AMDGPU::REG_SEQUENCE:
2344 case AMDGPU::INSERT_SUBREG:
2345 if (RI.hasVGPRs(NewDstRC))
2347 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
2355 unsigned DstReg = Inst->getOperand(0).getReg();
2356 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2357 MRI.replaceRegWith(DstReg, NewDstReg);
2359 // Legalize the operands
2360 legalizeOperands(Inst);
2362 addUsersToMoveToVALUWorklist(NewDstReg, MRI, Worklist);
2366 //===----------------------------------------------------------------------===//
2367 // Indirect addressing callbacks
2368 //===----------------------------------------------------------------------===//
2370 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
2371 unsigned Channel) const {
2372 assert(Channel == 0);
2376 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
2377 return &AMDGPU::VGPR_32RegClass;
2380 void SIInstrInfo::splitScalar64BitUnaryOp(
2381 SmallVectorImpl<MachineInstr *> &Worklist,
2383 unsigned Opcode) const {
2384 MachineBasicBlock &MBB = *Inst->getParent();
2385 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2387 MachineOperand &Dest = Inst->getOperand(0);
2388 MachineOperand &Src0 = Inst->getOperand(1);
2389 DebugLoc DL = Inst->getDebugLoc();
2391 MachineBasicBlock::iterator MII = Inst;
2393 const MCInstrDesc &InstDesc = get(Opcode);
2394 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2395 MRI.getRegClass(Src0.getReg()) :
2396 &AMDGPU::SGPR_32RegClass;
2398 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2400 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2401 AMDGPU::sub0, Src0SubRC);
2403 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2404 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
2405 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
2407 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
2408 BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2409 .addOperand(SrcReg0Sub0);
2411 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2412 AMDGPU::sub1, Src0SubRC);
2414 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
2415 BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2416 .addOperand(SrcReg0Sub1);
2418 unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC);
2419 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2421 .addImm(AMDGPU::sub0)
2423 .addImm(AMDGPU::sub1);
2425 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2427 // We don't need to legalizeOperands here because for a single operand, src0
2428 // will support any kind of input.
2430 // Move all users of this moved value.
2431 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
2434 void SIInstrInfo::splitScalar64BitBinaryOp(
2435 SmallVectorImpl<MachineInstr *> &Worklist,
2437 unsigned Opcode) const {
2438 MachineBasicBlock &MBB = *Inst->getParent();
2439 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2441 MachineOperand &Dest = Inst->getOperand(0);
2442 MachineOperand &Src0 = Inst->getOperand(1);
2443 MachineOperand &Src1 = Inst->getOperand(2);
2444 DebugLoc DL = Inst->getDebugLoc();
2446 MachineBasicBlock::iterator MII = Inst;
2448 const MCInstrDesc &InstDesc = get(Opcode);
2449 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2450 MRI.getRegClass(Src0.getReg()) :
2451 &AMDGPU::SGPR_32RegClass;
2453 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2454 const TargetRegisterClass *Src1RC = Src1.isReg() ?
2455 MRI.getRegClass(Src1.getReg()) :
2456 &AMDGPU::SGPR_32RegClass;
2458 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
2460 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2461 AMDGPU::sub0, Src0SubRC);
2462 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2463 AMDGPU::sub0, Src1SubRC);
2465 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2466 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
2467 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
2469 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
2470 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2471 .addOperand(SrcReg0Sub0)
2472 .addOperand(SrcReg1Sub0);
2474 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2475 AMDGPU::sub1, Src0SubRC);
2476 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2477 AMDGPU::sub1, Src1SubRC);
2479 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
2480 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2481 .addOperand(SrcReg0Sub1)
2482 .addOperand(SrcReg1Sub1);
2484 unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC);
2485 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2487 .addImm(AMDGPU::sub0)
2489 .addImm(AMDGPU::sub1);
2491 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2493 // Try to legalize the operands in case we need to swap the order to keep it
2495 legalizeOperands(LoHalf);
2496 legalizeOperands(HiHalf);
2498 // Move all users of this moved vlaue.
2499 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
2502 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
2503 MachineInstr *Inst) const {
2504 MachineBasicBlock &MBB = *Inst->getParent();
2505 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2507 MachineBasicBlock::iterator MII = Inst;
2508 DebugLoc DL = Inst->getDebugLoc();
2510 MachineOperand &Dest = Inst->getOperand(0);
2511 MachineOperand &Src = Inst->getOperand(1);
2513 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
2514 const TargetRegisterClass *SrcRC = Src.isReg() ?
2515 MRI.getRegClass(Src.getReg()) :
2516 &AMDGPU::SGPR_32RegClass;
2518 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2519 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2521 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
2523 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2524 AMDGPU::sub0, SrcSubRC);
2525 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2526 AMDGPU::sub1, SrcSubRC);
2528 BuildMI(MBB, MII, DL, InstDesc, MidReg)
2529 .addOperand(SrcRegSub0)
2532 BuildMI(MBB, MII, DL, InstDesc, ResultReg)
2533 .addOperand(SrcRegSub1)
2536 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2538 // We don't need to legalize operands here. src0 for etiher instruction can be
2539 // an SGPR, and the second input is unused or determined here.
2540 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2543 void SIInstrInfo::splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
2544 MachineInstr *Inst) const {
2545 MachineBasicBlock &MBB = *Inst->getParent();
2546 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2547 MachineBasicBlock::iterator MII = Inst;
2548 DebugLoc DL = Inst->getDebugLoc();
2550 MachineOperand &Dest = Inst->getOperand(0);
2551 uint32_t Imm = Inst->getOperand(2).getImm();
2552 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2553 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2557 // Only sext_inreg cases handled.
2558 assert(Inst->getOpcode() == AMDGPU::S_BFE_I64 &&
2563 if (BitWidth < 32) {
2564 unsigned MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2565 unsigned MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2566 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2568 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo)
2569 .addReg(Inst->getOperand(1).getReg(), 0, AMDGPU::sub0)
2573 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi)
2577 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2579 .addImm(AMDGPU::sub0)
2581 .addImm(AMDGPU::sub1);
2583 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2584 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2588 MachineOperand &Src = Inst->getOperand(1);
2589 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2590 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2592 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
2594 .addReg(Src.getReg(), 0, AMDGPU::sub0);
2596 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2597 .addReg(Src.getReg(), 0, AMDGPU::sub0)
2598 .addImm(AMDGPU::sub0)
2600 .addImm(AMDGPU::sub1);
2602 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2603 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2606 void SIInstrInfo::addUsersToMoveToVALUWorklist(
2608 MachineRegisterInfo &MRI,
2609 SmallVectorImpl<MachineInstr *> &Worklist) const {
2610 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(DstReg),
2611 E = MRI.use_end(); I != E; ++I) {
2612 MachineInstr &UseMI = *I->getParent();
2613 if (!canReadVGPR(UseMI, I.getOperandNo())) {
2614 Worklist.push_back(&UseMI);
2619 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
2620 int OpIndices[3]) const {
2621 const MCInstrDesc &Desc = get(MI->getOpcode());
2623 // Find the one SGPR operand we are allowed to use.
2624 unsigned SGPRReg = AMDGPU::NoRegister;
2626 // First we need to consider the instruction's operand requirements before
2627 // legalizing. Some operands are required to be SGPRs, such as implicit uses
2628 // of VCC, but we are still bound by the constant bus requirement to only use
2631 // If the operand's class is an SGPR, we can never move it.
2633 for (const MachineOperand &MO : MI->implicit_operands()) {
2634 // We only care about reads.
2638 if (MO.getReg() == AMDGPU::VCC)
2641 if (MO.getReg() == AMDGPU::FLAT_SCR)
2642 return AMDGPU::FLAT_SCR;
2645 unsigned UsedSGPRs[3] = { AMDGPU::NoRegister };
2646 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
2648 for (unsigned i = 0; i < 3; ++i) {
2649 int Idx = OpIndices[i];
2653 const MachineOperand &MO = MI->getOperand(Idx);
2654 if (RI.isSGPRClassID(Desc.OpInfo[Idx].RegClass))
2655 SGPRReg = MO.getReg();
2657 if (MO.isReg() && RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
2658 UsedSGPRs[i] = MO.getReg();
2661 if (SGPRReg != AMDGPU::NoRegister)
2664 // We don't have a required SGPR operand, so we have a bit more freedom in
2665 // selecting operands to move.
2667 // Try to select the most used SGPR. If an SGPR is equal to one of the
2668 // others, we choose that.
2671 // V_FMA_F32 v0, s0, s0, s0 -> No moves
2672 // V_FMA_F32 v0, s0, s1, s0 -> Move s1
2674 if (UsedSGPRs[0] != AMDGPU::NoRegister) {
2675 if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2])
2676 SGPRReg = UsedSGPRs[0];
2679 if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) {
2680 if (UsedSGPRs[1] == UsedSGPRs[2])
2681 SGPRReg = UsedSGPRs[1];
2687 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
2688 MachineBasicBlock *MBB,
2689 MachineBasicBlock::iterator I,
2691 unsigned Address, unsigned OffsetReg) const {
2692 const DebugLoc &DL = MBB->findDebugLoc(I);
2693 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2694 getIndirectIndexBegin(*MBB->getParent()));
2696 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
2697 .addReg(IndirectBaseReg, RegState::Define)
2698 .addOperand(I->getOperand(0))
2699 .addReg(IndirectBaseReg)
2705 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
2706 MachineBasicBlock *MBB,
2707 MachineBasicBlock::iterator I,
2709 unsigned Address, unsigned OffsetReg) const {
2710 const DebugLoc &DL = MBB->findDebugLoc(I);
2711 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2712 getIndirectIndexBegin(*MBB->getParent()));
2714 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
2715 .addOperand(I->getOperand(0))
2716 .addOperand(I->getOperand(1))
2717 .addReg(IndirectBaseReg)
2723 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
2724 const MachineFunction &MF) const {
2725 int End = getIndirectIndexEnd(MF);
2726 int Begin = getIndirectIndexBegin(MF);
2732 for (int Index = Begin; Index <= End; ++Index)
2733 Reserved.set(AMDGPU::VGPR_32RegClass.getRegister(Index));
2735 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
2736 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
2738 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
2739 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
2741 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
2742 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
2744 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
2745 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
2747 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
2748 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
2751 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
2752 unsigned OperandName) const {
2753 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
2757 return &MI.getOperand(Idx);
2760 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {
2761 uint64_t RsrcDataFormat = AMDGPU::RSRC_DATA_FORMAT;
2762 if (ST.isAmdHsaOS()) {
2763 RsrcDataFormat |= (1ULL << 56);
2765 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2767 RsrcDataFormat |= (2ULL << 59);
2770 return RsrcDataFormat;