1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/Support/Debug.h"
30 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
31 : AMDGPUInstrInfo(st), RI() {}
33 //===----------------------------------------------------------------------===//
34 // TargetInstrInfo callbacks
35 //===----------------------------------------------------------------------===//
37 static unsigned getNumOperandsNoGlue(SDNode *Node) {
38 unsigned N = Node->getNumOperands();
39 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
44 static SDValue findChainOperand(SDNode *Load) {
45 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1);
46 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
50 /// \brief Returns true if both nodes have the same value for the given
51 /// operand \p Op, or if both nodes do not have this operand.
52 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
53 unsigned Opc0 = N0->getMachineOpcode();
54 unsigned Opc1 = N1->getMachineOpcode();
56 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
57 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
59 if (Op0Idx == -1 && Op1Idx == -1)
63 if ((Op0Idx == -1 && Op1Idx != -1) ||
64 (Op1Idx == -1 && Op0Idx != -1))
67 // getNamedOperandIdx returns the index for the MachineInstr's operands,
68 // which includes the result as the first operand. We are indexing into the
69 // MachineSDNode's operands, so we need to skip the result operand to get
74 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
77 bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
78 AliasAnalysis *AA) const {
79 // TODO: The generic check fails for VALU instructions that should be
80 // rematerializable due to implicit reads of exec. We really want all of the
81 // generic logic for this except for this.
82 switch (MI->getOpcode()) {
83 case AMDGPU::V_MOV_B32_e32:
84 case AMDGPU::V_MOV_B32_e64:
91 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
93 int64_t &Offset1) const {
94 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
97 unsigned Opc0 = Load0->getMachineOpcode();
98 unsigned Opc1 = Load1->getMachineOpcode();
100 // Make sure both are actually loads.
101 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
104 if (isDS(Opc0) && isDS(Opc1)) {
106 // FIXME: Handle this case:
107 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
111 if (Load0->getOperand(1) != Load1->getOperand(1))
115 if (findChainOperand(Load0) != findChainOperand(Load1))
118 // Skip read2 / write2 variants for simplicity.
119 // TODO: We should report true if the used offsets are adjacent (excluded
121 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
122 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
125 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
126 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
130 if (isSMRD(Opc0) && isSMRD(Opc1)) {
131 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
134 if (Load0->getOperand(0) != Load1->getOperand(0))
137 const ConstantSDNode *Load0Offset =
138 dyn_cast<ConstantSDNode>(Load0->getOperand(1));
139 const ConstantSDNode *Load1Offset =
140 dyn_cast<ConstantSDNode>(Load1->getOperand(1));
142 if (!Load0Offset || !Load1Offset)
146 if (findChainOperand(Load0) != findChainOperand(Load1))
149 Offset0 = Load0Offset->getZExtValue();
150 Offset1 = Load1Offset->getZExtValue();
154 // MUBUF and MTBUF can access the same addresses.
155 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
157 // MUBUF and MTBUF have vaddr at different indices.
158 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
159 findChainOperand(Load0) != findChainOperand(Load1) ||
160 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
161 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
164 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
165 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
167 if (OffIdx0 == -1 || OffIdx1 == -1)
170 // getNamedOperandIdx returns the index for MachineInstrs. Since they
171 // inlcude the output in the operand list, but SDNodes don't, we need to
172 // subtract the index by one.
176 SDValue Off0 = Load0->getOperand(OffIdx0);
177 SDValue Off1 = Load1->getOperand(OffIdx1);
179 // The offset might be a FrameIndexSDNode.
180 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
183 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
184 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
191 static bool isStride64(unsigned Opc) {
193 case AMDGPU::DS_READ2ST64_B32:
194 case AMDGPU::DS_READ2ST64_B64:
195 case AMDGPU::DS_WRITE2ST64_B32:
196 case AMDGPU::DS_WRITE2ST64_B64:
203 bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
205 const TargetRegisterInfo *TRI) const {
206 unsigned Opc = LdSt->getOpcode();
208 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
209 AMDGPU::OpName::offset);
211 // Normal, single offset LDS instruction.
212 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
213 AMDGPU::OpName::addr);
215 BaseReg = AddrReg->getReg();
216 Offset = OffsetImm->getImm();
220 // The 2 offset instructions use offset0 and offset1 instead. We can treat
221 // these as a load with a single offset if the 2 offsets are consecutive. We
222 // will use this for some partially aligned loads.
223 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
224 AMDGPU::OpName::offset0);
225 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
226 AMDGPU::OpName::offset1);
228 uint8_t Offset0 = Offset0Imm->getImm();
229 uint8_t Offset1 = Offset1Imm->getImm();
231 if (Offset1 > Offset0 && Offset1 - Offset0 == 1) {
232 // Each of these offsets is in element sized units, so we need to convert
233 // to bytes of the individual reads.
237 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
239 assert(LdSt->mayStore());
240 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
241 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
247 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
248 AMDGPU::OpName::addr);
249 BaseReg = AddrReg->getReg();
250 Offset = EltSize * Offset0;
257 if (isMUBUF(Opc) || isMTBUF(Opc)) {
258 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
261 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
262 AMDGPU::OpName::vaddr);
266 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
267 AMDGPU::OpName::offset);
268 BaseReg = AddrReg->getReg();
269 Offset = OffsetImm->getImm();
274 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
275 AMDGPU::OpName::offset);
279 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
280 AMDGPU::OpName::sbase);
281 BaseReg = SBaseReg->getReg();
282 Offset = OffsetImm->getImm();
289 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
290 MachineInstr *SecondLdSt,
291 unsigned NumLoads) const {
292 unsigned Opc0 = FirstLdSt->getOpcode();
293 unsigned Opc1 = SecondLdSt->getOpcode();
295 // TODO: This needs finer tuning
299 if (isDS(Opc0) && isDS(Opc1))
302 if (isSMRD(Opc0) && isSMRD(Opc1))
305 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1)))
312 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
313 MachineBasicBlock::iterator MI, DebugLoc DL,
314 unsigned DestReg, unsigned SrcReg,
315 bool KillSrc) const {
317 // If we are trying to copy to or from SCC, there is a bug somewhere else in
318 // the backend. While it may be theoretically possible to do this, it should
319 // never be necessary.
320 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
322 static const int16_t Sub0_15[] = {
323 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
324 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
325 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
326 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
329 static const int16_t Sub0_7[] = {
330 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
331 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
334 static const int16_t Sub0_3[] = {
335 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
338 static const int16_t Sub0_2[] = {
339 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
342 static const int16_t Sub0_1[] = {
343 AMDGPU::sub0, AMDGPU::sub1, 0
347 const int16_t *SubIndices;
349 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
350 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
351 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
352 .addReg(SrcReg, getKillRegState(KillSrc));
355 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
356 if (DestReg == AMDGPU::VCC) {
357 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
358 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
359 .addReg(SrcReg, getKillRegState(KillSrc));
361 // FIXME: Hack until VReg_1 removed.
362 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
363 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32), AMDGPU::VCC)
365 .addReg(SrcReg, getKillRegState(KillSrc));
371 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
372 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
373 .addReg(SrcReg, getKillRegState(KillSrc));
376 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
377 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
378 Opcode = AMDGPU::S_MOV_B32;
381 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
382 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
383 Opcode = AMDGPU::S_MOV_B32;
386 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
387 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
388 Opcode = AMDGPU::S_MOV_B32;
389 SubIndices = Sub0_15;
391 } else if (AMDGPU::VGPR_32RegClass.contains(DestReg)) {
392 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
393 AMDGPU::SReg_32RegClass.contains(SrcReg));
394 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
395 .addReg(SrcReg, getKillRegState(KillSrc));
398 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
399 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
400 AMDGPU::SReg_64RegClass.contains(SrcReg));
401 Opcode = AMDGPU::V_MOV_B32_e32;
404 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
405 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
406 Opcode = AMDGPU::V_MOV_B32_e32;
409 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
410 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
411 AMDGPU::SReg_128RegClass.contains(SrcReg));
412 Opcode = AMDGPU::V_MOV_B32_e32;
415 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
416 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
417 AMDGPU::SReg_256RegClass.contains(SrcReg));
418 Opcode = AMDGPU::V_MOV_B32_e32;
421 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
422 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
423 AMDGPU::SReg_512RegClass.contains(SrcReg));
424 Opcode = AMDGPU::V_MOV_B32_e32;
425 SubIndices = Sub0_15;
428 llvm_unreachable("Can't copy register!");
431 while (unsigned SubIdx = *SubIndices++) {
432 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
433 get(Opcode), RI.getSubReg(DestReg, SubIdx));
435 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
438 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
442 int SIInstrInfo::commuteOpcode(const MachineInstr &MI) const {
443 const unsigned Opcode = MI.getOpcode();
447 // Try to map original to commuted opcode
448 NewOpc = AMDGPU::getCommuteRev(Opcode);
450 // Check if the commuted (REV) opcode exists on the target.
451 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
453 // Try to map commuted to original opcode
454 NewOpc = AMDGPU::getCommuteOrig(Opcode);
456 // Check if the original (non-REV) opcode exists on the target.
457 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
462 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
464 if (DstRC->getSize() == 4) {
465 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
466 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) {
467 return AMDGPU::S_MOV_B64;
468 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) {
469 return AMDGPU::V_MOV_B64_PSEUDO;
474 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
475 MachineBasicBlock::iterator MI,
476 unsigned SrcReg, bool isKill,
478 const TargetRegisterClass *RC,
479 const TargetRegisterInfo *TRI) const {
480 MachineFunction *MF = MBB.getParent();
481 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
482 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
483 DebugLoc DL = MBB.findDebugLoc(MI);
486 if (RI.isSGPRClass(RC)) {
487 // We are only allowed to create one new instruction when spilling
488 // registers, so we need to use pseudo instruction for spilling
490 switch (RC->getSize() * 8) {
491 case 32: Opcode = AMDGPU::SI_SPILL_S32_SAVE; break;
492 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
493 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
494 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
495 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
497 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
498 MFI->setHasSpilledVGPRs();
500 switch(RC->getSize() * 8) {
501 case 32: Opcode = AMDGPU::SI_SPILL_V32_SAVE; break;
502 case 64: Opcode = AMDGPU::SI_SPILL_V64_SAVE; break;
503 case 96: Opcode = AMDGPU::SI_SPILL_V96_SAVE; break;
504 case 128: Opcode = AMDGPU::SI_SPILL_V128_SAVE; break;
505 case 256: Opcode = AMDGPU::SI_SPILL_V256_SAVE; break;
506 case 512: Opcode = AMDGPU::SI_SPILL_V512_SAVE; break;
511 FrameInfo->setObjectAlignment(FrameIndex, 4);
512 BuildMI(MBB, MI, DL, get(Opcode))
514 .addFrameIndex(FrameIndex)
515 // Place-holder registers, these will be filled in by
516 // SIPrepareScratchRegs.
517 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
518 .addReg(AMDGPU::SGPR0, RegState::Undef);
520 LLVMContext &Ctx = MF->getFunction()->getContext();
521 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
523 BuildMI(MBB, MI, DL, get(AMDGPU::KILL))
528 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
529 MachineBasicBlock::iterator MI,
530 unsigned DestReg, int FrameIndex,
531 const TargetRegisterClass *RC,
532 const TargetRegisterInfo *TRI) const {
533 MachineFunction *MF = MBB.getParent();
534 const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
535 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
536 DebugLoc DL = MBB.findDebugLoc(MI);
539 if (RI.isSGPRClass(RC)){
540 switch(RC->getSize() * 8) {
541 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
542 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
543 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
544 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
545 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
547 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
548 switch(RC->getSize() * 8) {
549 case 32: Opcode = AMDGPU::SI_SPILL_V32_RESTORE; break;
550 case 64: Opcode = AMDGPU::SI_SPILL_V64_RESTORE; break;
551 case 96: Opcode = AMDGPU::SI_SPILL_V96_RESTORE; break;
552 case 128: Opcode = AMDGPU::SI_SPILL_V128_RESTORE; break;
553 case 256: Opcode = AMDGPU::SI_SPILL_V256_RESTORE; break;
554 case 512: Opcode = AMDGPU::SI_SPILL_V512_RESTORE; break;
559 FrameInfo->setObjectAlignment(FrameIndex, 4);
560 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
561 .addFrameIndex(FrameIndex)
562 // Place-holder registers, these will be filled in by
563 // SIPrepareScratchRegs.
564 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
565 .addReg(AMDGPU::SGPR0, RegState::Undef);
568 LLVMContext &Ctx = MF->getFunction()->getContext();
569 Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"
570 " restore register");
571 BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg);
575 /// \param @Offset Offset in bytes of the FrameIndex being spilled
576 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
577 MachineBasicBlock::iterator MI,
578 RegScavenger *RS, unsigned TmpReg,
579 unsigned FrameOffset,
580 unsigned Size) const {
581 MachineFunction *MF = MBB.getParent();
582 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
583 const AMDGPUSubtarget &ST = MF->getSubtarget<AMDGPUSubtarget>();
584 const SIRegisterInfo *TRI =
585 static_cast<const SIRegisterInfo*>(ST.getRegisterInfo());
586 DebugLoc DL = MBB.findDebugLoc(MI);
587 unsigned WorkGroupSize = MFI->getMaximumWorkGroupSize(*MF);
588 unsigned WavefrontSize = ST.getWavefrontSize();
590 unsigned TIDReg = MFI->getTIDReg();
591 if (!MFI->hasCalculatedTID()) {
592 MachineBasicBlock &Entry = MBB.getParent()->front();
593 MachineBasicBlock::iterator Insert = Entry.front();
594 DebugLoc DL = Insert->getDebugLoc();
596 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);
597 if (TIDReg == AMDGPU::NoRegister)
601 if (MFI->getShaderType() == ShaderType::COMPUTE &&
602 WorkGroupSize > WavefrontSize) {
604 unsigned TIDIGXReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_X);
605 unsigned TIDIGYReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Y);
606 unsigned TIDIGZReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Z);
607 unsigned InputPtrReg =
608 TRI->getPreloadedValue(*MF, SIRegisterInfo::INPUT_PTR);
609 for (unsigned Reg : {TIDIGXReg, TIDIGYReg, TIDIGZReg}) {
610 if (!Entry.isLiveIn(Reg))
611 Entry.addLiveIn(Reg);
614 RS->enterBasicBlock(&Entry);
615 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
616 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
617 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
619 .addImm(SI::KernelInputOffsets::NGROUPS_Z);
620 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
622 .addImm(SI::KernelInputOffsets::NGROUPS_Y);
624 // NGROUPS.X * NGROUPS.Y
625 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
628 // (NGROUPS.X * NGROUPS.Y) * TIDIG.X
629 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
632 // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)
633 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
637 // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z
638 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg)
643 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
648 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64),
654 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
658 MFI->setTIDReg(TIDReg);
661 // Add FrameIndex to LDS offset
662 unsigned LDSOffset = MFI->LDSSize + (FrameOffset * WorkGroupSize);
663 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg)
670 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
679 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
684 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
685 MachineBasicBlock &MBB = *MI->getParent();
686 DebugLoc DL = MBB.findDebugLoc(MI);
687 switch (MI->getOpcode()) {
688 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
690 case AMDGPU::SI_CONSTDATA_PTR: {
691 unsigned Reg = MI->getOperand(0).getReg();
692 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
693 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
695 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg);
697 // Add 32-bit offset from this instruction to the start of the constant data.
698 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_U32), RegLo)
700 .addTargetIndex(AMDGPU::TI_CONSTDATA_START)
701 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit);
702 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi)
705 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit)
706 .addReg(AMDGPU::SCC, RegState::Implicit);
707 MI->eraseFromParent();
710 case AMDGPU::SGPR_USE:
711 // This is just a placeholder for register allocation.
712 MI->eraseFromParent();
715 case AMDGPU::V_MOV_B64_PSEUDO: {
716 unsigned Dst = MI->getOperand(0).getReg();
717 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
718 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
720 const MachineOperand &SrcOp = MI->getOperand(1);
721 // FIXME: Will this work for 64-bit floating point immediates?
722 assert(!SrcOp.isFPImm());
724 APInt Imm(64, SrcOp.getImm());
725 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
726 .addImm(Imm.getLoBits(32).getZExtValue())
727 .addReg(Dst, RegState::Implicit);
728 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
729 .addImm(Imm.getHiBits(32).getZExtValue())
730 .addReg(Dst, RegState::Implicit);
732 assert(SrcOp.isReg());
733 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
734 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
735 .addReg(Dst, RegState::Implicit);
736 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
737 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
738 .addReg(Dst, RegState::Implicit);
740 MI->eraseFromParent();
744 case AMDGPU::V_CNDMASK_B64_PSEUDO: {
745 unsigned Dst = MI->getOperand(0).getReg();
746 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
747 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
748 unsigned Src0 = MI->getOperand(1).getReg();
749 unsigned Src1 = MI->getOperand(2).getReg();
750 const MachineOperand &SrcCond = MI->getOperand(3);
752 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
753 .addReg(RI.getSubReg(Src0, AMDGPU::sub0))
754 .addReg(RI.getSubReg(Src1, AMDGPU::sub0))
755 .addOperand(SrcCond);
756 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
757 .addReg(RI.getSubReg(Src0, AMDGPU::sub1))
758 .addReg(RI.getSubReg(Src1, AMDGPU::sub1))
759 .addOperand(SrcCond);
760 MI->eraseFromParent();
767 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
770 if (MI->getNumOperands() < 3)
773 int CommutedOpcode = commuteOpcode(*MI);
774 if (CommutedOpcode == -1)
777 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
778 AMDGPU::OpName::src0);
779 assert(Src0Idx != -1 && "Should always have src0 operand");
781 MachineOperand &Src0 = MI->getOperand(Src0Idx);
785 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
786 AMDGPU::OpName::src1);
790 MachineOperand &Src1 = MI->getOperand(Src1Idx);
792 // Make sure it's legal to commute operands for VOP2.
793 if (isVOP2(MI->getOpcode()) &&
794 (!isOperandLegal(MI, Src0Idx, &Src1) ||
795 !isOperandLegal(MI, Src1Idx, &Src0))) {
800 // Allow commuting instructions with Imm operands.
801 if (NewMI || !Src1.isImm() ||
802 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
806 // Be sure to copy the source modifiers to the right place.
807 if (MachineOperand *Src0Mods
808 = getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) {
809 MachineOperand *Src1Mods
810 = getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers);
812 int Src0ModsVal = Src0Mods->getImm();
813 if (!Src1Mods && Src0ModsVal != 0)
816 // XXX - This assert might be a lie. It might be useful to have a neg
817 // modifier with 0.0.
818 int Src1ModsVal = Src1Mods->getImm();
819 assert((Src1ModsVal == 0) && "Not expecting modifiers with immediates");
821 Src1Mods->setImm(Src0ModsVal);
822 Src0Mods->setImm(Src1ModsVal);
825 unsigned Reg = Src0.getReg();
826 unsigned SubReg = Src0.getSubReg();
828 Src0.ChangeToImmediate(Src1.getImm());
830 llvm_unreachable("Should only have immediates");
832 Src1.ChangeToRegister(Reg, false);
833 Src1.setSubReg(SubReg);
835 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
839 MI->setDesc(get(CommutedOpcode));
844 // This needs to be implemented because the source modifiers may be inserted
845 // between the true commutable operands, and the base
846 // TargetInstrInfo::commuteInstruction uses it.
847 bool SIInstrInfo::findCommutedOpIndices(MachineInstr *MI,
849 unsigned &SrcOpIdx2) const {
850 const MCInstrDesc &MCID = MI->getDesc();
851 if (!MCID.isCommutable())
854 unsigned Opc = MI->getOpcode();
855 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
859 // FIXME: Workaround TargetInstrInfo::commuteInstruction asserting on
861 if (!MI->getOperand(Src0Idx).isReg())
864 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
868 if (!MI->getOperand(Src1Idx).isReg())
871 // If any source modifiers are set, the generic instruction commuting won't
872 // understand how to copy the source modifiers.
873 if (hasModifiersSet(*MI, AMDGPU::OpName::src0_modifiers) ||
874 hasModifiersSet(*MI, AMDGPU::OpName::src1_modifiers))
882 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
883 MachineBasicBlock::iterator I,
885 unsigned SrcReg) const {
886 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
887 DstReg) .addReg(SrcReg);
890 bool SIInstrInfo::isMov(unsigned Opcode) const {
892 default: return false;
893 case AMDGPU::S_MOV_B32:
894 case AMDGPU::S_MOV_B64:
895 case AMDGPU::V_MOV_B32_e32:
896 case AMDGPU::V_MOV_B32_e64:
902 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
903 return RC != &AMDGPU::EXECRegRegClass;
906 static void removeModOperands(MachineInstr &MI) {
907 unsigned Opc = MI.getOpcode();
908 int Src0ModIdx = AMDGPU::getNamedOperandIdx(Opc,
909 AMDGPU::OpName::src0_modifiers);
910 int Src1ModIdx = AMDGPU::getNamedOperandIdx(Opc,
911 AMDGPU::OpName::src1_modifiers);
912 int Src2ModIdx = AMDGPU::getNamedOperandIdx(Opc,
913 AMDGPU::OpName::src2_modifiers);
915 MI.RemoveOperand(Src2ModIdx);
916 MI.RemoveOperand(Src1ModIdx);
917 MI.RemoveOperand(Src0ModIdx);
920 bool SIInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
921 unsigned Reg, MachineRegisterInfo *MRI) const {
922 if (!MRI->hasOneNonDBGUse(Reg))
925 unsigned Opc = UseMI->getOpcode();
926 if (Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64) {
927 // Don't fold if we are using source modifiers. The new VOP2 instructions
929 if (hasModifiersSet(*UseMI, AMDGPU::OpName::src0_modifiers) ||
930 hasModifiersSet(*UseMI, AMDGPU::OpName::src1_modifiers) ||
931 hasModifiersSet(*UseMI, AMDGPU::OpName::src2_modifiers)) {
935 MachineOperand *Src0 = getNamedOperand(*UseMI, AMDGPU::OpName::src0);
936 MachineOperand *Src1 = getNamedOperand(*UseMI, AMDGPU::OpName::src1);
937 MachineOperand *Src2 = getNamedOperand(*UseMI, AMDGPU::OpName::src2);
939 // Multiplied part is the constant: Use v_madmk_f32
940 // We should only expect these to be on src0 due to canonicalizations.
941 if (Src0->isReg() && Src0->getReg() == Reg) {
942 if (!Src1->isReg() ||
943 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
946 if (!Src2->isReg() ||
947 (Src2->isReg() && RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))))
950 // We need to do some weird looking operand shuffling since the madmk
951 // operands are out of the normal expected order with the multiplied
952 // constant as the last operand.
954 // v_mad_f32 src0, src1, src2 -> v_madmk_f32 src0 * src2K + src1
959 const int64_t Imm = DefMI->getOperand(1).getImm();
961 // FIXME: This would be a lot easier if we could return a new instruction
962 // instead of having to modify in place.
964 // Remove these first since they are at the end.
965 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
966 AMDGPU::OpName::omod));
967 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
968 AMDGPU::OpName::clamp));
970 unsigned Src1Reg = Src1->getReg();
971 unsigned Src1SubReg = Src1->getSubReg();
972 unsigned Src2Reg = Src2->getReg();
973 unsigned Src2SubReg = Src2->getSubReg();
974 Src0->setReg(Src1Reg);
975 Src0->setSubReg(Src1SubReg);
976 Src0->setIsKill(Src1->isKill());
978 Src1->setReg(Src2Reg);
979 Src1->setSubReg(Src2SubReg);
980 Src1->setIsKill(Src2->isKill());
982 if (Opc == AMDGPU::V_MAC_F32_e64) {
983 UseMI->untieRegOperand(
984 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
987 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
988 AMDGPU::OpName::src2));
989 // ChangingToImmediate adds Src2 back to the instruction.
990 Src2->ChangeToImmediate(Imm);
992 removeModOperands(*UseMI);
993 UseMI->setDesc(get(AMDGPU::V_MADMK_F32));
995 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
997 DefMI->eraseFromParent();
1002 // Added part is the constant: Use v_madak_f32
1003 if (Src2->isReg() && Src2->getReg() == Reg) {
1004 // Not allowed to use constant bus for another operand.
1005 // We can however allow an inline immediate as src0.
1006 if (!Src0->isImm() &&
1007 (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg()))))
1010 if (!Src1->isReg() ||
1011 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
1014 const int64_t Imm = DefMI->getOperand(1).getImm();
1016 // FIXME: This would be a lot easier if we could return a new instruction
1017 // instead of having to modify in place.
1019 // Remove these first since they are at the end.
1020 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1021 AMDGPU::OpName::omod));
1022 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1023 AMDGPU::OpName::clamp));
1025 if (Opc == AMDGPU::V_MAC_F32_e64) {
1026 UseMI->untieRegOperand(
1027 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
1030 // ChangingToImmediate adds Src2 back to the instruction.
1031 Src2->ChangeToImmediate(Imm);
1033 // These come before src2.
1034 removeModOperands(*UseMI);
1035 UseMI->setDesc(get(AMDGPU::V_MADAK_F32));
1037 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1039 DefMI->eraseFromParent();
1048 static bool offsetsDoNotOverlap(int WidthA, int OffsetA,
1049 int WidthB, int OffsetB) {
1050 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
1051 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
1052 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
1053 return LowOffset + LowWidth <= HighOffset;
1056 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
1057 MachineInstr *MIb) const {
1058 unsigned BaseReg0, Offset0;
1059 unsigned BaseReg1, Offset1;
1061 if (getMemOpBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) &&
1062 getMemOpBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) {
1063 assert(MIa->hasOneMemOperand() && MIb->hasOneMemOperand() &&
1064 "read2 / write2 not expected here yet");
1065 unsigned Width0 = (*MIa->memoperands_begin())->getSize();
1066 unsigned Width1 = (*MIb->memoperands_begin())->getSize();
1067 if (BaseReg0 == BaseReg1 &&
1068 offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) {
1076 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
1078 AliasAnalysis *AA) const {
1079 unsigned Opc0 = MIa->getOpcode();
1080 unsigned Opc1 = MIb->getOpcode();
1082 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
1083 "MIa must load from or modify a memory location");
1084 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
1085 "MIb must load from or modify a memory location");
1087 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects())
1090 // XXX - Can we relax this between address spaces?
1091 if (MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
1094 // TODO: Should we check the address space from the MachineMemOperand? That
1095 // would allow us to distinguish objects we know don't alias based on the
1096 // underlying addres space, even if it was lowered to a different one,
1097 // e.g. private accesses lowered to use MUBUF instructions on a scratch
1101 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1103 return !isFLAT(Opc1);
1106 if (isMUBUF(Opc0) || isMTBUF(Opc0)) {
1107 if (isMUBUF(Opc1) || isMTBUF(Opc1))
1108 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1110 return !isFLAT(Opc1) && !isSMRD(Opc1);
1115 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1117 return !isFLAT(Opc1) && !isMUBUF(Opc0) && !isMTBUF(Opc0);
1122 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1130 MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB,
1131 MachineBasicBlock::iterator &MI,
1132 LiveVariables *LV) const {
1134 switch (MI->getOpcode()) {
1135 default: return nullptr;
1136 case AMDGPU::V_MAC_F32_e64: break;
1137 case AMDGPU::V_MAC_F32_e32: {
1138 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
1139 if (Src0->isImm() && !isInlineConstant(*Src0, 4))
1145 const MachineOperand *Dst = getNamedOperand(*MI, AMDGPU::OpName::dst);
1146 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
1147 const MachineOperand *Src1 = getNamedOperand(*MI, AMDGPU::OpName::src1);
1148 const MachineOperand *Src2 = getNamedOperand(*MI, AMDGPU::OpName::src2);
1150 return BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_MAD_F32))
1152 .addImm(0) // Src0 mods
1154 .addImm(0) // Src1 mods
1156 .addImm(0) // Src mods
1162 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
1163 int64_t SVal = Imm.getSExtValue();
1164 if (SVal >= -16 && SVal <= 64)
1167 if (Imm.getBitWidth() == 64) {
1168 uint64_t Val = Imm.getZExtValue();
1169 return (DoubleToBits(0.0) == Val) ||
1170 (DoubleToBits(1.0) == Val) ||
1171 (DoubleToBits(-1.0) == Val) ||
1172 (DoubleToBits(0.5) == Val) ||
1173 (DoubleToBits(-0.5) == Val) ||
1174 (DoubleToBits(2.0) == Val) ||
1175 (DoubleToBits(-2.0) == Val) ||
1176 (DoubleToBits(4.0) == Val) ||
1177 (DoubleToBits(-4.0) == Val);
1180 // The actual type of the operand does not seem to matter as long
1181 // as the bits match one of the inline immediate values. For example:
1183 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
1184 // so it is a legal inline immediate.
1186 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
1187 // floating-point, so it is a legal inline immediate.
1188 uint32_t Val = Imm.getZExtValue();
1190 return (FloatToBits(0.0f) == Val) ||
1191 (FloatToBits(1.0f) == Val) ||
1192 (FloatToBits(-1.0f) == Val) ||
1193 (FloatToBits(0.5f) == Val) ||
1194 (FloatToBits(-0.5f) == Val) ||
1195 (FloatToBits(2.0f) == Val) ||
1196 (FloatToBits(-2.0f) == Val) ||
1197 (FloatToBits(4.0f) == Val) ||
1198 (FloatToBits(-4.0f) == Val);
1201 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,
1202 unsigned OpSize) const {
1204 // MachineOperand provides no way to tell the true operand size, since it
1205 // only records a 64-bit value. We need to know the size to determine if a
1206 // 32-bit floating point immediate bit pattern is legal for an integer
1207 // immediate. It would be for any 32-bit integer operand, but would not be
1208 // for a 64-bit one.
1210 unsigned BitSize = 8 * OpSize;
1211 return isInlineConstant(APInt(BitSize, MO.getImm(), true));
1217 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO,
1218 unsigned OpSize) const {
1219 return MO.isImm() && !isInlineConstant(MO, OpSize);
1222 static bool compareMachineOp(const MachineOperand &Op0,
1223 const MachineOperand &Op1) {
1224 if (Op0.getType() != Op1.getType())
1227 switch (Op0.getType()) {
1228 case MachineOperand::MO_Register:
1229 return Op0.getReg() == Op1.getReg();
1230 case MachineOperand::MO_Immediate:
1231 return Op0.getImm() == Op1.getImm();
1233 llvm_unreachable("Didn't expect to be comparing these operand types");
1237 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
1238 const MachineOperand &MO) const {
1239 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
1241 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
1243 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
1246 if (OpInfo.RegClass < 0)
1249 unsigned OpSize = RI.getRegClass(OpInfo.RegClass)->getSize();
1250 if (isLiteralConstant(MO, OpSize))
1251 return RI.opCanUseLiteralConstant(OpInfo.OperandType);
1253 return RI.opCanUseInlineConstant(OpInfo.OperandType);
1256 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
1257 int Op32 = AMDGPU::getVOPe32(Opcode);
1261 return pseudoToMCOpcode(Op32) != -1;
1264 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
1265 // The src0_modifier operand is present on all instructions
1266 // that have modifiers.
1268 return AMDGPU::getNamedOperandIdx(Opcode,
1269 AMDGPU::OpName::src0_modifiers) != -1;
1272 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,
1273 unsigned OpName) const {
1274 const MachineOperand *Mods = getNamedOperand(MI, OpName);
1275 return Mods && Mods->getImm();
1278 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
1279 const MachineOperand &MO,
1280 unsigned OpSize) const {
1281 // Literal constants use the constant bus.
1282 if (isLiteralConstant(MO, OpSize))
1285 if (!MO.isReg() || !MO.isUse())
1288 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1289 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
1291 // FLAT_SCR is just an SGPR pair.
1292 if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
1295 // EXEC register uses the constant bus.
1296 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
1299 // SGPRs use the constant bus
1300 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
1301 (!MO.isImplicit() &&
1302 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
1303 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
1310 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
1311 StringRef &ErrInfo) const {
1312 uint16_t Opcode = MI->getOpcode();
1313 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1314 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
1315 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
1316 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
1318 // Make sure the number of operands is correct.
1319 const MCInstrDesc &Desc = get(Opcode);
1320 if (!Desc.isVariadic() &&
1321 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
1322 ErrInfo = "Instruction has wrong number of operands.";
1326 // Make sure the register classes are correct
1327 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
1328 if (MI->getOperand(i).isFPImm()) {
1329 ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast "
1330 "all fp values to integers.";
1334 int RegClass = Desc.OpInfo[i].RegClass;
1336 switch (Desc.OpInfo[i].OperandType) {
1337 case MCOI::OPERAND_REGISTER:
1338 if (MI->getOperand(i).isImm()) {
1339 ErrInfo = "Illegal immediate value for operand.";
1343 case AMDGPU::OPERAND_REG_IMM32:
1345 case AMDGPU::OPERAND_REG_INLINE_C:
1346 if (isLiteralConstant(MI->getOperand(i),
1347 RI.getRegClass(RegClass)->getSize())) {
1348 ErrInfo = "Illegal immediate value for operand.";
1352 case MCOI::OPERAND_IMMEDIATE:
1353 // Check if this operand is an immediate.
1354 // FrameIndex operands will be replaced by immediates, so they are
1356 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFI()) {
1357 ErrInfo = "Expected immediate, but got non-immediate";
1365 if (!MI->getOperand(i).isReg())
1368 if (RegClass != -1) {
1369 unsigned Reg = MI->getOperand(i).getReg();
1370 if (TargetRegisterInfo::isVirtualRegister(Reg))
1373 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
1374 if (!RC->contains(Reg)) {
1375 ErrInfo = "Operand has incorrect register class.";
1383 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
1384 // Only look at the true operands. Only a real operand can use the constant
1385 // bus, and we don't want to check pseudo-operands like the source modifier
1387 const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
1389 unsigned ConstantBusCount = 0;
1390 unsigned SGPRUsed = AMDGPU::NoRegister;
1391 for (int OpIdx : OpIndices) {
1394 const MachineOperand &MO = MI->getOperand(OpIdx);
1395 if (usesConstantBus(MRI, MO, getOpSize(Opcode, OpIdx))) {
1397 if (MO.getReg() != SGPRUsed)
1399 SGPRUsed = MO.getReg();
1405 if (ConstantBusCount > 1) {
1406 ErrInfo = "VOP* instruction uses the constant bus more than once";
1411 // Verify misc. restrictions on specific instructions.
1412 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
1413 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
1414 const MachineOperand &Src0 = MI->getOperand(Src0Idx);
1415 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1416 const MachineOperand &Src2 = MI->getOperand(Src2Idx);
1417 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
1418 if (!compareMachineOp(Src0, Src1) &&
1419 !compareMachineOp(Src0, Src2)) {
1420 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
1429 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
1430 switch (MI.getOpcode()) {
1431 default: return AMDGPU::INSTRUCTION_LIST_END;
1432 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
1433 case AMDGPU::COPY: return AMDGPU::COPY;
1434 case AMDGPU::PHI: return AMDGPU::PHI;
1435 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
1436 case AMDGPU::S_MOV_B32:
1437 return MI.getOperand(1).isReg() ?
1438 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
1439 case AMDGPU::S_ADD_I32:
1440 case AMDGPU::S_ADD_U32: return AMDGPU::V_ADD_I32_e32;
1441 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
1442 case AMDGPU::S_SUB_I32:
1443 case AMDGPU::S_SUB_U32: return AMDGPU::V_SUB_I32_e32;
1444 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
1445 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32;
1446 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
1447 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
1448 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
1449 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
1450 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
1451 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
1452 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
1453 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
1454 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
1455 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
1456 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
1457 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
1458 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
1459 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
1460 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
1461 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
1462 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
1463 case AMDGPU::S_BFM_B32: return AMDGPU::V_BFM_B32_e64;
1464 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
1465 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
1466 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
1467 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
1468 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
1469 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
1470 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
1471 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
1472 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
1473 case AMDGPU::S_LOAD_DWORD_IMM:
1474 case AMDGPU::S_LOAD_DWORD_SGPR: return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1475 case AMDGPU::S_LOAD_DWORDX2_IMM:
1476 case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1477 case AMDGPU::S_LOAD_DWORDX4_IMM:
1478 case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1479 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
1480 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
1481 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
1482 case AMDGPU::S_FLBIT_I32: return AMDGPU::V_FFBH_I32_e64;
1486 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
1487 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
1490 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
1491 unsigned OpNo) const {
1492 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1493 const MCInstrDesc &Desc = get(MI.getOpcode());
1494 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
1495 Desc.OpInfo[OpNo].RegClass == -1) {
1496 unsigned Reg = MI.getOperand(OpNo).getReg();
1498 if (TargetRegisterInfo::isVirtualRegister(Reg))
1499 return MRI.getRegClass(Reg);
1500 return RI.getPhysRegClass(Reg);
1503 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
1504 return RI.getRegClass(RCID);
1507 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
1508 switch (MI.getOpcode()) {
1510 case AMDGPU::REG_SEQUENCE:
1512 case AMDGPU::INSERT_SUBREG:
1513 return RI.hasVGPRs(getOpRegClass(MI, 0));
1515 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
1519 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
1520 MachineBasicBlock::iterator I = MI;
1521 MachineBasicBlock *MBB = MI->getParent();
1522 MachineOperand &MO = MI->getOperand(OpIdx);
1523 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1524 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
1525 const TargetRegisterClass *RC = RI.getRegClass(RCID);
1526 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1528 Opcode = AMDGPU::COPY;
1529 else if (RI.isSGPRClass(RC))
1530 Opcode = AMDGPU::S_MOV_B32;
1533 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
1534 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC))
1535 VRC = &AMDGPU::VReg_64RegClass;
1537 VRC = &AMDGPU::VGPR_32RegClass;
1539 unsigned Reg = MRI.createVirtualRegister(VRC);
1540 DebugLoc DL = MBB->findDebugLoc(I);
1541 BuildMI(*MI->getParent(), I, DL, get(Opcode), Reg)
1543 MO.ChangeToRegister(Reg, false);
1546 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
1547 MachineRegisterInfo &MRI,
1548 MachineOperand &SuperReg,
1549 const TargetRegisterClass *SuperRC,
1551 const TargetRegisterClass *SubRC)
1553 assert(SuperReg.isReg());
1555 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
1556 unsigned SubReg = MRI.createVirtualRegister(SubRC);
1558 // Just in case the super register is itself a sub-register, copy it to a new
1559 // value so we don't need to worry about merging its subreg index with the
1560 // SubIdx passed to this function. The register coalescer should be able to
1561 // eliminate this extra copy.
1562 MachineBasicBlock *MBB = MI->getParent();
1563 DebugLoc DL = MI->getDebugLoc();
1565 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
1566 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
1568 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1569 .addReg(NewSuperReg, 0, SubIdx);
1574 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
1575 MachineBasicBlock::iterator MII,
1576 MachineRegisterInfo &MRI,
1578 const TargetRegisterClass *SuperRC,
1580 const TargetRegisterClass *SubRC) const {
1582 // XXX - Is there a better way to do this?
1583 if (SubIdx == AMDGPU::sub0)
1584 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
1585 if (SubIdx == AMDGPU::sub1)
1586 return MachineOperand::CreateImm(Op.getImm() >> 32);
1588 llvm_unreachable("Unhandled register index for immediate");
1591 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
1593 return MachineOperand::CreateReg(SubReg, false);
1596 unsigned SIInstrInfo::split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
1597 MachineBasicBlock::iterator MI,
1598 MachineRegisterInfo &MRI,
1599 const TargetRegisterClass *RC,
1600 const MachineOperand &Op) const {
1601 MachineBasicBlock *MBB = MI->getParent();
1602 DebugLoc DL = MI->getDebugLoc();
1603 unsigned LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1604 unsigned HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1605 unsigned Dst = MRI.createVirtualRegister(RC);
1607 MachineInstr *Lo = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1609 .addImm(Op.getImm() & 0xFFFFFFFF);
1610 MachineInstr *Hi = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1612 .addImm(Op.getImm() >> 32);
1614 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
1616 .addImm(AMDGPU::sub0)
1618 .addImm(AMDGPU::sub1);
1620 Worklist.push_back(Lo);
1621 Worklist.push_back(Hi);
1626 // Change the order of operands from (0, 1, 2) to (0, 2, 1)
1627 void SIInstrInfo::swapOperands(MachineBasicBlock::iterator Inst) const {
1628 assert(Inst->getNumExplicitOperands() == 3);
1629 MachineOperand Op1 = Inst->getOperand(1);
1630 Inst->RemoveOperand(1);
1631 Inst->addOperand(Op1);
1634 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1635 const MachineOperand *MO) const {
1636 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1637 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1638 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
1639 const TargetRegisterClass *DefinedRC =
1640 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
1642 MO = &MI->getOperand(OpIdx);
1644 if (isVALU(InstDesc.Opcode) &&
1645 usesConstantBus(MRI, *MO, DefinedRC->getSize())) {
1647 MO->isReg() ? MO->getReg() : (unsigned)AMDGPU::NoRegister;
1648 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1651 const MachineOperand &Op = MI->getOperand(i);
1652 if (Op.isReg() && Op.getReg() != SGPRUsed &&
1653 usesConstantBus(MRI, Op, getOpSize(*MI, i))) {
1661 const TargetRegisterClass *RC =
1662 TargetRegisterInfo::isVirtualRegister(MO->getReg()) ?
1663 MRI.getRegClass(MO->getReg()) :
1664 RI.getPhysRegClass(MO->getReg());
1666 // In order to be legal, the common sub-class must be equal to the
1667 // class of the current operand. For example:
1669 // v_mov_b32 s0 ; Operand defined as vsrc_32
1670 // ; RI.getCommonSubClass(s0,vsrc_32) = sgpr ; LEGAL
1672 // s_sendmsg 0, s0 ; Operand defined as m0reg
1673 // ; RI.getCommonSubClass(s0,m0reg) = m0reg ; NOT LEGAL
1675 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC;
1679 // Handle non-register types that are treated like immediates.
1680 assert(MO->isImm() || MO->isTargetIndex() || MO->isFI());
1683 // This operand expects an immediate.
1687 return isImmOperandLegal(MI, OpIdx, *MO);
1690 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1691 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1693 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1694 AMDGPU::OpName::src0);
1695 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1696 AMDGPU::OpName::src1);
1697 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1698 AMDGPU::OpName::src2);
1701 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
1703 if (!isOperandLegal(MI, Src0Idx))
1704 legalizeOpWithMove(MI, Src0Idx);
1707 if (isOperandLegal(MI, Src1Idx))
1710 // Usually src0 of VOP2 instructions allow more types of inputs
1711 // than src1, so try to commute the instruction to decrease our
1712 // chances of having to insert a MOV instruction to legalize src1.
1713 if (MI->isCommutable()) {
1714 if (commuteInstruction(MI))
1715 // If we are successful in commuting, then we know MI is legal, so
1720 legalizeOpWithMove(MI, Src1Idx);
1724 // XXX - Do any VOP3 instructions read VCC?
1726 if (isVOP3(MI->getOpcode())) {
1727 int VOP3Idx[3] = { Src0Idx, Src1Idx, Src2Idx };
1729 // Find the one SGPR operand we are allowed to use.
1730 unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx);
1732 for (unsigned i = 0; i < 3; ++i) {
1733 int Idx = VOP3Idx[i];
1736 MachineOperand &MO = MI->getOperand(Idx);
1739 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1740 continue; // VGPRs are legal
1742 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
1744 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1745 SGPRReg = MO.getReg();
1746 // We can use one SGPR in each VOP3 instruction.
1749 } else if (!isLiteralConstant(MO, getOpSize(MI->getOpcode(), Idx))) {
1750 // If it is not a register and not a literal constant, then it must be
1751 // an inline constant which is always legal.
1754 // If we make it this far, then the operand is not legal and we must
1756 legalizeOpWithMove(MI, Idx);
1760 // Legalize REG_SEQUENCE and PHI
1761 // The register class of the operands much be the same type as the register
1762 // class of the output.
1763 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE ||
1764 MI->getOpcode() == AMDGPU::PHI) {
1765 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1766 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1767 if (!MI->getOperand(i).isReg() ||
1768 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1770 const TargetRegisterClass *OpRC =
1771 MRI.getRegClass(MI->getOperand(i).getReg());
1772 if (RI.hasVGPRs(OpRC)) {
1779 // If any of the operands are VGPR registers, then they all most be
1780 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1782 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1785 VRC = RI.getEquivalentVGPRClass(SRC);
1792 // Update all the operands so they have the same type.
1793 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1794 if (!MI->getOperand(i).isReg() ||
1795 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1797 unsigned DstReg = MRI.createVirtualRegister(RC);
1798 MachineBasicBlock *InsertBB;
1799 MachineBasicBlock::iterator Insert;
1800 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1801 InsertBB = MI->getParent();
1804 // MI is a PHI instruction.
1805 InsertBB = MI->getOperand(i + 1).getMBB();
1806 Insert = InsertBB->getFirstTerminator();
1808 BuildMI(*InsertBB, Insert, MI->getDebugLoc(),
1809 get(AMDGPU::COPY), DstReg)
1810 .addOperand(MI->getOperand(i));
1811 MI->getOperand(i).setReg(DstReg);
1815 // Legalize INSERT_SUBREG
1816 // src0 must have the same register class as dst
1817 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
1818 unsigned Dst = MI->getOperand(0).getReg();
1819 unsigned Src0 = MI->getOperand(1).getReg();
1820 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1821 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1822 if (DstRC != Src0RC) {
1823 MachineBasicBlock &MBB = *MI->getParent();
1824 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
1825 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
1827 MI->getOperand(1).setReg(NewSrc0);
1832 // Legalize MUBUF* instructions
1833 // FIXME: If we start using the non-addr64 instructions for compute, we
1834 // may need to legalize them here.
1836 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc);
1837 if (SRsrcIdx != -1) {
1838 // We have an MUBUF instruction
1839 MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx);
1840 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass;
1841 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()),
1842 RI.getRegClass(SRsrcRC))) {
1843 // The operands are legal.
1844 // FIXME: We may need to legalize operands besided srsrc.
1848 MachineBasicBlock &MBB = *MI->getParent();
1849 // Extract the ptr from the resource descriptor.
1851 // SRsrcPtrLo = srsrc:sub0
1852 unsigned SRsrcPtrLo = buildExtractSubReg(MI, MRI, *SRsrc,
1853 &AMDGPU::VReg_128RegClass, AMDGPU::sub0, &AMDGPU::VGPR_32RegClass);
1855 // SRsrcPtrHi = srsrc:sub1
1856 unsigned SRsrcPtrHi = buildExtractSubReg(MI, MRI, *SRsrc,
1857 &AMDGPU::VReg_128RegClass, AMDGPU::sub1, &AMDGPU::VGPR_32RegClass);
1859 // Create an empty resource descriptor
1860 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1861 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1862 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1863 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1864 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
1867 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1871 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1872 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1874 .addImm(RsrcDataFormat & 0xFFFFFFFF);
1876 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1877 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1879 .addImm(RsrcDataFormat >> 32);
1881 // NewSRsrc = {Zero64, SRsrcFormat}
1882 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1885 .addImm(AMDGPU::sub0_sub1)
1886 .addReg(SRsrcFormatLo)
1887 .addImm(AMDGPU::sub2)
1888 .addReg(SRsrcFormatHi)
1889 .addImm(AMDGPU::sub3);
1891 MachineOperand *VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1892 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
1893 unsigned NewVAddrLo;
1894 unsigned NewVAddrHi;
1896 // This is already an ADDR64 instruction so we need to add the pointer
1897 // extracted from the resource descriptor to the current value of VAddr.
1898 NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1899 NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1901 // NewVaddrLo = SRsrcPtrLo + VAddr:sub0
1902 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADD_I32_e32),
1905 .addReg(VAddr->getReg(), 0, AMDGPU::sub0)
1906 .addReg(AMDGPU::VCC, RegState::ImplicitDefine);
1908 // NewVaddrHi = SRsrcPtrHi + VAddr:sub1
1909 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADDC_U32_e32),
1912 .addReg(VAddr->getReg(), 0, AMDGPU::sub1)
1913 .addReg(AMDGPU::VCC, RegState::ImplicitDefine)
1914 .addReg(AMDGPU::VCC, RegState::Implicit);
1917 // This instructions is the _OFFSET variant, so we need to convert it to
1919 MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata);
1920 MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset);
1921 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset);
1923 // Create the new instruction.
1924 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
1925 MachineInstr *Addr64 =
1926 BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
1928 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
1929 // This will be replaced later
1930 // with the new value of vaddr.
1932 .addOperand(*SOffset)
1933 .addOperand(*Offset)
1938 MI->removeFromParent();
1941 NewVAddrLo = SRsrcPtrLo;
1942 NewVAddrHi = SRsrcPtrHi;
1943 VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1944 SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc);
1947 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1948 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1951 .addImm(AMDGPU::sub0)
1953 .addImm(AMDGPU::sub1);
1956 // Update the instruction to use NewVaddr
1957 VAddr->setReg(NewVAddr);
1958 // Update the instruction to use NewSRsrc
1959 SRsrc->setReg(NewSRsrc);
1963 void SIInstrInfo::splitSMRD(MachineInstr *MI,
1964 const TargetRegisterClass *HalfRC,
1965 unsigned HalfImmOp, unsigned HalfSGPROp,
1966 MachineInstr *&Lo, MachineInstr *&Hi) const {
1968 DebugLoc DL = MI->getDebugLoc();
1969 MachineBasicBlock *MBB = MI->getParent();
1970 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1971 unsigned RegLo = MRI.createVirtualRegister(HalfRC);
1972 unsigned RegHi = MRI.createVirtualRegister(HalfRC);
1973 unsigned HalfSize = HalfRC->getSize();
1974 const MachineOperand *OffOp =
1975 getNamedOperand(*MI, AMDGPU::OpName::offset);
1976 const MachineOperand *SBase = getNamedOperand(*MI, AMDGPU::OpName::sbase);
1978 // The SMRD has an 8-bit offset in dwords on SI and a 20-bit offset in bytes
1981 bool IsKill = SBase->isKill();
1984 MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() >=
1985 AMDGPUSubtarget::VOLCANIC_ISLANDS;
1986 unsigned OffScale = isVI ? 1 : 4;
1987 // Handle the _IMM variant
1988 unsigned LoOffset = OffOp->getImm() * OffScale;
1989 unsigned HiOffset = LoOffset + HalfSize;
1990 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo)
1991 // Use addReg instead of addOperand
1992 // to make sure kill flag is cleared.
1993 .addReg(SBase->getReg(), 0, SBase->getSubReg())
1994 .addImm(LoOffset / OffScale);
1996 if (!isUInt<20>(HiOffset) || (!isVI && !isUInt<8>(HiOffset / OffScale))) {
1997 unsigned OffsetSGPR =
1998 MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1999 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR)
2000 .addImm(HiOffset); // The offset in register is in bytes.
2001 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
2002 .addReg(SBase->getReg(), getKillRegState(IsKill),
2004 .addReg(OffsetSGPR);
2006 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi)
2007 .addReg(SBase->getReg(), getKillRegState(IsKill),
2009 .addImm(HiOffset / OffScale);
2012 // Handle the _SGPR variant
2013 MachineOperand *SOff = getNamedOperand(*MI, AMDGPU::OpName::soff);
2014 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo)
2015 .addReg(SBase->getReg(), 0, SBase->getSubReg())
2017 unsigned OffsetSGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
2018 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR)
2021 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp))
2022 .addReg(SBase->getReg(), getKillRegState(IsKill),
2024 .addReg(OffsetSGPR);
2027 unsigned SubLo, SubHi;
2030 SubLo = AMDGPU::sub0;
2031 SubHi = AMDGPU::sub1;
2034 SubLo = AMDGPU::sub0_sub1;
2035 SubHi = AMDGPU::sub2_sub3;
2038 SubLo = AMDGPU::sub0_sub1_sub2_sub3;
2039 SubHi = AMDGPU::sub4_sub5_sub6_sub7;
2042 SubLo = AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7;
2043 SubHi = AMDGPU::sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15;
2046 llvm_unreachable("Unhandled HalfSize");
2049 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE))
2050 .addOperand(MI->getOperand(0))
2057 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
2058 MachineBasicBlock *MBB = MI->getParent();
2059 switch (MI->getOpcode()) {
2060 case AMDGPU::S_LOAD_DWORD_IMM:
2061 case AMDGPU::S_LOAD_DWORD_SGPR:
2062 case AMDGPU::S_LOAD_DWORDX2_IMM:
2063 case AMDGPU::S_LOAD_DWORDX2_SGPR:
2064 case AMDGPU::S_LOAD_DWORDX4_IMM:
2065 case AMDGPU::S_LOAD_DWORDX4_SGPR: {
2066 unsigned NewOpcode = getVALUOp(*MI);
2070 if (MI->getOperand(2).isReg()) {
2071 RegOffset = MI->getOperand(2).getReg();
2074 assert(MI->getOperand(2).isImm());
2075 // SMRD instructions take a dword offsets on SI and byte offset on VI
2076 // and MUBUF instructions always take a byte offset.
2077 ImmOffset = MI->getOperand(2).getImm();
2078 if (MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() <=
2079 AMDGPUSubtarget::SEA_ISLANDS)
2081 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2083 if (isUInt<12>(ImmOffset)) {
2084 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2088 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2095 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
2096 unsigned DWord0 = RegOffset;
2097 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2098 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2099 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2100 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
2102 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
2104 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
2105 .addImm(RsrcDataFormat & 0xFFFFFFFF);
2106 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
2107 .addImm(RsrcDataFormat >> 32);
2108 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
2110 .addImm(AMDGPU::sub0)
2112 .addImm(AMDGPU::sub1)
2114 .addImm(AMDGPU::sub2)
2116 .addImm(AMDGPU::sub3);
2117 MI->setDesc(get(NewOpcode));
2118 if (MI->getOperand(2).isReg()) {
2119 MI->getOperand(2).setReg(SRsrc);
2121 MI->getOperand(2).ChangeToRegister(SRsrc, false);
2123 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0));
2124 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
2125 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0)); // glc
2126 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0)); // slc
2127 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0)); // tfe
2129 const TargetRegisterClass *NewDstRC =
2130 RI.getRegClass(get(NewOpcode).OpInfo[0].RegClass);
2132 unsigned DstReg = MI->getOperand(0).getReg();
2133 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2134 MRI.replaceRegWith(DstReg, NewDstReg);
2137 case AMDGPU::S_LOAD_DWORDX8_IMM:
2138 case AMDGPU::S_LOAD_DWORDX8_SGPR: {
2139 MachineInstr *Lo, *Hi;
2140 splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
2141 AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
2142 MI->eraseFromParent();
2143 moveSMRDToVALU(Lo, MRI);
2144 moveSMRDToVALU(Hi, MRI);
2148 case AMDGPU::S_LOAD_DWORDX16_IMM:
2149 case AMDGPU::S_LOAD_DWORDX16_SGPR: {
2150 MachineInstr *Lo, *Hi;
2151 splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
2152 AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
2153 MI->eraseFromParent();
2154 moveSMRDToVALU(Lo, MRI);
2155 moveSMRDToVALU(Hi, MRI);
2161 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
2162 SmallVector<MachineInstr *, 128> Worklist;
2163 Worklist.push_back(&TopInst);
2165 while (!Worklist.empty()) {
2166 MachineInstr *Inst = Worklist.pop_back_val();
2167 MachineBasicBlock *MBB = Inst->getParent();
2168 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2170 unsigned Opcode = Inst->getOpcode();
2171 unsigned NewOpcode = getVALUOp(*Inst);
2173 // Handle some special cases
2176 if (isSMRD(Inst->getOpcode())) {
2177 moveSMRDToVALU(Inst, MRI);
2180 case AMDGPU::S_MOV_B64: {
2181 DebugLoc DL = Inst->getDebugLoc();
2183 // If the source operand is a register we can replace this with a
2185 if (Inst->getOperand(1).isReg()) {
2186 MachineInstr *Copy = BuildMI(*MBB, Inst, DL, get(TargetOpcode::COPY))
2187 .addOperand(Inst->getOperand(0))
2188 .addOperand(Inst->getOperand(1));
2189 Worklist.push_back(Copy);
2191 // Otherwise, we need to split this into two movs, because there is
2192 // no 64-bit VALU move instruction.
2193 unsigned Reg = Inst->getOperand(0).getReg();
2194 unsigned Dst = split64BitImm(Worklist,
2197 MRI.getRegClass(Reg),
2198 Inst->getOperand(1));
2199 MRI.replaceRegWith(Reg, Dst);
2201 Inst->eraseFromParent();
2204 case AMDGPU::S_AND_B64:
2205 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32);
2206 Inst->eraseFromParent();
2209 case AMDGPU::S_OR_B64:
2210 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_OR_B32);
2211 Inst->eraseFromParent();
2214 case AMDGPU::S_XOR_B64:
2215 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XOR_B32);
2216 Inst->eraseFromParent();
2219 case AMDGPU::S_NOT_B64:
2220 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::S_NOT_B32);
2221 Inst->eraseFromParent();
2224 case AMDGPU::S_BCNT1_I32_B64:
2225 splitScalar64BitBCNT(Worklist, Inst);
2226 Inst->eraseFromParent();
2229 case AMDGPU::S_BFE_I64: {
2230 splitScalar64BitBFE(Worklist, Inst);
2231 Inst->eraseFromParent();
2235 case AMDGPU::S_LSHL_B32:
2236 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2237 NewOpcode = AMDGPU::V_LSHLREV_B32_e64;
2241 case AMDGPU::S_ASHR_I32:
2242 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2243 NewOpcode = AMDGPU::V_ASHRREV_I32_e64;
2247 case AMDGPU::S_LSHR_B32:
2248 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2249 NewOpcode = AMDGPU::V_LSHRREV_B32_e64;
2253 case AMDGPU::S_LSHL_B64:
2254 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2255 NewOpcode = AMDGPU::V_LSHLREV_B64;
2259 case AMDGPU::S_ASHR_I64:
2260 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2261 NewOpcode = AMDGPU::V_ASHRREV_I64;
2265 case AMDGPU::S_LSHR_B64:
2266 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2267 NewOpcode = AMDGPU::V_LSHRREV_B64;
2272 case AMDGPU::S_BFE_U64:
2273 case AMDGPU::S_BFM_B64:
2274 llvm_unreachable("Moving this op to VALU not implemented");
2277 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
2278 // We cannot move this instruction to the VALU, so we should try to
2279 // legalize its operands instead.
2280 legalizeOperands(Inst);
2284 // Use the new VALU Opcode.
2285 const MCInstrDesc &NewDesc = get(NewOpcode);
2286 Inst->setDesc(NewDesc);
2288 // Remove any references to SCC. Vector instructions can't read from it, and
2289 // We're just about to add the implicit use / defs of VCC, and we don't want
2291 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
2292 MachineOperand &Op = Inst->getOperand(i);
2293 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
2294 Inst->RemoveOperand(i);
2297 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
2298 // We are converting these to a BFE, so we need to add the missing
2299 // operands for the size and offset.
2300 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
2301 Inst->addOperand(MachineOperand::CreateImm(0));
2302 Inst->addOperand(MachineOperand::CreateImm(Size));
2304 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
2305 // The VALU version adds the second operand to the result, so insert an
2307 Inst->addOperand(MachineOperand::CreateImm(0));
2310 addDescImplicitUseDef(NewDesc, Inst);
2312 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
2313 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
2314 // If we need to move this to VGPRs, we need to unpack the second operand
2315 // back into the 2 separate ones for bit offset and width.
2316 assert(OffsetWidthOp.isImm() &&
2317 "Scalar BFE is only implemented for constant width and offset");
2318 uint32_t Imm = OffsetWidthOp.getImm();
2320 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2321 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2322 Inst->RemoveOperand(2); // Remove old immediate.
2323 Inst->addOperand(MachineOperand::CreateImm(Offset));
2324 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
2327 // Update the destination register class.
2329 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
2332 // For target instructions, getOpRegClass just returns the virtual
2333 // register class associated with the operand, so we need to find an
2334 // equivalent VGPR register class in order to move the instruction to the
2338 case AMDGPU::REG_SEQUENCE:
2339 case AMDGPU::INSERT_SUBREG:
2340 if (RI.hasVGPRs(NewDstRC))
2342 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
2350 unsigned DstReg = Inst->getOperand(0).getReg();
2351 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2352 MRI.replaceRegWith(DstReg, NewDstReg);
2354 // Legalize the operands
2355 legalizeOperands(Inst);
2357 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
2358 E = MRI.use_end(); I != E; ++I) {
2359 MachineInstr &UseMI = *I->getParent();
2360 if (!canReadVGPR(UseMI, I.getOperandNo())) {
2361 Worklist.push_back(&UseMI);
2367 //===----------------------------------------------------------------------===//
2368 // Indirect addressing callbacks
2369 //===----------------------------------------------------------------------===//
2371 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
2372 unsigned Channel) const {
2373 assert(Channel == 0);
2377 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
2378 return &AMDGPU::VGPR_32RegClass;
2381 void SIInstrInfo::splitScalar64BitUnaryOp(
2382 SmallVectorImpl<MachineInstr *> &Worklist,
2384 unsigned Opcode) const {
2385 MachineBasicBlock &MBB = *Inst->getParent();
2386 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2388 MachineOperand &Dest = Inst->getOperand(0);
2389 MachineOperand &Src0 = Inst->getOperand(1);
2390 DebugLoc DL = Inst->getDebugLoc();
2392 MachineBasicBlock::iterator MII = Inst;
2394 const MCInstrDesc &InstDesc = get(Opcode);
2395 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2396 MRI.getRegClass(Src0.getReg()) :
2397 &AMDGPU::SGPR_32RegClass;
2399 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2401 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2402 AMDGPU::sub0, Src0SubRC);
2404 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2405 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
2407 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
2408 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2409 .addOperand(SrcReg0Sub0);
2411 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2412 AMDGPU::sub1, Src0SubRC);
2414 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
2415 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2416 .addOperand(SrcReg0Sub1);
2418 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
2419 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2421 .addImm(AMDGPU::sub0)
2423 .addImm(AMDGPU::sub1);
2425 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2427 // Try to legalize the operands in case we need to swap the order to keep it
2429 Worklist.push_back(LoHalf);
2430 Worklist.push_back(HiHalf);
2433 void SIInstrInfo::splitScalar64BitBinaryOp(
2434 SmallVectorImpl<MachineInstr *> &Worklist,
2436 unsigned Opcode) const {
2437 MachineBasicBlock &MBB = *Inst->getParent();
2438 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2440 MachineOperand &Dest = Inst->getOperand(0);
2441 MachineOperand &Src0 = Inst->getOperand(1);
2442 MachineOperand &Src1 = Inst->getOperand(2);
2443 DebugLoc DL = Inst->getDebugLoc();
2445 MachineBasicBlock::iterator MII = Inst;
2447 const MCInstrDesc &InstDesc = get(Opcode);
2448 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2449 MRI.getRegClass(Src0.getReg()) :
2450 &AMDGPU::SGPR_32RegClass;
2452 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2453 const TargetRegisterClass *Src1RC = Src1.isReg() ?
2454 MRI.getRegClass(Src1.getReg()) :
2455 &AMDGPU::SGPR_32RegClass;
2457 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
2459 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2460 AMDGPU::sub0, Src0SubRC);
2461 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2462 AMDGPU::sub0, Src1SubRC);
2464 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2465 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
2467 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
2468 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2469 .addOperand(SrcReg0Sub0)
2470 .addOperand(SrcReg1Sub0);
2472 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2473 AMDGPU::sub1, Src0SubRC);
2474 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2475 AMDGPU::sub1, Src1SubRC);
2477 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
2478 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2479 .addOperand(SrcReg0Sub1)
2480 .addOperand(SrcReg1Sub1);
2482 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
2483 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2485 .addImm(AMDGPU::sub0)
2487 .addImm(AMDGPU::sub1);
2489 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2491 // Try to legalize the operands in case we need to swap the order to keep it
2493 Worklist.push_back(LoHalf);
2494 Worklist.push_back(HiHalf);
2497 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
2498 MachineInstr *Inst) const {
2499 MachineBasicBlock &MBB = *Inst->getParent();
2500 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2502 MachineBasicBlock::iterator MII = Inst;
2503 DebugLoc DL = Inst->getDebugLoc();
2505 MachineOperand &Dest = Inst->getOperand(0);
2506 MachineOperand &Src = Inst->getOperand(1);
2508 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
2509 const TargetRegisterClass *SrcRC = Src.isReg() ?
2510 MRI.getRegClass(Src.getReg()) :
2511 &AMDGPU::SGPR_32RegClass;
2513 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2514 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2516 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
2518 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2519 AMDGPU::sub0, SrcSubRC);
2520 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2521 AMDGPU::sub1, SrcSubRC);
2523 MachineInstr *First = BuildMI(MBB, MII, DL, InstDesc, MidReg)
2524 .addOperand(SrcRegSub0)
2527 MachineInstr *Second = BuildMI(MBB, MII, DL, InstDesc, ResultReg)
2528 .addOperand(SrcRegSub1)
2531 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2533 Worklist.push_back(First);
2534 Worklist.push_back(Second);
2537 void SIInstrInfo::splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
2538 MachineInstr *Inst) const {
2539 MachineBasicBlock &MBB = *Inst->getParent();
2540 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2541 MachineBasicBlock::iterator MII = Inst;
2542 DebugLoc DL = Inst->getDebugLoc();
2544 MachineOperand &Dest = Inst->getOperand(0);
2545 uint32_t Imm = Inst->getOperand(2).getImm();
2546 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2547 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2551 // Only sext_inreg cases handled.
2552 assert(Inst->getOpcode() == AMDGPU::S_BFE_I64 &&
2557 if (BitWidth < 32) {
2558 unsigned MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2559 unsigned MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2560 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2562 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo)
2563 .addReg(Inst->getOperand(1).getReg(), 0, AMDGPU::sub0)
2567 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi)
2571 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2573 .addImm(AMDGPU::sub0)
2575 .addImm(AMDGPU::sub1);
2577 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2581 MachineOperand &Src = Inst->getOperand(1);
2582 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2583 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2585 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
2587 .addReg(Src.getReg(), 0, AMDGPU::sub0);
2589 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2590 .addReg(Src.getReg(), 0, AMDGPU::sub0)
2591 .addImm(AMDGPU::sub0)
2593 .addImm(AMDGPU::sub1);
2595 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2598 void SIInstrInfo::addDescImplicitUseDef(const MCInstrDesc &NewDesc,
2599 MachineInstr *Inst) const {
2600 // Add the implict and explicit register definitions.
2601 if (NewDesc.ImplicitUses) {
2602 for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
2603 unsigned Reg = NewDesc.ImplicitUses[i];
2604 Inst->addOperand(MachineOperand::CreateReg(Reg, false, true));
2608 if (NewDesc.ImplicitDefs) {
2609 for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
2610 unsigned Reg = NewDesc.ImplicitDefs[i];
2611 Inst->addOperand(MachineOperand::CreateReg(Reg, true, true));
2616 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
2617 int OpIndices[3]) const {
2618 const MCInstrDesc &Desc = get(MI->getOpcode());
2620 // Find the one SGPR operand we are allowed to use.
2621 unsigned SGPRReg = AMDGPU::NoRegister;
2623 // First we need to consider the instruction's operand requirements before
2624 // legalizing. Some operands are required to be SGPRs, such as implicit uses
2625 // of VCC, but we are still bound by the constant bus requirement to only use
2628 // If the operand's class is an SGPR, we can never move it.
2630 for (const MachineOperand &MO : MI->implicit_operands()) {
2631 // We only care about reads.
2635 if (MO.getReg() == AMDGPU::VCC)
2638 if (MO.getReg() == AMDGPU::FLAT_SCR)
2639 return AMDGPU::FLAT_SCR;
2642 unsigned UsedSGPRs[3] = { AMDGPU::NoRegister };
2643 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
2645 for (unsigned i = 0; i < 3; ++i) {
2646 int Idx = OpIndices[i];
2650 const MachineOperand &MO = MI->getOperand(Idx);
2651 if (RI.isSGPRClassID(Desc.OpInfo[Idx].RegClass))
2652 SGPRReg = MO.getReg();
2654 if (MO.isReg() && RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
2655 UsedSGPRs[i] = MO.getReg();
2658 if (SGPRReg != AMDGPU::NoRegister)
2661 // We don't have a required SGPR operand, so we have a bit more freedom in
2662 // selecting operands to move.
2664 // Try to select the most used SGPR. If an SGPR is equal to one of the
2665 // others, we choose that.
2668 // V_FMA_F32 v0, s0, s0, s0 -> No moves
2669 // V_FMA_F32 v0, s0, s1, s0 -> Move s1
2671 if (UsedSGPRs[0] != AMDGPU::NoRegister) {
2672 if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2])
2673 SGPRReg = UsedSGPRs[0];
2676 if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) {
2677 if (UsedSGPRs[1] == UsedSGPRs[2])
2678 SGPRReg = UsedSGPRs[1];
2684 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
2685 MachineBasicBlock *MBB,
2686 MachineBasicBlock::iterator I,
2688 unsigned Address, unsigned OffsetReg) const {
2689 const DebugLoc &DL = MBB->findDebugLoc(I);
2690 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2691 getIndirectIndexBegin(*MBB->getParent()));
2693 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
2694 .addReg(IndirectBaseReg, RegState::Define)
2695 .addOperand(I->getOperand(0))
2696 .addReg(IndirectBaseReg)
2702 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
2703 MachineBasicBlock *MBB,
2704 MachineBasicBlock::iterator I,
2706 unsigned Address, unsigned OffsetReg) const {
2707 const DebugLoc &DL = MBB->findDebugLoc(I);
2708 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2709 getIndirectIndexBegin(*MBB->getParent()));
2711 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
2712 .addOperand(I->getOperand(0))
2713 .addOperand(I->getOperand(1))
2714 .addReg(IndirectBaseReg)
2720 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
2721 const MachineFunction &MF) const {
2722 int End = getIndirectIndexEnd(MF);
2723 int Begin = getIndirectIndexBegin(MF);
2729 for (int Index = Begin; Index <= End; ++Index)
2730 Reserved.set(AMDGPU::VGPR_32RegClass.getRegister(Index));
2732 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
2733 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
2735 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
2736 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
2738 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
2739 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
2741 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
2742 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
2744 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
2745 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
2748 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
2749 unsigned OperandName) const {
2750 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
2754 return &MI.getOperand(Idx);
2757 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {
2758 uint64_t RsrcDataFormat = AMDGPU::RSRC_DATA_FORMAT;
2759 if (ST.isAmdHsaOS()) {
2760 RsrcDataFormat |= (1ULL << 56);
2762 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2764 RsrcDataFormat |= (2ULL << 59);
2767 return RsrcDataFormat;