1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_R600_SIINSTRINFO_H
17 #define LLVM_LIB_TARGET_R600_SIINSTRINFO_H
19 #include "AMDGPUInstrInfo.h"
20 #include "SIDefines.h"
21 #include "SIRegisterInfo.h"
25 class SIInstrInfo : public AMDGPUInstrInfo {
27 const SIRegisterInfo RI;
29 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
30 MachineRegisterInfo &MRI,
31 MachineOperand &SuperReg,
32 const TargetRegisterClass *SuperRC,
34 const TargetRegisterClass *SubRC) const;
35 MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
36 MachineRegisterInfo &MRI,
37 MachineOperand &SuperReg,
38 const TargetRegisterClass *SuperRC,
40 const TargetRegisterClass *SubRC) const;
42 unsigned split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
43 MachineBasicBlock::iterator MI,
44 MachineRegisterInfo &MRI,
45 const TargetRegisterClass *RC,
46 const MachineOperand &Op) const;
48 void swapOperands(MachineBasicBlock::iterator Inst) const;
50 void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
51 MachineInstr *Inst, unsigned Opcode) const;
53 void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
54 MachineInstr *Inst, unsigned Opcode) const;
56 void splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
57 MachineInstr *Inst) const;
58 void splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
59 MachineInstr *Inst) const;
61 void addDescImplicitUseDef(const MCInstrDesc &Desc, MachineInstr *MI) const;
63 bool checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
64 MachineInstr *MIb) const;
66 unsigned findUsedSGPR(const MachineInstr *MI, int OpIndices[3]) const;
69 explicit SIInstrInfo(const AMDGPUSubtarget &st);
71 const SIRegisterInfo &getRegisterInfo() const override {
75 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
76 AliasAnalysis *AA) const override;
78 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
80 int64_t &Offset2) const override;
82 bool getLdStBaseRegImmOfs(MachineInstr *LdSt,
83 unsigned &BaseReg, unsigned &Offset,
84 const TargetRegisterInfo *TRI) const final;
86 bool shouldClusterLoads(MachineInstr *FirstLdSt,
87 MachineInstr *SecondLdSt,
88 unsigned NumLoads) const final;
90 void copyPhysReg(MachineBasicBlock &MBB,
91 MachineBasicBlock::iterator MI, DebugLoc DL,
92 unsigned DestReg, unsigned SrcReg,
93 bool KillSrc) const override;
95 unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB,
96 MachineBasicBlock::iterator MI,
100 unsigned Size) const;
102 void storeRegToStackSlot(MachineBasicBlock &MBB,
103 MachineBasicBlock::iterator MI,
104 unsigned SrcReg, bool isKill, int FrameIndex,
105 const TargetRegisterClass *RC,
106 const TargetRegisterInfo *TRI) const override;
108 void loadRegFromStackSlot(MachineBasicBlock &MBB,
109 MachineBasicBlock::iterator MI,
110 unsigned DestReg, int FrameIndex,
111 const TargetRegisterClass *RC,
112 const TargetRegisterInfo *TRI) const override;
114 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
116 // \brief Returns an opcode that can be used to move a value to a \p DstRC
117 // register. If there is no hardware instruction that can store to \p
118 // DstRC, then AMDGPU::COPY is returned.
119 unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
120 unsigned commuteOpcode(const MachineInstr &MI) const;
122 MachineInstr *commuteInstruction(MachineInstr *MI,
123 bool NewMI = false) const override;
124 bool findCommutedOpIndices(MachineInstr *MI,
126 unsigned &SrcOpIdx2) const override;
128 bool isTriviallyReMaterializable(const MachineInstr *MI,
129 AliasAnalysis *AA = nullptr) const;
131 bool areMemAccessesTriviallyDisjoint(
132 MachineInstr *MIa, MachineInstr *MIb,
133 AliasAnalysis *AA = nullptr) const override;
135 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
136 MachineBasicBlock::iterator I,
137 unsigned DstReg, unsigned SrcReg) const override;
138 bool isMov(unsigned Opcode) const override;
140 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
142 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
143 unsigned Reg, MachineRegisterInfo *MRI) const final;
145 unsigned getMachineCSELookAheadLimit() const override { return 500; }
147 bool isSALU(uint16_t Opcode) const {
148 return get(Opcode).TSFlags & SIInstrFlags::SALU;
151 bool isVALU(uint16_t Opcode) const {
152 return get(Opcode).TSFlags & SIInstrFlags::VALU;
155 bool isSOP1(uint16_t Opcode) const {
156 return get(Opcode).TSFlags & SIInstrFlags::SOP1;
159 bool isSOP2(uint16_t Opcode) const {
160 return get(Opcode).TSFlags & SIInstrFlags::SOP2;
163 bool isSOPC(uint16_t Opcode) const {
164 return get(Opcode).TSFlags & SIInstrFlags::SOPC;
167 bool isSOPK(uint16_t Opcode) const {
168 return get(Opcode).TSFlags & SIInstrFlags::SOPK;
171 bool isSOPP(uint16_t Opcode) const {
172 return get(Opcode).TSFlags & SIInstrFlags::SOPP;
175 bool isVOP1(uint16_t Opcode) const {
176 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
179 bool isVOP2(uint16_t Opcode) const {
180 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
183 bool isVOP3(uint16_t Opcode) const {
184 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
187 bool isVOPC(uint16_t Opcode) const {
188 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
191 bool isMUBUF(uint16_t Opcode) const {
192 return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
195 bool isMTBUF(uint16_t Opcode) const {
196 return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
199 bool isSMRD(uint16_t Opcode) const {
200 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
203 bool isDS(uint16_t Opcode) const {
204 return get(Opcode).TSFlags & SIInstrFlags::DS;
207 bool isMIMG(uint16_t Opcode) const {
208 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
211 bool isFLAT(uint16_t Opcode) const {
212 return get(Opcode).TSFlags & SIInstrFlags::FLAT;
215 bool isWQM(uint16_t Opcode) const {
216 return get(Opcode).TSFlags & SIInstrFlags::WQM;
219 bool isVGPRSpill(uint16_t Opcode) const {
220 return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
223 bool isInlineConstant(const APInt &Imm) const;
224 bool isInlineConstant(const MachineOperand &MO, unsigned OpSize) const;
225 bool isLiteralConstant(const MachineOperand &MO, unsigned OpSize) const;
227 bool isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
228 const MachineOperand &MO) const;
230 /// \brief Return true if this 64-bit VALU instruction has a 32-bit encoding.
231 /// This function will return false if you pass it a 32-bit instruction.
232 bool hasVALU32BitEncoding(unsigned Opcode) const;
234 /// \brief Returns true if this operand uses the constant bus.
235 bool usesConstantBus(const MachineRegisterInfo &MRI,
236 const MachineOperand &MO,
237 unsigned OpSize) const;
239 /// \brief Return true if this instruction has any modifiers.
240 /// e.g. src[012]_mod, omod, clamp.
241 bool hasModifiers(unsigned Opcode) const;
243 bool hasModifiersSet(const MachineInstr &MI,
244 unsigned OpName) const;
246 bool verifyInstruction(const MachineInstr *MI,
247 StringRef &ErrInfo) const override;
249 static unsigned getVALUOp(const MachineInstr &MI);
251 bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
253 /// \brief Return the correct register class for \p OpNo. For target-specific
254 /// instructions, this will return the register class that has been defined
255 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
256 /// the register class of its machine operand.
257 /// to infer the correct register class base on the other operands.
258 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
259 unsigned OpNo) const;
261 /// \brief Return the size in bytes of the operand OpNo on the given
262 // instruction opcode.
263 unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
264 const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
266 if (OpInfo.RegClass == -1) {
267 // If this is an immediate operand, this must be a 32-bit literal.
268 assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);
272 return RI.getRegClass(OpInfo.RegClass)->getSize();
275 /// \brief This form should usually be preferred since it handles operands
276 /// with unknown register classes.
277 unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
278 return getOpRegClass(MI, OpNo)->getSize();
281 /// \returns true if it is legal for the operand at index \p OpNo
283 bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
285 /// \brief Legalize the \p OpIndex operand of this instruction by inserting
286 /// a MOV. For example:
287 /// ADD_I32_e32 VGPR0, 15
290 /// ADD_I32_e32 VGPR0, VGPR1
292 /// If the operand being legalized is a register, then a COPY will be used
294 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
296 /// \brief Check if \p MO is a legal operand if it was the \p OpIdx Operand
298 bool isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
299 const MachineOperand *MO = nullptr) const;
301 /// \brief Legalize all operands in this instruction. This function may
302 /// create new instruction and insert them before \p MI.
303 void legalizeOperands(MachineInstr *MI) const;
305 /// \brief Split an SMRD instruction into two smaller loads of half the
306 // size storing the results in \p Lo and \p Hi.
307 void splitSMRD(MachineInstr *MI, const TargetRegisterClass *HalfRC,
308 unsigned HalfImmOp, unsigned HalfSGPROp,
309 MachineInstr *&Lo, MachineInstr *&Hi) const;
311 void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const;
313 /// \brief Replace this instruction's opcode with the equivalent VALU
314 /// opcode. This function will also move the users of \p MI to the
315 /// VALU if necessary.
316 void moveToVALU(MachineInstr &MI) const;
318 unsigned calculateIndirectAddress(unsigned RegIndex,
319 unsigned Channel) const override;
321 const TargetRegisterClass *getIndirectAddrRegClass() const override;
323 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
324 MachineBasicBlock::iterator I,
327 unsigned OffsetReg) const override;
329 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
330 MachineBasicBlock::iterator I,
333 unsigned OffsetReg) const override;
334 void reserveIndirectRegisters(BitVector &Reserved,
335 const MachineFunction &MF) const;
337 void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
338 unsigned SavReg, unsigned IndexReg) const;
340 void insertNOPs(MachineBasicBlock::iterator MI, int Count) const;
342 /// \brief Returns the operand named \p Op. If \p MI does not have an
343 /// operand named \c Op, this function returns nullptr.
344 MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
346 const MachineOperand *getNamedOperand(const MachineInstr &MI,
347 unsigned OpName) const {
348 return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
351 uint64_t getDefaultRsrcDataFormat() const;
357 int getVOPe64(uint16_t Opcode);
358 int getVOPe32(uint16_t Opcode);
359 int getCommuteRev(uint16_t Opcode);
360 int getCommuteOrig(uint16_t Opcode);
361 int getAddr64Inst(uint16_t Opcode);
362 int getAtomicRetOp(uint16_t Opcode);
363 int getAtomicNoRetOp(uint16_t Opcode);
365 const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
366 const uint64_t RSRC_TID_ENABLE = 1LL << 55;
368 } // End namespace AMDGPU
371 namespace KernelInputOffsets {
373 /// Offsets in bytes from the start of the input buffer
386 } // End namespace KernelInputOffsets
387 } // End namespace SI
389 } // End namespace llvm