1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_R600_SIINSTRINFO_H
17 #define LLVM_LIB_TARGET_R600_SIINSTRINFO_H
19 #include "AMDGPUInstrInfo.h"
20 #include "SIDefines.h"
21 #include "SIRegisterInfo.h"
25 class SIInstrInfo : public AMDGPUInstrInfo {
27 const SIRegisterInfo RI;
29 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
30 MachineRegisterInfo &MRI,
31 MachineOperand &SuperReg,
32 const TargetRegisterClass *SuperRC,
34 const TargetRegisterClass *SubRC) const;
35 MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
36 MachineRegisterInfo &MRI,
37 MachineOperand &SuperReg,
38 const TargetRegisterClass *SuperRC,
40 const TargetRegisterClass *SubRC) const;
42 unsigned split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
43 MachineBasicBlock::iterator MI,
44 MachineRegisterInfo &MRI,
45 const TargetRegisterClass *RC,
46 const MachineOperand &Op) const;
48 void swapOperands(MachineBasicBlock::iterator Inst) const;
50 void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
51 MachineInstr *Inst, unsigned Opcode) const;
53 void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
54 MachineInstr *Inst, unsigned Opcode) const;
56 void splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
57 MachineInstr *Inst) const;
58 void splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
59 MachineInstr *Inst) const;
61 bool checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
62 MachineInstr *MIb) const;
64 unsigned findUsedSGPR(const MachineInstr *MI, int OpIndices[3]) const;
67 explicit SIInstrInfo(const AMDGPUSubtarget &st);
69 const SIRegisterInfo &getRegisterInfo() const override {
73 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
74 AliasAnalysis *AA) const override;
76 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
78 int64_t &Offset2) const override;
80 bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
82 const TargetRegisterInfo *TRI) const final;
84 bool shouldClusterLoads(MachineInstr *FirstLdSt,
85 MachineInstr *SecondLdSt,
86 unsigned NumLoads) const final;
88 void copyPhysReg(MachineBasicBlock &MBB,
89 MachineBasicBlock::iterator MI, DebugLoc DL,
90 unsigned DestReg, unsigned SrcReg,
91 bool KillSrc) const override;
93 unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB,
94 MachineBasicBlock::iterator MI,
100 void storeRegToStackSlot(MachineBasicBlock &MBB,
101 MachineBasicBlock::iterator MI,
102 unsigned SrcReg, bool isKill, int FrameIndex,
103 const TargetRegisterClass *RC,
104 const TargetRegisterInfo *TRI) const override;
106 void loadRegFromStackSlot(MachineBasicBlock &MBB,
107 MachineBasicBlock::iterator MI,
108 unsigned DestReg, int FrameIndex,
109 const TargetRegisterClass *RC,
110 const TargetRegisterInfo *TRI) const override;
112 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
114 // \brief Returns an opcode that can be used to move a value to a \p DstRC
115 // register. If there is no hardware instruction that can store to \p
116 // DstRC, then AMDGPU::COPY is returned.
117 unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
118 int commuteOpcode(const MachineInstr &MI) const;
120 MachineInstr *commuteInstruction(MachineInstr *MI,
121 bool NewMI = false) const override;
122 bool findCommutedOpIndices(MachineInstr *MI,
124 unsigned &SrcOpIdx2) const override;
126 bool areMemAccessesTriviallyDisjoint(
127 MachineInstr *MIa, MachineInstr *MIb,
128 AliasAnalysis *AA = nullptr) const override;
130 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
131 MachineBasicBlock::iterator I,
132 unsigned DstReg, unsigned SrcReg) const override;
133 bool isMov(unsigned Opcode) const override;
135 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
137 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
138 unsigned Reg, MachineRegisterInfo *MRI) const final;
140 unsigned getMachineCSELookAheadLimit() const override { return 500; }
142 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MBB,
143 MachineBasicBlock::iterator &MI,
144 LiveVariables *LV) const override;
146 bool isSALU(uint16_t Opcode) const {
147 return get(Opcode).TSFlags & SIInstrFlags::SALU;
150 bool isVALU(uint16_t Opcode) const {
151 return get(Opcode).TSFlags & SIInstrFlags::VALU;
154 bool isSOP1(uint16_t Opcode) const {
155 return get(Opcode).TSFlags & SIInstrFlags::SOP1;
158 bool isSOP2(uint16_t Opcode) const {
159 return get(Opcode).TSFlags & SIInstrFlags::SOP2;
162 bool isSOPC(uint16_t Opcode) const {
163 return get(Opcode).TSFlags & SIInstrFlags::SOPC;
166 bool isSOPK(uint16_t Opcode) const {
167 return get(Opcode).TSFlags & SIInstrFlags::SOPK;
170 bool isSOPP(uint16_t Opcode) const {
171 return get(Opcode).TSFlags & SIInstrFlags::SOPP;
174 bool isVOP1(uint16_t Opcode) const {
175 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
178 bool isVOP2(uint16_t Opcode) const {
179 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
182 bool isVOP3(uint16_t Opcode) const {
183 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
186 bool isVOPC(uint16_t Opcode) const {
187 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
190 bool isMUBUF(uint16_t Opcode) const {
191 return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
194 bool isMTBUF(uint16_t Opcode) const {
195 return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
198 bool isSMRD(uint16_t Opcode) const {
199 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
202 bool isDS(uint16_t Opcode) const {
203 return get(Opcode).TSFlags & SIInstrFlags::DS;
206 bool isMIMG(uint16_t Opcode) const {
207 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
210 bool isFLAT(uint16_t Opcode) const {
211 return get(Opcode).TSFlags & SIInstrFlags::FLAT;
214 bool isWQM(uint16_t Opcode) const {
215 return get(Opcode).TSFlags & SIInstrFlags::WQM;
218 bool isVGPRSpill(uint16_t Opcode) const {
219 return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
222 bool isInlineConstant(const APInt &Imm) const;
223 bool isInlineConstant(const MachineOperand &MO, unsigned OpSize) const;
224 bool isLiteralConstant(const MachineOperand &MO, unsigned OpSize) const;
226 bool isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
227 const MachineOperand &MO) const;
229 /// \brief Return true if this 64-bit VALU instruction has a 32-bit encoding.
230 /// This function will return false if you pass it a 32-bit instruction.
231 bool hasVALU32BitEncoding(unsigned Opcode) const;
233 /// \brief Returns true if this operand uses the constant bus.
234 bool usesConstantBus(const MachineRegisterInfo &MRI,
235 const MachineOperand &MO,
236 unsigned OpSize) const;
238 /// \brief Return true if this instruction has any modifiers.
239 /// e.g. src[012]_mod, omod, clamp.
240 bool hasModifiers(unsigned Opcode) const;
242 bool hasModifiersSet(const MachineInstr &MI,
243 unsigned OpName) const;
245 bool verifyInstruction(const MachineInstr *MI,
246 StringRef &ErrInfo) const override;
248 static unsigned getVALUOp(const MachineInstr &MI);
250 bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
252 /// \brief Return the correct register class for \p OpNo. For target-specific
253 /// instructions, this will return the register class that has been defined
254 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
255 /// the register class of its machine operand.
256 /// to infer the correct register class base on the other operands.
257 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
258 unsigned OpNo) const;
260 /// \brief Return the size in bytes of the operand OpNo on the given
261 // instruction opcode.
262 unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
263 const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
265 if (OpInfo.RegClass == -1) {
266 // If this is an immediate operand, this must be a 32-bit literal.
267 assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);
271 return RI.getRegClass(OpInfo.RegClass)->getSize();
274 /// \brief This form should usually be preferred since it handles operands
275 /// with unknown register classes.
276 unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
277 return getOpRegClass(MI, OpNo)->getSize();
280 /// \returns true if it is legal for the operand at index \p OpNo
282 bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
284 /// \brief Legalize the \p OpIndex operand of this instruction by inserting
285 /// a MOV. For example:
286 /// ADD_I32_e32 VGPR0, 15
289 /// ADD_I32_e32 VGPR0, VGPR1
291 /// If the operand being legalized is a register, then a COPY will be used
293 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
295 /// \brief Check if \p MO is a legal operand if it was the \p OpIdx Operand
297 bool isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
298 const MachineOperand *MO = nullptr) const;
300 /// \brief Legalize all operands in this instruction. This function may
301 /// create new instruction and insert them before \p MI.
302 void legalizeOperands(MachineInstr *MI) const;
304 /// \brief Split an SMRD instruction into two smaller loads of half the
305 // size storing the results in \p Lo and \p Hi.
306 void splitSMRD(MachineInstr *MI, const TargetRegisterClass *HalfRC,
307 unsigned HalfImmOp, unsigned HalfSGPROp,
308 MachineInstr *&Lo, MachineInstr *&Hi) const;
310 void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const;
312 /// \brief Replace this instruction's opcode with the equivalent VALU
313 /// opcode. This function will also move the users of \p MI to the
314 /// VALU if necessary.
315 void moveToVALU(MachineInstr &MI) const;
317 unsigned calculateIndirectAddress(unsigned RegIndex,
318 unsigned Channel) const override;
320 const TargetRegisterClass *getIndirectAddrRegClass() const override;
322 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
323 MachineBasicBlock::iterator I,
326 unsigned OffsetReg) const override;
328 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
329 MachineBasicBlock::iterator I,
332 unsigned OffsetReg) const override;
333 void reserveIndirectRegisters(BitVector &Reserved,
334 const MachineFunction &MF) const;
336 void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
337 unsigned SavReg, unsigned IndexReg) const;
339 void insertNOPs(MachineBasicBlock::iterator MI, int Count) const;
341 /// \brief Returns the operand named \p Op. If \p MI does not have an
342 /// operand named \c Op, this function returns nullptr.
343 MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
345 const MachineOperand *getNamedOperand(const MachineInstr &MI,
346 unsigned OpName) const {
347 return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
350 uint64_t getDefaultRsrcDataFormat() const;
356 int getVOPe64(uint16_t Opcode);
357 int getVOPe32(uint16_t Opcode);
358 int getCommuteRev(uint16_t Opcode);
359 int getCommuteOrig(uint16_t Opcode);
360 int getAddr64Inst(uint16_t Opcode);
361 int getAtomicRetOp(uint16_t Opcode);
362 int getAtomicNoRetOp(uint16_t Opcode);
364 const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
365 const uint64_t RSRC_TID_ENABLE = 1LL << 55;
367 } // End namespace AMDGPU
370 namespace KernelInputOffsets {
372 /// Offsets in bytes from the start of the input buffer
385 } // End namespace KernelInputOffsets
386 } // End namespace SI
388 } // End namespace llvm