1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 def isCI : Predicate<"Subtarget->getGeneration() "
10 ">= AMDGPUSubtarget::SEA_ISLANDS">;
11 def isCIOnly : Predicate<"Subtarget->getGeneration() =="
12 "AMDGPUSubtarget::SEA_ISLANDS">,
13 AssemblerPredicate <"FeatureSeaIslands">;
15 def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">;
22 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
23 field bits<8> SI = si;
24 field bits<8> VI = vi;
26 field bits<9> SI3 = {0, si{7-0}};
27 field bits<10> VI3 = {0, 0, vi{7-0}};
30 class vop1 <bits<8> si, bits<8> vi = si> : vop {
31 field bits<8> SI = si;
32 field bits<8> VI = vi;
34 field bits<9> SI3 = {1, 1, si{6-0}};
35 field bits<10> VI3 = !add(0x140, vi);
38 class vop2 <bits<6> si, bits<6> vi = si> : vop {
39 field bits<6> SI = si;
40 field bits<6> VI = vi;
42 field bits<9> SI3 = {1, 0, 0, si{5-0}};
43 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
46 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
47 // that doesn't have VOP2 encoding on VI
48 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
52 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
57 class sop1 <bits<8> si, bits<8> vi = si> {
58 field bits<8> SI = si;
59 field bits<8> VI = vi;
62 class sop2 <bits<7> si, bits<7> vi = si> {
63 field bits<7> SI = si;
64 field bits<7> VI = vi;
67 class sopk <bits<5> si, bits<5> vi = si> {
68 field bits<5> SI = si;
69 field bits<5> VI = vi;
72 // Specify an SMRD opcode for SI and SMEM opcode for VI
74 // FIXME: This should really be bits<5> si, Tablegen crashes if
75 // parameter default value is other parameter with different bit size
76 class smrd<bits<8> si, bits<8> vi = si> {
77 field bits<5> SI = si{4-0};
78 field bits<8> VI = vi;
81 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
82 // in AMDGPUInstrInfo.cpp
89 //===----------------------------------------------------------------------===//
91 //===----------------------------------------------------------------------===//
93 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
94 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
95 [SDNPMayLoad, SDNPMemOperand]
98 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
100 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
101 SDTCisVT<1, iAny>, // vdata(VGPR)
102 SDTCisVT<2, i32>, // num_channels(imm)
103 SDTCisVT<3, i32>, // vaddr(VGPR)
104 SDTCisVT<4, i32>, // soffset(SGPR)
105 SDTCisVT<5, i32>, // inst_offset(imm)
106 SDTCisVT<6, i32>, // dfmt(imm)
107 SDTCisVT<7, i32>, // nfmt(imm)
108 SDTCisVT<8, i32>, // offen(imm)
109 SDTCisVT<9, i32>, // idxen(imm)
110 SDTCisVT<10, i32>, // glc(imm)
111 SDTCisVT<11, i32>, // slc(imm)
112 SDTCisVT<12, i32> // tfe(imm)
114 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
117 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
118 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
122 class SDSample<string opcode> : SDNode <opcode,
123 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
124 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
127 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
128 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
129 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
130 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
132 def SIconstdata_ptr : SDNode<
133 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 1, [SDTCisVT<0, i64>,
137 def mubuf_load : PatFrag <(ops node:$ptr), (load node:$ptr), [{
138 return isGlobalLoad(cast<LoadSDNode>(N)) ||
139 isConstantLoad(cast<LoadSDNode>(N), -1);
142 def smrd_load : PatFrag <(ops node:$ptr), (load node:$ptr), [{
143 return isConstantLoad(cast<LoadSDNode>(N), -1) &&
144 static_cast<const SITargetLowering *>(getTargetLowering())->isMemOpUniform(N);
147 //===----------------------------------------------------------------------===//
148 // SDNodes and PatFrag for local loads and stores to enable s_mov_b32 m0, -1
149 // to be glued to the memory instructions.
150 //===----------------------------------------------------------------------===//
152 def SIld_local : SDNode <"ISD::LOAD", SDTLoad,
153 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
156 def si_ld_local : PatFrag <(ops node:$ptr), (SIld_local node:$ptr), [{
157 return isLocalLoad(cast<LoadSDNode>(N));
160 def si_load_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{
161 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
162 cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
165 def si_load_local_align8 : Aligned8Bytes <
166 (ops node:$ptr), (si_load_local node:$ptr)
169 def si_sextload_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{
170 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
172 def si_az_extload_local : AZExtLoadBase <si_ld_local>;
174 multiclass SIExtLoadLocal <PatFrag ld_node> {
176 def _i8 : PatFrag <(ops node:$ptr), (ld_node node:$ptr),
177 [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;}]
180 def _i16 : PatFrag <(ops node:$ptr), (ld_node node:$ptr),
181 [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;}]
185 defm si_sextload_local : SIExtLoadLocal <si_sextload_local>;
186 defm si_az_extload_local : SIExtLoadLocal <si_az_extload_local>;
188 def SIst_local : SDNode <"ISD::STORE", SDTStore,
189 [SDNPHasChain, SDNPMayStore, SDNPMemOperand, SDNPInGlue]
192 def si_st_local : PatFrag <
193 (ops node:$val, node:$ptr), (SIst_local node:$val, node:$ptr), [{
194 return isLocalStore(cast<StoreSDNode>(N));
197 def si_store_local : PatFrag <
198 (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{
199 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
200 !cast<StoreSDNode>(N)->isTruncatingStore();
203 def si_store_local_align8 : Aligned8Bytes <
204 (ops node:$val, node:$ptr), (si_store_local node:$val, node:$ptr)
207 def si_truncstore_local : PatFrag <
208 (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{
209 return cast<StoreSDNode>(N)->isTruncatingStore();
212 def si_truncstore_local_i8 : PatFrag <
213 (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{
214 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
217 def si_truncstore_local_i16 : PatFrag <
218 (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{
219 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
222 multiclass SIAtomicM0Glue2 <string op_name> {
224 def _glue : SDNode <"ISD::ATOMIC_"#op_name, SDTAtomic2,
225 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
228 def _local : local_binary_atomic_op <!cast<SDNode>(NAME#"_glue")>;
231 defm si_atomic_load_add : SIAtomicM0Glue2 <"LOAD_ADD">;
232 defm si_atomic_load_and : SIAtomicM0Glue2 <"LOAD_AND">;
233 defm si_atomic_load_min : SIAtomicM0Glue2 <"LOAD_MIN">;
234 defm si_atomic_load_max : SIAtomicM0Glue2 <"LOAD_MAX">;
235 defm si_atomic_load_or : SIAtomicM0Glue2 <"LOAD_OR">;
236 defm si_atomic_load_sub : SIAtomicM0Glue2 <"LOAD_SUB">;
237 defm si_atomic_load_xor : SIAtomicM0Glue2 <"LOAD_XOR">;
238 defm si_atomic_load_umin : SIAtomicM0Glue2 <"LOAD_UMIN">;
239 defm si_atomic_load_umax : SIAtomicM0Glue2 <"LOAD_UMAX">;
240 defm si_atomic_swap : SIAtomicM0Glue2 <"SWAP">;
242 def si_atomic_cmp_swap_glue : SDNode <"ISD::ATOMIC_CMP_SWAP", SDTAtomic3,
243 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
246 defm si_atomic_cmp_swap : AtomicCmpSwapLocal <si_atomic_cmp_swap_glue>;
248 // Transformation function, extract the lower 32bit of a 64bit immediate
249 def LO32 : SDNodeXForm<imm, [{
250 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, SDLoc(N),
254 def LO32f : SDNodeXForm<fpimm, [{
255 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
256 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
259 // Transformation function, extract the upper 32bit of a 64bit immediate
260 def HI32 : SDNodeXForm<imm, [{
261 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, SDLoc(N), MVT::i32);
264 def HI32f : SDNodeXForm<fpimm, [{
265 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
266 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), SDLoc(N),
270 def IMM8bitDWORD : PatLeaf <(imm),
271 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
274 def as_dword_i32imm : SDNodeXForm<imm, [{
275 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, SDLoc(N), MVT::i32);
278 def as_i1imm : SDNodeXForm<imm, [{
279 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i1);
282 def as_i8imm : SDNodeXForm<imm, [{
283 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i8);
286 def as_i16imm : SDNodeXForm<imm, [{
287 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
290 def as_i32imm: SDNodeXForm<imm, [{
291 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
294 def as_i64imm: SDNodeXForm<imm, [{
295 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
298 // Copied from the AArch64 backend:
299 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
300 return CurDAG->getTargetConstant(
301 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
304 // Copied from the AArch64 backend:
305 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
306 return CurDAG->getTargetConstant(
307 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
310 def IMM8bit : PatLeaf <(imm),
311 [{return isUInt<8>(N->getZExtValue());}]
314 def IMM12bit : PatLeaf <(imm),
315 [{return isUInt<12>(N->getZExtValue());}]
318 def IMM16bit : PatLeaf <(imm),
319 [{return isUInt<16>(N->getZExtValue());}]
322 def IMM20bit : PatLeaf <(imm),
323 [{return isUInt<20>(N->getZExtValue());}]
326 def IMM32bit : PatLeaf <(imm),
327 [{return isUInt<32>(N->getZExtValue());}]
330 def mubuf_vaddr_offset : PatFrag<
331 (ops node:$ptr, node:$offset, node:$imm_offset),
332 (add (add node:$ptr, node:$offset), node:$imm_offset)
335 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
336 return isInlineImmediate(N);
339 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
340 return isInlineImmediate(N);
343 class SGPRImm <dag frag> : PatLeaf<frag, [{
344 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
347 const SIRegisterInfo *SIRI =
348 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
349 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
351 const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());
352 if (RC && SIRI->isSGPRClass(RC))
358 //===----------------------------------------------------------------------===//
360 //===----------------------------------------------------------------------===//
362 def FRAMEri32 : Operand<iPTR> {
363 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
366 def SoppBrTarget : AsmOperandClass {
367 let Name = "SoppBrTarget";
368 let ParserMethod = "parseSOppBrTarget";
371 def sopp_brtarget : Operand<OtherVT> {
372 let EncoderMethod = "getSOPPBrEncoding";
373 let OperandType = "OPERAND_PCREL";
374 let ParserMatchClass = SoppBrTarget;
377 def const_ga : Operand<iPTR>;
379 include "SIInstrFormats.td"
380 include "VIInstrFormats.td"
382 def MubufOffsetMatchClass : AsmOperandClass {
383 let Name = "MubufOffset";
384 let ParserMethod = "parseMubufOptionalOps";
385 let RenderMethod = "addImmOperands";
388 class DSOffsetBaseMatchClass <string parser> : AsmOperandClass {
389 let Name = "DSOffset"#parser;
390 let ParserMethod = parser;
391 let RenderMethod = "addImmOperands";
392 let PredicateMethod = "isDSOffset";
395 def DSOffsetMatchClass : DSOffsetBaseMatchClass <"parseDSOptionalOps">;
396 def DSOffsetGDSMatchClass : DSOffsetBaseMatchClass <"parseDSOffsetOptional">;
398 def DSOffset01MatchClass : AsmOperandClass {
399 let Name = "DSOffset1";
400 let ParserMethod = "parseDSOff01OptionalOps";
401 let RenderMethod = "addImmOperands";
402 let PredicateMethod = "isDSOffset01";
405 class GDSBaseMatchClass <string parser> : AsmOperandClass {
406 let Name = "GDS"#parser;
407 let PredicateMethod = "isImm";
408 let ParserMethod = parser;
409 let RenderMethod = "addImmOperands";
412 def GDSMatchClass : GDSBaseMatchClass <"parseDSOptionalOps">;
413 def GDS01MatchClass : GDSBaseMatchClass <"parseDSOff01OptionalOps">;
415 class GLCBaseMatchClass <string parser> : AsmOperandClass {
416 let Name = "GLC"#parser;
417 let PredicateMethod = "isImm";
418 let ParserMethod = parser;
419 let RenderMethod = "addImmOperands";
422 def GLCMubufMatchClass : GLCBaseMatchClass <"parseMubufOptionalOps">;
423 def GLCFlatMatchClass : GLCBaseMatchClass <"parseFlatOptionalOps">;
425 class SLCBaseMatchClass <string parser> : AsmOperandClass {
426 let Name = "SLC"#parser;
427 let PredicateMethod = "isImm";
428 let ParserMethod = parser;
429 let RenderMethod = "addImmOperands";
432 def SLCMubufMatchClass : SLCBaseMatchClass <"parseMubufOptionalOps">;
433 def SLCFlatMatchClass : SLCBaseMatchClass <"parseFlatOptionalOps">;
434 def SLCFlatAtomicMatchClass : SLCBaseMatchClass <"parseFlatAtomicOptionalOps">;
436 class TFEBaseMatchClass <string parser> : AsmOperandClass {
437 let Name = "TFE"#parser;
438 let PredicateMethod = "isImm";
439 let ParserMethod = parser;
440 let RenderMethod = "addImmOperands";
443 def TFEMubufMatchClass : TFEBaseMatchClass <"parseMubufOptionalOps">;
444 def TFEFlatMatchClass : TFEBaseMatchClass <"parseFlatOptionalOps">;
445 def TFEFlatAtomicMatchClass : TFEBaseMatchClass <"parseFlatAtomicOptionalOps">;
447 def OModMatchClass : AsmOperandClass {
449 let PredicateMethod = "isImm";
450 let ParserMethod = "parseVOP3OptionalOps";
451 let RenderMethod = "addImmOperands";
454 def ClampMatchClass : AsmOperandClass {
456 let PredicateMethod = "isImm";
457 let ParserMethod = "parseVOP3OptionalOps";
458 let RenderMethod = "addImmOperands";
461 class SMRDOffsetBaseMatchClass <string predicate> : AsmOperandClass {
462 let Name = "SMRDOffset"#predicate;
463 let PredicateMethod = predicate;
464 let RenderMethod = "addImmOperands";
467 def SMRDOffsetMatchClass : SMRDOffsetBaseMatchClass <"isSMRDOffset">;
468 def SMRDLiteralOffsetMatchClass : SMRDOffsetBaseMatchClass <
469 "isSMRDLiteralOffset"
472 let OperandType = "OPERAND_IMMEDIATE" in {
474 def offen : Operand<i1> {
475 let PrintMethod = "printOffen";
477 def idxen : Operand<i1> {
478 let PrintMethod = "printIdxen";
480 def addr64 : Operand<i1> {
481 let PrintMethod = "printAddr64";
483 def mbuf_offset : Operand<i16> {
484 let PrintMethod = "printMBUFOffset";
485 let ParserMatchClass = MubufOffsetMatchClass;
487 class ds_offset_base <AsmOperandClass mc> : Operand<i16> {
488 let PrintMethod = "printDSOffset";
489 let ParserMatchClass = mc;
491 def ds_offset : ds_offset_base <DSOffsetMatchClass>;
492 def ds_offset_gds : ds_offset_base <DSOffsetGDSMatchClass>;
494 def ds_offset0 : Operand<i8> {
495 let PrintMethod = "printDSOffset0";
496 let ParserMatchClass = DSOffset01MatchClass;
498 def ds_offset1 : Operand<i8> {
499 let PrintMethod = "printDSOffset1";
500 let ParserMatchClass = DSOffset01MatchClass;
502 class gds_base <AsmOperandClass mc> : Operand <i1> {
503 let PrintMethod = "printGDS";
504 let ParserMatchClass = mc;
506 def gds : gds_base <GDSMatchClass>;
508 def gds01 : gds_base <GDS01MatchClass>;
510 class glc_base <AsmOperandClass mc> : Operand <i1> {
511 let PrintMethod = "printGLC";
512 let ParserMatchClass = mc;
515 def glc : glc_base <GLCMubufMatchClass>;
516 def glc_flat : glc_base <GLCFlatMatchClass>;
518 class slc_base <AsmOperandClass mc> : Operand <i1> {
519 let PrintMethod = "printSLC";
520 let ParserMatchClass = mc;
523 def slc : slc_base <SLCMubufMatchClass>;
524 def slc_flat : slc_base <SLCFlatMatchClass>;
525 def slc_flat_atomic : slc_base <SLCFlatAtomicMatchClass>;
527 class tfe_base <AsmOperandClass mc> : Operand <i1> {
528 let PrintMethod = "printTFE";
529 let ParserMatchClass = mc;
532 def tfe : tfe_base <TFEMubufMatchClass>;
533 def tfe_flat : tfe_base <TFEFlatMatchClass>;
534 def tfe_flat_atomic : tfe_base <TFEFlatAtomicMatchClass>;
536 def omod : Operand <i32> {
537 let PrintMethod = "printOModSI";
538 let ParserMatchClass = OModMatchClass;
541 def ClampMod : Operand <i1> {
542 let PrintMethod = "printClampSI";
543 let ParserMatchClass = ClampMatchClass;
546 def smrd_offset : Operand <i32> {
547 let PrintMethod = "printU32ImmOperand";
548 let ParserMatchClass = SMRDOffsetMatchClass;
551 def smrd_literal_offset : Operand <i32> {
552 let PrintMethod = "printU32ImmOperand";
553 let ParserMatchClass = SMRDLiteralOffsetMatchClass;
556 } // End OperandType = "OPERAND_IMMEDIATE"
558 def VOPDstS64 : VOPDstOperand <SReg_64>;
560 //===----------------------------------------------------------------------===//
562 //===----------------------------------------------------------------------===//
564 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
565 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
567 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
568 def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">;
569 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
570 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
571 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
572 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
574 def SMRDImm : ComplexPattern<i64, 2, "SelectSMRDImm">;
575 def SMRDImm32 : ComplexPattern<i64, 2, "SelectSMRDImm32">;
576 def SMRDSgpr : ComplexPattern<i64, 2, "SelectSMRDSgpr">;
577 def SMRDBufferImm : ComplexPattern<i32, 1, "SelectSMRDBufferImm">;
578 def SMRDBufferImm32 : ComplexPattern<i32, 1, "SelectSMRDBufferImm32">;
579 def SMRDBufferSgpr : ComplexPattern<i32, 1, "SelectSMRDBufferSgpr">;
581 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
582 def VOP3NoMods0 : ComplexPattern<untyped, 4, "SelectVOP3NoMods0">;
583 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
584 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
585 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
586 def VOP3NoMods : ComplexPattern<untyped, 2, "SelectVOP3NoMods">;
588 //===----------------------------------------------------------------------===//
589 // SI assembler operands
590 //===----------------------------------------------------------------------===//
611 //===----------------------------------------------------------------------===//
613 // SI Instruction multiclass helpers.
615 // Instructions with _32 take 32-bit operands.
616 // Instructions with _64 take 64-bit operands.
618 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
619 // encoding is the standard encoding, but instruction that make use of
620 // any of the instruction modifiers must use the 64-bit encoding.
622 // Instructions with _e32 use the 32-bit encoding.
623 // Instructions with _e64 use the 64-bit encoding.
625 //===----------------------------------------------------------------------===//
627 class SIMCInstr <string pseudo, int subtarget> {
628 string PseudoInstr = pseudo;
629 int Subtarget = subtarget;
632 //===----------------------------------------------------------------------===//
634 //===----------------------------------------------------------------------===//
636 class EXPCommon : InstSI<
638 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
639 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
640 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
649 let isPseudo = 1, isCodeGenOnly = 1 in {
650 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
653 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
655 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
658 //===----------------------------------------------------------------------===//
660 //===----------------------------------------------------------------------===//
662 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
663 SOP1 <outs, ins, "", pattern>,
664 SIMCInstr<opName, SISubtarget.NONE> {
666 let isCodeGenOnly = 1;
669 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
670 SOP1 <outs, ins, asm, []>,
672 SIMCInstr<opName, SISubtarget.SI> {
673 let isCodeGenOnly = 0;
674 let AssemblerPredicates = [isSICI];
677 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
678 SOP1 <outs, ins, asm, []>,
680 SIMCInstr<opName, SISubtarget.VI> {
681 let isCodeGenOnly = 0;
682 let AssemblerPredicates = [isVI];
685 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
688 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
690 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
692 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
696 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
697 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
698 opName#" $dst, $src0", pattern
701 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
702 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
703 opName#" $dst, $src0", pattern
706 // no input, 64-bit output.
707 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
708 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
710 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
715 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
721 // 64-bit input, no output
722 multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
723 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
725 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
730 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
736 // 64-bit input, 32-bit output.
737 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
738 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
739 opName#" $dst, $src0", pattern
742 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
743 SOP2<outs, ins, "", pattern>,
744 SIMCInstr<opName, SISubtarget.NONE> {
746 let isCodeGenOnly = 1;
749 // Pseudo instructions have no encodings, but adding this field here allows
751 // let sdst = xxx in {
752 // for multiclasses that include both real and pseudo instructions.
753 field bits<7> sdst = 0;
756 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
757 SOP2<outs, ins, asm, []>,
759 SIMCInstr<opName, SISubtarget.SI> {
760 let AssemblerPredicates = [isSICI];
763 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
764 SOP2<outs, ins, asm, []>,
766 SIMCInstr<opName, SISubtarget.VI> {
767 let AssemblerPredicates = [isVI];
770 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
773 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
775 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
777 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
781 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
782 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
783 opName#" $dst, $src0, $src1", pattern
786 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
787 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
788 opName#" $dst, $src0, $src1", pattern
791 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
792 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
793 opName#" $dst, $src0, $src1", pattern
796 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
797 string opName, PatLeaf cond> : SOPC <
798 op, (outs), (ins rc:$src0, rc:$src1),
799 opName#" $src0, $src1", []> {
803 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
804 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
806 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
807 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
809 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
810 SOPK <outs, ins, "", pattern>,
811 SIMCInstr<opName, SISubtarget.NONE> {
813 let isCodeGenOnly = 1;
816 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
817 SOPK <outs, ins, asm, []>,
819 SIMCInstr<opName, SISubtarget.SI> {
820 let AssemblerPredicates = [isSICI];
821 let isCodeGenOnly = 0;
824 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
825 SOPK <outs, ins, asm, []>,
827 SIMCInstr<opName, SISubtarget.VI> {
828 let AssemblerPredicates = [isVI];
829 let isCodeGenOnly = 0;
832 multiclass SOPK_m <sopk op, string opName, dag outs, dag ins, string opAsm,
833 string asm = opName#opAsm> {
834 def "" : SOPK_Pseudo <opName, outs, ins, []>;
836 def _si : SOPK_Real_si <op, opName, outs, ins, asm>;
838 def _vi : SOPK_Real_vi <op, opName, outs, ins, asm>;
842 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
843 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
846 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
847 opName#" $dst, $src0">;
849 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
850 opName#" $dst, $src0">;
853 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
854 def "" : SOPK_Pseudo <opName, (outs),
855 (ins SReg_32:$src0, u16imm:$src1), pattern> {
860 def _si : SOPK_Real_si <op, opName, (outs),
861 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16"> {
865 def _vi : SOPK_Real_vi <op, opName, (outs),
866 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16"> {
871 multiclass SOPK_32TIE <sopk op, string opName, list<dag> pattern> : SOPK_m <
872 op, opName, (outs SReg_32:$sdst), (ins SReg_32:$src0, u16imm:$simm16),
876 multiclass SOPK_IMM32 <sopk op, string opName, dag outs, dag ins,
877 string argAsm, string asm = opName#argAsm> {
879 def "" : SOPK_Pseudo <opName, outs, ins, []>;
881 def _si : SOPK <outs, ins, asm, []>,
883 SIMCInstr<opName, SISubtarget.SI> {
884 let AssemblerPredicates = [isSICI];
885 let isCodeGenOnly = 0;
888 def _vi : SOPK <outs, ins, asm, []>,
890 SIMCInstr<opName, SISubtarget.VI> {
891 let AssemblerPredicates = [isVI];
892 let isCodeGenOnly = 0;
895 //===----------------------------------------------------------------------===//
897 //===----------------------------------------------------------------------===//
899 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
900 SMRD <outs, ins, "", pattern>,
901 SIMCInstr<opName, SISubtarget.NONE> {
903 let isCodeGenOnly = 1;
906 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
908 SMRD <outs, ins, asm, []>,
910 SIMCInstr<opName, SISubtarget.SI> {
911 let AssemblerPredicates = [isSICI];
914 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
915 string asm, list<dag> pattern = []> :
916 SMRD <outs, ins, asm, pattern>,
918 SIMCInstr<opName, SISubtarget.VI> {
919 let AssemblerPredicates = [isVI];
922 multiclass SMRD_m <smrd op, string opName, bit imm, dag outs, dag ins,
923 string asm, list<dag> pattern> {
925 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
927 def _si : SMRD_Real_si <op.SI, opName, imm, outs, ins, asm>;
929 // glc is only applicable to scalar stores, which are not yet
932 def _vi : SMRD_Real_vi <op.VI, opName, imm, outs, ins, asm>;
936 multiclass SMRD_Inval <smrd op, string opName,
937 SDPatternOperator node> {
938 let hasSideEffects = 1, mayStore = 1 in {
939 def "" : SMRD_Pseudo <opName, (outs), (ins), [(node)]>;
941 let sbase = 0, offset = 0 in {
943 def _si : SMRD_Real_si <op.SI, opName, 0, (outs), (ins), opName>;
946 let glc = 0, sdata = 0 in {
947 def _vi : SMRD_Real_vi <op.VI, opName, 0, (outs), (ins), opName>;
953 class SMEM_Inval <bits<8> op, string opName, SDPatternOperator node> :
954 SMRD_Real_vi<op, opName, 0, (outs), (ins), opName, [(node)]> {
955 let hasSideEffects = 1;
963 multiclass SMRD_Helper <smrd op, string opName, RegisterClass baseClass,
964 RegisterClass dstClass> {
966 op, opName#"_IMM", 1, (outs dstClass:$dst),
967 (ins baseClass:$sbase, smrd_offset:$offset),
968 opName#" $dst, $sbase, $offset", []
972 (outs dstClass:$dst), (ins baseClass:$sbase, smrd_literal_offset:$offset),
973 opName#" $dst, $sbase, $offset", []>, SMRD_IMMe_ci <op.SI> {
974 let AssemblerPredicates = [isCIOnly];
977 defm _SGPR : SMRD_m <
978 op, opName#"_SGPR", 0, (outs dstClass:$dst),
979 (ins baseClass:$sbase, SReg_32:$soff),
980 opName#" $dst, $sbase, $soff", []
984 //===----------------------------------------------------------------------===//
985 // Vector ALU classes
986 //===----------------------------------------------------------------------===//
988 // This must always be right before the operand being input modified.
989 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
990 let PrintMethod = "printOperandAndMods";
993 def InputModsMatchClass : AsmOperandClass {
994 let Name = "RegWithInputMods";
997 def InputModsNoDefault : Operand <i32> {
998 let PrintMethod = "printOperandAndMods";
999 let ParserMatchClass = InputModsMatchClass;
1002 class getNumSrcArgs<ValueType Src0, ValueType Src1, ValueType Src2> {
1004 !if (!eq(Src0.Value, untyped.Value), 0,
1005 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
1006 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
1010 // Returns the register class to use for the destination of VOP[123C]
1011 // instructions for the given VT.
1012 class getVALUDstForVT<ValueType VT> {
1013 RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
1014 !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
1015 !if(!eq(VT.Size, 16), VOPDstOperand<VGPR_32>,
1016 VOPDstOperand<SReg_64>))); // else VT == i1
1019 // Returns the register class to use for source 0 of VOP[12C]
1020 // instructions for the given VT.
1021 class getVOPSrc0ForVT<ValueType VT> {
1022 RegisterOperand ret = !if(!eq(VT.Size, 64), VSrc_64, VSrc_32);
1025 // Returns the register class to use for source 1 of VOP[12C] for the
1027 class getVOPSrc1ForVT<ValueType VT> {
1028 RegisterClass ret = !if(!eq(VT.Size, 64), VReg_64, VGPR_32);
1031 // Returns the register class to use for sources of VOP3 instructions for the
1033 class getVOP3SrcForVT<ValueType VT> {
1034 RegisterOperand ret =
1035 !if(!eq(VT.Size, 64),
1037 !if(!eq(VT.Value, i1.Value),
1044 // Returns 1 if the source arguments have modifiers, 0 if they do not.
1045 // XXX - do f16 instructions?
1046 class hasModifiers<ValueType SrcVT> {
1047 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
1048 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
1051 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
1052 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
1053 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
1054 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1058 // Returns the input arguments for VOP3 instructions for the given SrcVT.
1059 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
1060 RegisterOperand Src2RC, int NumSrcArgs,
1064 !if (!eq(NumSrcArgs, 1),
1065 !if (!eq(HasModifiers, 1),
1066 // VOP1 with modifiers
1067 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
1068 ClampMod:$clamp, omod:$omod)
1070 // VOP1 without modifiers
1073 !if (!eq(NumSrcArgs, 2),
1074 !if (!eq(HasModifiers, 1),
1075 // VOP 2 with modifiers
1076 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
1077 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
1078 ClampMod:$clamp, omod:$omod)
1080 // VOP2 without modifiers
1081 (ins Src0RC:$src0, Src1RC:$src1)
1083 /* NumSrcArgs == 3 */,
1084 !if (!eq(HasModifiers, 1),
1085 // VOP3 with modifiers
1086 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
1087 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
1088 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
1089 ClampMod:$clamp, omod:$omod)
1091 // VOP3 without modifiers
1092 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
1096 // Returns the assembly string for the inputs and outputs of a VOP[12C]
1097 // instruction. This does not add the _e32 suffix, so it can be reused
1099 class getAsm32 <bit HasDst, int NumSrcArgs> {
1100 string dst = "$dst";
1101 string src0 = ", $src0";
1102 string src1 = ", $src1";
1103 string src2 = ", $src2";
1104 string ret = !if(HasDst, dst, "") #
1105 !if(!eq(NumSrcArgs, 1), src0, "") #
1106 !if(!eq(NumSrcArgs, 2), src0#src1, "") #
1107 !if(!eq(NumSrcArgs, 3), src0#src1#src2, "");
1110 // Returns the assembly string for the inputs and outputs of a VOP3
1112 class getAsm64 <bit HasDst, int NumSrcArgs, bit HasModifiers> {
1113 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
1114 string src1 = !if(!eq(NumSrcArgs, 1), "",
1115 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
1116 " $src1_modifiers,"));
1117 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
1119 !if(!eq(HasModifiers, 0),
1120 getAsm32<HasDst, NumSrcArgs>.ret,
1121 "$dst, "#src0#src1#src2#"$clamp"#"$omod");
1124 class VOPProfile <list<ValueType> _ArgVT> {
1126 field list<ValueType> ArgVT = _ArgVT;
1128 field ValueType DstVT = ArgVT[0];
1129 field ValueType Src0VT = ArgVT[1];
1130 field ValueType Src1VT = ArgVT[2];
1131 field ValueType Src2VT = ArgVT[3];
1132 field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
1133 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
1134 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
1135 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
1136 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
1137 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
1139 field bit HasDst = !if(!eq(DstVT.Value, untyped.Value), 0, 1);
1140 field bit HasDst32 = HasDst;
1141 field int NumSrcArgs = getNumSrcArgs<Src0VT, Src1VT, Src2VT>.ret;
1142 field bit HasModifiers = hasModifiers<Src0VT>.ret;
1144 field dag Outs = !if(HasDst,(outs DstRC:$dst),(outs));
1146 // VOP3b instructions are a special case with a second explicit
1147 // output. This is manually overridden for them.
1148 field dag Outs32 = Outs;
1149 field dag Outs64 = Outs;
1151 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
1152 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
1155 field string Asm32 = getAsm32<HasDst, NumSrcArgs>.ret;
1156 field string Asm64 = getAsm64<HasDst, NumSrcArgs, HasModifiers>.ret;
1159 // FIXME: I think these F16/I16 profiles will need to use f16/i16 types in order
1160 // for the instruction patterns to work.
1161 def VOP_F16_F16 : VOPProfile <[f16, f16, untyped, untyped]>;
1162 def VOP_F16_I16 : VOPProfile <[f16, i32, untyped, untyped]>;
1163 def VOP_I16_F16 : VOPProfile <[i32, f16, untyped, untyped]>;
1165 def VOP_F16_F16_F16 : VOPProfile <[f16, f16, f16, untyped]>;
1166 def VOP_F16_F16_I16 : VOPProfile <[f16, f16, i32, untyped]>;
1167 def VOP_I16_I16_I16 : VOPProfile <[i32, i32, i32, untyped]>;
1169 def VOP_NONE : VOPProfile <[untyped, untyped, untyped, untyped]>;
1171 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
1172 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
1173 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
1174 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
1175 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
1176 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
1177 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
1178 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
1179 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
1181 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
1182 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
1183 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
1184 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
1185 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
1186 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
1187 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
1189 // Write out to vcc or arbitrary SGPR.
1190 def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped]> {
1191 let Asm32 = "$dst, vcc, $src0, $src1";
1192 let Asm64 = "$dst, $sdst, $src0, $src1";
1193 let Outs32 = (outs DstRC:$dst);
1194 let Outs64 = (outs DstRC:$dst, SReg_64:$sdst);
1197 // Write out to vcc or arbitrary SGPR and read in from vcc or
1199 def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1]> {
1200 // We use VCSrc_32 to exclude literal constants, even though the
1201 // encoding normally allows them since the implicit VCC use means
1202 // using one would always violate the constant bus
1203 // restriction. SGPRs are still allowed because it should
1204 // technically be possible to use VCC again as src0.
1205 let Src0RC32 = VCSrc_32;
1206 let Asm32 = "$dst, vcc, $src0, $src1, vcc";
1207 let Asm64 = "$dst, $sdst, $src0, $src1, $src2";
1208 let Outs32 = (outs DstRC:$dst);
1209 let Outs64 = (outs DstRC:$dst, SReg_64:$sdst);
1211 // Suppress src2 implied by type since the 32-bit encoding uses an
1212 // implicit VCC use.
1213 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
1216 class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> {
1217 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
1218 let Asm64 = "$vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod";
1221 def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile<f32> {
1222 // FIXME: Hack to stop printing _e64
1223 let DstRC = RegisterOperand<VGPR_32>;
1226 def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64> {
1227 // FIXME: Hack to stop printing _e64
1228 let DstRC = RegisterOperand<VReg_64>;
1231 // VOPC instructions are a special case because for the 32-bit
1232 // encoding, we want to display the implicit vcc write as if it were
1233 // an explicit $dst.
1234 class VOPC_Profile<ValueType vt0, ValueType vt1 = vt0> : VOPProfile <[i1, vt0, vt1, untyped]> {
1235 let Asm32 = "vcc, $src0, $src1";
1236 // The destination for 32-bit encoding is implicit.
1240 class VOPC_Class_Profile<ValueType vt> : VOPC_Profile<vt, i32> {
1241 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
1242 let Asm64 = "$dst, $src0_modifiers, $src1";
1245 def VOPC_I1_F32_F32 : VOPC_Profile<f32>;
1246 def VOPC_I1_F64_F64 : VOPC_Profile<f64>;
1247 def VOPC_I1_I32_I32 : VOPC_Profile<i32>;
1248 def VOPC_I1_I64_I64 : VOPC_Profile<i64>;
1250 def VOPC_I1_F32_I32 : VOPC_Class_Profile<f32>;
1251 def VOPC_I1_F64_I32 : VOPC_Class_Profile<f64>;
1253 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
1254 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
1255 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
1256 def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> {
1257 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
1258 let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
1259 let Asm64 = "$dst, $src0, $src1, $src2";
1262 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
1263 def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {
1264 field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
1265 field string Asm = "$dst, $src0, $vsrc1, $src2";
1267 def VOP_MAC : VOPProfile <[f32, f32, f32, f32]> {
1268 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);
1269 let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3,
1271 let Asm32 = getAsm32<1, 2>.ret;
1272 let Asm64 = getAsm64<1, 2, HasModifiers>.ret;
1274 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
1275 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
1276 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
1278 class SIInstAlias <string asm, Instruction inst, VOPProfile p> :
1279 InstAlias <asm, (inst)>, PredicateControl {
1281 field bit isCompare;
1282 field bit isCommutable;
1286 !if (!eq(p.NumSrcArgs, 0),
1288 (inst p.DstRC:$dst),
1289 !if (!eq(p.NumSrcArgs, 1),
1291 (inst p.DstRC:$dst, p.Src0RC32:$src0),
1292 !if (!eq(p.NumSrcArgs, 2),
1294 (inst p.DstRC:$dst, p.Src0RC32:$src0, p.Src1RC32:$src1),
1295 // else - unreachable
1298 !if (!eq(p.NumSrcArgs, 2),
1300 (inst p.Src0RC32:$src0, p.Src1RC32:$src1),
1301 !if (!eq(p.NumSrcArgs, 1),
1303 (inst p.Src0RC32:$src1),
1309 class SIInstAliasSI <string asm, string op_name, VOPProfile p> :
1310 SIInstAlias <asm, !cast<Instruction>(op_name#"_e32_si"), p> {
1311 let AssemblerPredicate = SIAssemblerPredicate;
1314 class SIInstAliasVI <string asm, string op_name, VOPProfile p> :
1315 SIInstAlias <asm, !cast<Instruction>(op_name#"_e32_vi"), p> {
1316 let AssemblerPredicates = [isVI];
1319 multiclass SIInstAliasBuilder <string asm, VOPProfile p> {
1321 def : SIInstAliasSI <asm, NAME, p>;
1323 def : SIInstAliasVI <asm, NAME, p>;
1326 class VOP <string opName> {
1327 string OpName = opName;
1330 class VOP2_REV <string revOp, bit isOrig> {
1331 string RevOp = revOp;
1332 bit IsOrig = isOrig;
1335 class AtomicNoRet <string noRetOp, bit isRet> {
1336 string NoRetOp = noRetOp;
1340 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1341 VOP1Common <outs, ins, "", pattern>,
1343 SIMCInstr <opName#"_e32", SISubtarget.NONE>,
1344 MnemonicAlias<opName#"_e32", opName> {
1346 let isCodeGenOnly = 1;
1352 class VOP1_Real_si <string opName, vop1 op, dag outs, dag ins, string asm> :
1353 VOP1<op.SI, outs, ins, asm, []>,
1354 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1355 let AssemblerPredicate = SIAssemblerPredicate;
1358 class VOP1_Real_vi <string opName, vop1 op, dag outs, dag ins, string asm> :
1359 VOP1<op.VI, outs, ins, asm, []>,
1360 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1361 let AssemblerPredicates = [isVI];
1364 multiclass VOP1_m <vop1 op, string opName, VOPProfile p, list<dag> pattern,
1365 string asm = opName#p.Asm32> {
1366 def "" : VOP1_Pseudo <p.Outs, p.Ins32, pattern, opName>;
1368 def _si : VOP1_Real_si <opName, op, p.Outs, p.Ins32, asm>;
1370 def _vi : VOP1_Real_vi <opName, op, p.Outs, p.Ins32, asm>;
1374 multiclass VOP1SI_m <vop1 op, string opName, VOPProfile p, list<dag> pattern,
1375 string asm = opName#p.Asm32> {
1377 def "" : VOP1_Pseudo <p.Outs, p.Ins32, pattern, opName>;
1379 def _si : VOP1_Real_si <opName, op, p.Outs, p.Ins32, asm>;
1382 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1383 VOP2Common <outs, ins, "", pattern>,
1385 SIMCInstr<opName#"_e32", SISubtarget.NONE>,
1386 MnemonicAlias<opName#"_e32", opName> {
1388 let isCodeGenOnly = 1;
1391 class VOP2_Real_si <string opName, vop2 op, dag outs, dag ins, string asm> :
1392 VOP2 <op.SI, outs, ins, opName#asm, []>,
1393 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1394 let AssemblerPredicates = [isSICI];
1397 class VOP2_Real_vi <string opName, vop2 op, dag outs, dag ins, string asm> :
1398 VOP2 <op.VI, outs, ins, opName#asm, []>,
1399 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1400 let AssemblerPredicates = [isVI];
1403 multiclass VOP2SI_m <vop2 op, string opName, VOPProfile p, list<dag> pattern,
1406 def "" : VOP2_Pseudo <p.Outs32, p.Ins32, pattern, opName>,
1407 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
1409 def _si : VOP2_Real_si <opName, op, p.Outs32, p.Ins32, p.Asm32>;
1412 multiclass VOP2_m <vop2 op, string opName, VOPProfile p, list <dag> pattern,
1415 def "" : VOP2_Pseudo <p.Outs32, p.Ins32, pattern, opName>,
1416 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
1418 def _si : VOP2_Real_si <opName, op, p.Outs32, p.Ins32, p.Asm32>;
1420 def _vi : VOP2_Real_vi <opName, op, p.Outs32, p.Ins32, p.Asm32>;
1424 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
1426 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
1427 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
1428 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0);
1429 bits<2> omod = !if(HasModifiers, ?, 0);
1430 bits<1> clamp = !if(HasModifiers, ?, 0);
1431 bits<9> src1 = !if(HasSrc1, ?, 0);
1432 bits<9> src2 = !if(HasSrc2, ?, 0);
1435 class VOP3DisableModFields <bit HasSrc0Mods,
1436 bit HasSrc1Mods = 0,
1437 bit HasSrc2Mods = 0,
1438 bit HasOutputMods = 0> {
1439 bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0);
1440 bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0);
1441 bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0);
1442 bits<2> omod = !if(HasOutputMods, ?, 0);
1443 bits<1> clamp = !if(HasOutputMods, ?, 0);
1446 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1447 VOP3Common <outs, ins, "", pattern>,
1449 SIMCInstr<opName#"_e64", SISubtarget.NONE>,
1450 MnemonicAlias<opName#"_e64", opName> {
1452 let isCodeGenOnly = 1;
1458 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1459 VOP3Common <outs, ins, asm, []>,
1461 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1462 let AssemblerPredicates = [isSICI];
1465 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1466 VOP3Common <outs, ins, asm, []>,
1468 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1469 let AssemblerPredicates = [isVI];
1472 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1473 VOP3Common <outs, ins, asm, []>,
1475 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1476 let AssemblerPredicates = [isSICI];
1479 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1480 VOP3Common <outs, ins, asm, []>,
1482 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1483 let AssemblerPredicates = [isVI];
1486 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
1487 string opName, int NumSrcArgs, bit HasMods = 1> {
1489 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1491 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1492 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1493 !if(!eq(NumSrcArgs, 2), 0, 1),
1495 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1496 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1497 !if(!eq(NumSrcArgs, 2), 0, 1),
1501 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
1502 list<dag> pattern, string opName, bit HasMods = 1> {
1504 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1506 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1507 VOP3DisableFields<0, 0, HasMods>;
1509 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1510 VOP3DisableFields<0, 0, HasMods>;
1513 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
1514 list<dag> pattern, string opName, bit HasMods = 1> {
1516 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1518 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1519 VOP3DisableFields<0, 0, HasMods>;
1520 // No VI instruction. This class is for SI only.
1523 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
1524 list<dag> pattern, string opName, string revOp,
1527 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1528 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1530 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1531 VOP3DisableFields<1, 0, HasMods>;
1533 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1534 VOP3DisableFields<1, 0, HasMods>;
1537 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
1538 list<dag> pattern, string opName, string revOp,
1541 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1542 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1544 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1545 VOP3DisableFields<1, 0, HasMods>;
1547 // No VI instruction. This class is for SI only.
1550 // Two operand VOP3b instruction that may have a 3rd SGPR bool operand
1551 // instead of an implicit VCC as in the VOP2b format.
1552 multiclass VOP3b_2_3_m <vop op, dag outs, dag ins, string asm,
1553 list<dag> pattern, string opName, string revOp,
1554 bit HasMods = 1, bit useSrc2Input = 0> {
1555 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1557 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1558 VOP3DisableFields<1, useSrc2Input, HasMods>;
1560 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1561 VOP3DisableFields<1, useSrc2Input, HasMods>;
1564 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1565 list<dag> pattern, string opName,
1566 bit HasMods, bit defExec,
1567 string revOp, list<SchedReadWrite> sched> {
1569 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1570 VOP2_REV<revOp#"_e64", !eq(revOp, opName)> {
1571 let Defs = !if(defExec, [EXEC], []);
1572 let SchedRW = sched;
1575 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1576 VOP3DisableFields<1, 0, HasMods> {
1577 let Defs = !if(defExec, [EXEC], []);
1578 let SchedRW = sched;
1581 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1582 VOP3DisableFields<1, 0, HasMods> {
1583 let Defs = !if(defExec, [EXEC], []);
1584 let SchedRW = sched;
1588 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1589 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1590 string asm, list<dag> pattern = []> {
1591 let isPseudo = 1, isCodeGenOnly = 1 in {
1592 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1593 SIMCInstr<opName, SISubtarget.NONE>;
1596 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1597 SIMCInstr <opName, SISubtarget.SI> {
1598 let AssemblerPredicates = [isSICI];
1601 def _vi : VOP3Common <outs, ins, asm, []>,
1603 VOP3DisableFields <1, 0, 0>,
1604 SIMCInstr <opName, SISubtarget.VI> {
1605 let AssemblerPredicates = [isVI];
1609 multiclass VOP1_Helper <vop1 op, string opName, VOPProfile p, list<dag> pat32,
1612 defm _e32 : VOP1_m <op, opName, p, pat32>;
1614 defm _e64 : VOP3_1_m <op, p.Outs, p.Ins64, opName#p.Asm64, pat64, opName,
1618 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1619 SDPatternOperator node = null_frag> : VOP1_Helper <
1622 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1623 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1624 [(set P.DstVT:$dst, (node P.Src0VT:$src0))])
1627 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1628 SDPatternOperator node = null_frag> {
1630 defm _e32 : VOP1SI_m <op, opName, P, []>;
1632 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1634 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1635 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1636 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1637 opName, P.HasModifiers>;
1640 multiclass VOP2_Helper <vop2 op, string opName, VOPProfile p, list<dag> pat32,
1641 list<dag> pat64, string revOp> {
1643 defm _e32 : VOP2_m <op, opName, p, pat32, revOp>;
1645 defm _e64 : VOP3_2_m <op, p.Outs, p.Ins64, opName#p.Asm64, pat64, opName,
1646 revOp, p.HasModifiers>;
1649 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1650 SDPatternOperator node = null_frag,
1651 string revOp = opName> : VOP2_Helper <
1655 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1656 i1:$clamp, i32:$omod)),
1657 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1658 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1662 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1663 SDPatternOperator node = null_frag,
1664 string revOp = opName> {
1666 defm _e32 : VOP2SI_m <op, opName, P, [], revOp>;
1668 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1671 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1672 i1:$clamp, i32:$omod)),
1673 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1674 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1675 opName, revOp, P.HasModifiers>;
1678 multiclass VOP2b_Helper <vop2 op, string opName, VOPProfile p,
1679 list<dag> pat32, list<dag> pat64,
1680 string revOp, bit useSGPRInput> {
1682 let SchedRW = [Write32Bit, WriteSALU] in {
1683 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in {
1684 defm _e32 : VOP2_m <op, opName, p, pat32, revOp>;
1687 defm _e64 : VOP3b_2_3_m <op, p.Outs64, p.Ins64, opName#p.Asm64, pat64,
1688 opName, revOp, p.HasModifiers, useSGPRInput>;
1692 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1693 SDPatternOperator node = null_frag,
1694 string revOp = opName> : VOP2b_Helper <
1698 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1699 i1:$clamp, i32:$omod)),
1700 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1701 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1702 revOp, !eq(P.NumSrcArgs, 3)
1705 // A VOP2 instruction that is VOP3-only on VI.
1706 multiclass VOP2_VI3_Helper <vop23 op, string opName, VOPProfile p,
1707 list<dag> pat32, list<dag> pat64, string revOp> {
1709 defm _e32 : VOP2SI_m <op, opName, p, pat32, revOp>;
1711 defm _e64 : VOP3_2_m <op, p.Outs, p.Ins64, opName#p.Asm64, pat64, opName,
1712 revOp, p.HasModifiers>;
1715 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1716 SDPatternOperator node = null_frag,
1717 string revOp = opName>
1722 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1723 i1:$clamp, i32:$omod)),
1724 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1725 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1729 multiclass VOP2MADK <vop2 op, string opName, list<dag> pattern = []> {
1731 def "" : VOP2_Pseudo <VOP_MADK.Outs, VOP_MADK.Ins, pattern, opName>;
1733 let isCodeGenOnly = 0 in {
1734 def _si : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1735 !strconcat(opName, VOP_MADK.Asm), []>,
1736 SIMCInstr <opName#"_e32", SISubtarget.SI>,
1737 VOP2_MADKe <op.SI> {
1738 let AssemblerPredicates = [isSICI];
1741 def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1742 !strconcat(opName, VOP_MADK.Asm), []>,
1743 SIMCInstr <opName#"_e32", SISubtarget.VI>,
1744 VOP2_MADKe <op.VI> {
1745 let AssemblerPredicates = [isVI];
1747 } // End isCodeGenOnly = 0
1750 class VOPC_Pseudo <dag ins, list<dag> pattern, string opName> :
1751 VOPCCommon <ins, "", pattern>,
1753 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1755 let isCodeGenOnly = 1;
1758 multiclass VOPC_m <vopc op, dag ins, string op_asm, list<dag> pattern,
1759 string opName, bit DefExec, VOPProfile p,
1760 list<SchedReadWrite> sched,
1761 string revOpName = "", string asm = opName#"_e32 "#op_asm,
1762 string alias_asm = opName#" "#op_asm> {
1763 def "" : VOPC_Pseudo <ins, pattern, opName> {
1764 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
1765 let SchedRW = sched;
1768 let AssemblerPredicates = [isSICI] in {
1769 def _si : VOPC<op.SI, ins, asm, []>,
1770 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1771 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
1772 let hasSideEffects = DefExec;
1773 let SchedRW = sched;
1776 } // End AssemblerPredicates = [isSICI]
1778 let AssemblerPredicates = [isVI] in {
1779 def _vi : VOPC<op.VI, ins, asm, []>,
1780 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1781 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
1782 let hasSideEffects = DefExec;
1783 let SchedRW = sched;
1786 } // End AssemblerPredicates = [isVI]
1788 defm : SIInstAliasBuilder<alias_asm, p>;
1791 multiclass VOPC_Helper <vopc op, string opName, list<dag> pat32,
1792 list<dag> pat64, bit DefExec, string revOp,
1793 VOPProfile p, list<SchedReadWrite> sched> {
1794 defm _e32 : VOPC_m <op, p.Ins32, p.Asm32, pat32, opName, DefExec, p, sched>;
1796 defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$dst), p.Ins64, opName#p.Asm64, pat64,
1797 opName, p.HasModifiers, DefExec, revOp, sched>;
1800 // Special case for class instructions which only have modifiers on
1801 // the 1st source operand.
1802 multiclass VOPC_Class_Helper <vopc op, string opName, list<dag> pat32,
1803 list<dag> pat64, bit DefExec, string revOp,
1804 VOPProfile p, list<SchedReadWrite> sched> {
1805 defm _e32 : VOPC_m <op, p.Ins32, p.Asm32, pat32, opName, DefExec, p, sched>;
1807 defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$dst), p.Ins64, opName#p.Asm64, pat64,
1808 opName, p.HasModifiers, DefExec, revOp, sched>,
1809 VOP3DisableModFields<1, 0, 0>;
1812 multiclass VOPCInst <vopc op, string opName,
1813 VOPProfile P, PatLeaf cond = COND_NULL,
1814 string revOp = opName,
1816 list<SchedReadWrite> sched = [Write32Bit]> :
1821 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1822 i1:$clamp, i32:$omod)),
1823 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1825 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1826 DefExec, revOp, P, sched
1829 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1831 list<SchedReadWrite> sched> : VOPC_Class_Helper <
1835 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1836 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1837 DefExec, opName, P, sched
1841 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1842 VOPCInst <op, opName, VOPC_I1_F32_F32, cond, revOp>;
1844 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1845 VOPCInst <op, opName, VOPC_I1_F64_F64, cond, revOp, 0, [WriteDoubleAdd]>;
1847 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1848 VOPCInst <op, opName, VOPC_I1_I32_I32, cond, revOp>;
1850 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1851 VOPCInst <op, opName, VOPC_I1_I64_I64, cond, revOp, 0, [Write64Bit]>;
1854 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1855 PatLeaf cond = COND_NULL,
1856 list<SchedReadWrite> sched,
1858 : VOPCInst <op, opName, P, cond, revOp, 1, sched>;
1860 multiclass VOPCX_F32 <vopc op, string opName, string revOp = opName> :
1861 VOPCX <op, opName, VOPC_I1_F32_F32, COND_NULL, [Write32Bit], revOp>;
1863 multiclass VOPCX_F64 <vopc op, string opName, string revOp = opName> :
1864 VOPCX <op, opName, VOPC_I1_F64_F64, COND_NULL, [WriteDoubleAdd], revOp>;
1866 multiclass VOPCX_I32 <vopc op, string opName, string revOp = opName> :
1867 VOPCX <op, opName, VOPC_I1_I32_I32, COND_NULL, [Write32Bit], revOp>;
1869 multiclass VOPCX_I64 <vopc op, string opName, string revOp = opName> :
1870 VOPCX <op, opName, VOPC_I1_I64_I64, COND_NULL, [Write64Bit], revOp>;
1872 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1873 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1874 op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods
1877 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1878 VOPCClassInst <op, opName, VOPC_I1_F32_I32, 0, [Write32Bit]>;
1880 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1881 VOPCClassInst <op, opName, VOPC_I1_F32_I32, 1, [Write32Bit]>;
1883 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1884 VOPCClassInst <op, opName, VOPC_I1_F64_I32, 0, [WriteDoubleAdd]>;
1886 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1887 VOPCClassInst <op, opName, VOPC_I1_F64_I32, 1, [WriteDoubleAdd]>;
1889 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1890 SDPatternOperator node = null_frag> : VOP3_Helper <
1891 op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64,
1892 !if(!eq(P.NumSrcArgs, 3),
1895 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1896 i1:$clamp, i32:$omod)),
1897 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1898 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1899 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1901 !if(!eq(P.NumSrcArgs, 2),
1904 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1905 i1:$clamp, i32:$omod)),
1906 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1907 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1908 /* P.NumSrcArgs == 1 */,
1911 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1912 i1:$clamp, i32:$omod))))],
1913 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1914 P.NumSrcArgs, P.HasModifiers
1917 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1918 // only VOP instruction that implicitly reads VCC.
1919 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1921 SDPatternOperator node = null_frag> : VOP3_Helper <
1923 (outs P.DstRC.RegClass:$dst),
1924 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1925 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1926 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1929 "$dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1931 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1932 i1:$clamp, i32:$omod)),
1933 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1934 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1939 multiclass VOP3bInst <vop op, string opName, VOPProfile P, list<dag> pattern = []> :
1941 op, P.Outs64, P.Ins64,
1942 opName#" "#P.Asm64, pattern,
1946 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1947 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1948 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1949 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1950 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1951 i32:$src1_modifiers, P.Src1VT:$src1,
1952 i32:$src2_modifiers, P.Src2VT:$src2,
1956 //===----------------------------------------------------------------------===//
1957 // Interpolation opcodes
1958 //===----------------------------------------------------------------------===//
1960 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1961 VINTRPCommon <outs, ins, "", pattern>,
1962 SIMCInstr<opName, SISubtarget.NONE> {
1964 let isCodeGenOnly = 1;
1967 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1969 VINTRPCommon <outs, ins, asm, []>,
1971 SIMCInstr<opName, SISubtarget.SI>;
1973 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1975 VINTRPCommon <outs, ins, asm, []>,
1977 SIMCInstr<opName, SISubtarget.VI>;
1979 multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
1980 list<dag> pattern = []> {
1981 def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
1983 def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>;
1985 def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
1988 //===----------------------------------------------------------------------===//
1989 // Vector I/O classes
1990 //===----------------------------------------------------------------------===//
1992 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1993 DS <outs, ins, "", pattern>,
1994 SIMCInstr <opName, SISubtarget.NONE> {
1996 let isCodeGenOnly = 1;
1999 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
2000 DS <outs, ins, asm, []>,
2002 SIMCInstr <opName, SISubtarget.SI> {
2003 let isCodeGenOnly = 0;
2006 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
2007 DS <outs, ins, asm, []>,
2009 SIMCInstr <opName, SISubtarget.VI>;
2011 class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
2012 DS_Real_si <op,opName, outs, ins, asm> {
2014 // Single load interpret the 2 i8imm operands as a single i16 offset.
2016 let offset0 = offset{7-0};
2017 let offset1 = offset{15-8};
2018 let isCodeGenOnly = 0;
2021 class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
2022 DS_Real_vi <op, opName, outs, ins, asm> {
2024 // Single load interpret the 2 i8imm operands as a single i16 offset.
2026 let offset0 = offset{7-0};
2027 let offset1 = offset{15-8};
2030 multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc,
2031 dag outs = (outs rc:$vdst),
2032 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds),
2033 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
2035 def "" : DS_Pseudo <opName, outs, ins, []>;
2037 let data0 = 0, data1 = 0 in {
2038 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2039 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2043 multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc,
2044 dag outs = (outs rc:$vdst),
2045 dag ins = (ins VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
2047 string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> {
2049 def "" : DS_Pseudo <opName, outs, ins, []>;
2051 let data0 = 0, data1 = 0, AsmMatchConverter = "cvtDSOffset01" in {
2052 def _si : DS_Real_si <op, opName, outs, ins, asm>;
2053 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
2057 multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc,
2059 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds),
2060 string asm = opName#" $addr, $data0"#"$offset$gds"> {
2062 def "" : DS_Pseudo <opName, outs, ins, []>,
2063 AtomicNoRet<opName, 0>;
2065 let data1 = 0, vdst = 0 in {
2066 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2067 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2071 multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc,
2073 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
2074 ds_offset0:$offset0, ds_offset1:$offset1, gds01:$gds),
2075 string asm = opName#" $addr, $data0, $data1"#"$offset0"#"$offset1"#"$gds"> {
2077 def "" : DS_Pseudo <opName, outs, ins, []>;
2079 let vdst = 0, AsmMatchConverter = "cvtDSOffset01" in {
2080 def _si : DS_Real_si <op, opName, outs, ins, asm>;
2081 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
2085 multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc,
2086 string noRetOp = "",
2087 dag outs = (outs rc:$vdst),
2088 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds),
2089 string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> {
2091 let hasPostISelHook = 1 in {
2092 def "" : DS_Pseudo <opName, outs, ins, []>,
2093 AtomicNoRet<noRetOp, 1>;
2096 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2097 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2102 multiclass DS_1A2D_RET_m <bits<8> op, string opName, RegisterClass rc,
2103 string noRetOp = "", dag ins,
2104 dag outs = (outs rc:$vdst),
2105 string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"#"$gds"> {
2107 let hasPostISelHook = 1 in {
2108 def "" : DS_Pseudo <opName, outs, ins, []>,
2109 AtomicNoRet<noRetOp, 1>;
2111 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2112 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2116 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
2117 string noRetOp = "", RegisterClass src = rc> :
2118 DS_1A2D_RET_m <op, asm, rc, noRetOp,
2119 (ins VGPR_32:$addr, src:$data0, src:$data1,
2120 ds_offset:$offset, gds:$gds)
2123 multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc,
2124 string noRetOp = opName,
2126 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
2127 ds_offset:$offset, gds:$gds),
2128 string asm = opName#" $addr, $data0, $data1"#"$offset"#"$gds"> {
2130 def "" : DS_Pseudo <opName, outs, ins, []>,
2131 AtomicNoRet<noRetOp, 0>;
2134 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2135 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2139 multiclass DS_0A_RET <bits<8> op, string opName,
2140 dag outs = (outs VGPR_32:$vdst),
2141 dag ins = (ins ds_offset:$offset, gds:$gds),
2142 string asm = opName#" $vdst"#"$offset"#"$gds"> {
2144 let mayLoad = 1, mayStore = 1 in {
2145 def "" : DS_Pseudo <opName, outs, ins, []>;
2147 let addr = 0, data0 = 0, data1 = 0 in {
2148 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2149 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2150 } // end addr = 0, data0 = 0, data1 = 0
2151 } // end mayLoad = 1, mayStore = 1
2154 multiclass DS_1A_RET_GDS <bits<8> op, string opName,
2155 dag outs = (outs VGPR_32:$vdst),
2156 dag ins = (ins VGPR_32:$addr, ds_offset_gds:$offset),
2157 string asm = opName#" $vdst, $addr"#"$offset gds"> {
2159 def "" : DS_Pseudo <opName, outs, ins, []>;
2161 let data0 = 0, data1 = 0, gds = 1 in {
2162 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2163 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2164 } // end data0 = 0, data1 = 0, gds = 1
2167 multiclass DS_1A_GDS <bits<8> op, string opName,
2169 dag ins = (ins VGPR_32:$addr),
2170 string asm = opName#" $addr gds"> {
2172 def "" : DS_Pseudo <opName, outs, ins, []>;
2174 let vdst = 0, data0 = 0, data1 = 0, offset0 = 0, offset1 = 0, gds = 1 in {
2175 def _si : DS_Real_si <op, opName, outs, ins, asm>;
2176 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
2177 } // end vdst = 0, data = 0, data1 = 0, gds = 1
2180 multiclass DS_1A <bits<8> op, string opName,
2182 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds),
2183 string asm = opName#" $addr"#"$offset"#"$gds"> {
2185 let mayLoad = 1, mayStore = 1 in {
2186 def "" : DS_Pseudo <opName, outs, ins, []>;
2188 let vdst = 0, data0 = 0, data1 = 0 in {
2189 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2190 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2191 } // let vdst = 0, data0 = 0, data1 = 0
2192 } // end mayLoad = 1, mayStore = 1
2195 //===----------------------------------------------------------------------===//
2197 //===----------------------------------------------------------------------===//
2199 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2200 MTBUF <outs, ins, "", pattern>,
2201 SIMCInstr<opName, SISubtarget.NONE> {
2203 let isCodeGenOnly = 1;
2206 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
2208 MTBUF <outs, ins, asm, []>,
2210 SIMCInstr<opName, SISubtarget.SI>;
2212 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
2213 MTBUF <outs, ins, asm, []>,
2215 SIMCInstr <opName, SISubtarget.VI>;
2217 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
2218 list<dag> pattern> {
2220 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
2222 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
2224 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
2228 let mayStore = 1, mayLoad = 0 in {
2230 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
2231 RegisterClass regClass> : MTBUF_m <
2233 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
2234 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
2235 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2236 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
2237 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2240 } // mayStore = 1, mayLoad = 0
2242 let mayLoad = 1, mayStore = 0 in {
2244 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
2245 RegisterClass regClass> : MTBUF_m <
2246 op, opName, (outs regClass:$dst),
2247 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
2248 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
2249 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2250 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
2251 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2254 } // mayLoad = 1, mayStore = 0
2256 //===----------------------------------------------------------------------===//
2258 //===----------------------------------------------------------------------===//
2260 class mubuf <bits<7> si, bits<7> vi = si> {
2261 field bits<7> SI = si;
2262 field bits<7> VI = vi;
2265 let isCodeGenOnly = 0 in {
2267 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
2268 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
2272 } // End let isCodeGenOnly = 0
2274 class MUBUF_vi <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
2275 MUBUF <outs, ins, asm, pattern>, MUBUFe_vi <op> {
2279 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
2280 bit IsAddr64 = is_addr64;
2281 string OpName = NAME # suffix;
2284 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2285 MUBUF <outs, ins, "", pattern>,
2286 SIMCInstr<opName, SISubtarget.NONE> {
2288 let isCodeGenOnly = 1;
2290 // dummy fields, so that we can use let statements around multiclasses
2300 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
2302 MUBUF <outs, ins, asm, []>,
2304 SIMCInstr<opName, SISubtarget.SI> {
2308 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
2310 MUBUF <outs, ins, asm, []>,
2312 SIMCInstr<opName, SISubtarget.VI> {
2316 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
2317 list<dag> pattern> {
2319 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2320 MUBUFAddr64Table <0>;
2322 let addr64 = 0, isCodeGenOnly = 0 in {
2323 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2326 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2329 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
2330 dag ins, string asm, list<dag> pattern> {
2332 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2333 MUBUFAddr64Table <1>;
2335 let addr64 = 1, isCodeGenOnly = 0 in {
2336 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2339 // There is no VI version. If the pseudo is selected, it should be lowered
2340 // for VI appropriately.
2343 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
2344 string asm, list<dag> pattern, bit is_return> {
2346 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2347 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
2348 AtomicNoRet<NAME#"_OFFSET", is_return>;
2350 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
2352 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2355 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2359 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
2360 string asm, list<dag> pattern, bit is_return> {
2362 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2363 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
2364 AtomicNoRet<NAME#"_ADDR64", is_return>;
2366 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
2367 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2370 // There is no VI version. If the pseudo is selected, it should be lowered
2371 // for VI appropriately.
2374 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
2375 ValueType vt, SDPatternOperator atomic> {
2377 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
2379 // No return variants
2382 defm _ADDR64 : MUBUFAtomicAddr64_m <
2383 op, name#"_addr64", (outs),
2384 (ins rc:$vdata, VReg_64:$vaddr, SReg_128:$srsrc,
2385 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2386 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
2389 defm _OFFSET : MUBUFAtomicOffset_m <
2390 op, name#"_offset", (outs),
2391 (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset,
2393 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
2397 // Variant that return values
2398 let glc = 1, Constraints = "$vdata = $vdata_in",
2399 DisableEncoding = "$vdata_in" in {
2401 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
2402 op, name#"_rtn_addr64", (outs rc:$vdata),
2403 (ins rc:$vdata_in, VReg_64:$vaddr, SReg_128:$srsrc,
2404 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2405 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
2407 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
2408 i16:$offset, i1:$slc), vt:$vdata_in))], 1
2411 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
2412 op, name#"_rtn_offset", (outs rc:$vdata),
2413 (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset,
2414 mbuf_offset:$offset, slc:$slc),
2415 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc$slc",
2417 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
2418 i1:$slc), vt:$vdata_in))], 1
2423 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
2426 // FIXME: tfe can't be an operand because it requires a separate
2427 // opcode because it needs an N+1 register class dest register.
2428 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
2429 ValueType load_vt = i32,
2430 SDPatternOperator ld = null_frag> {
2432 let mayLoad = 1, mayStore = 0 in {
2433 let offen = 0, idxen = 0, vaddr = 0 in {
2434 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
2435 (ins SReg_128:$srsrc, SCSrc_32:$soffset,
2436 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2437 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2438 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
2439 i32:$soffset, i16:$offset,
2440 i1:$glc, i1:$slc, i1:$tfe)))]>;
2443 let offen = 1, idxen = 0 in {
2444 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
2445 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2446 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
2448 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2451 let offen = 0, idxen = 1 in {
2452 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
2453 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2454 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2455 slc:$slc, tfe:$tfe),
2456 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2459 let offen = 1, idxen = 1 in {
2460 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
2461 (ins VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2462 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2463 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2466 let offen = 0, idxen = 0 in {
2467 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
2468 (ins VReg_64:$vaddr, SReg_128:$srsrc,
2469 SCSrc_32:$soffset, mbuf_offset:$offset,
2470 glc:$glc, slc:$slc, tfe:$tfe),
2471 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#
2472 "$glc"#"$slc"#"$tfe",
2473 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
2474 i64:$vaddr, i32:$soffset,
2475 i16:$offset, i1:$glc, i1:$slc,
2481 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
2482 ValueType store_vt = i32, SDPatternOperator st = null_frag> {
2483 let mayLoad = 0, mayStore = 1 in {
2484 defm : MUBUF_m <op, name, (outs),
2485 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2486 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
2488 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
2489 "$glc"#"$slc"#"$tfe", []>;
2491 let offen = 0, idxen = 0, vaddr = 0 in {
2492 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
2493 (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset,
2494 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2495 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2496 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
2497 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
2498 } // offen = 0, idxen = 0, vaddr = 0
2500 let offen = 1, idxen = 0 in {
2501 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
2502 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2503 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2504 slc:$slc, tfe:$tfe),
2505 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
2506 "$glc"#"$slc"#"$tfe", []>;
2507 } // end offen = 1, idxen = 0
2509 let offen = 0, idxen = 1 in {
2510 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs),
2511 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2512 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2513 slc:$slc, tfe:$tfe),
2514 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2517 let offen = 1, idxen = 1 in {
2518 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs),
2519 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2520 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2521 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2524 let offen = 0, idxen = 0 in {
2525 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
2526 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc,
2528 mbuf_offset:$offset, glc:$glc, slc:$slc,
2530 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#
2531 "$offset"#"$glc"#"$slc"#"$tfe",
2532 [(st store_vt:$vdata,
2533 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
2534 i32:$soffset, i16:$offset,
2535 i1:$glc, i1:$slc, i1:$tfe))]>;
2537 } // End mayLoad = 0, mayStore = 1
2540 // For cache invalidation instructions.
2541 multiclass MUBUF_Invalidate <mubuf op, string opName, SDPatternOperator node> {
2542 let hasSideEffects = 1, mayStore = 1, AsmMatchConverter = "" in {
2543 def "" : MUBUF_Pseudo <opName, (outs), (ins), [(node)]>;
2545 // Set everything to 0.
2546 let offset = 0, offen = 0, idxen = 0, glc = 0, vaddr = 0,
2547 vdata = 0, srsrc = 0, slc = 0, tfe = 0, soffset = 0 in {
2549 def _si : MUBUF_Real_si <op, opName, (outs), (ins), opName>;
2552 def _vi : MUBUF_Real_vi <op, opName, (outs), (ins), opName>;
2554 } // End hasSideEffects = 1, mayStore = 1, AsmMatchConverter = ""
2557 //===----------------------------------------------------------------------===//
2559 //===----------------------------------------------------------------------===//
2561 class flat <bits<7> ci, bits<7> vi = ci> {
2562 field bits<7> CI = ci;
2563 field bits<7> VI = vi;
2566 class FLAT_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2567 FLAT <0, outs, ins, "", pattern>,
2568 SIMCInstr<opName, SISubtarget.NONE> {
2570 let isCodeGenOnly = 1;
2573 class FLAT_Real_ci <bits<7> op, string opName, dag outs, dag ins, string asm> :
2574 FLAT <op, outs, ins, asm, []>,
2575 SIMCInstr<opName, SISubtarget.SI> {
2576 let AssemblerPredicate = isCIOnly;
2579 class FLAT_Real_vi <bits<7> op, string opName, dag outs, dag ins, string asm> :
2580 FLAT <op, outs, ins, asm, []>,
2581 SIMCInstr<opName, SISubtarget.VI> {
2582 let AssemblerPredicate = VIAssemblerPredicate;
2585 multiclass FLAT_AtomicRet_m <flat op, dag outs, dag ins, string asm,
2586 list<dag> pattern> {
2587 def "" : FLAT_Pseudo <NAME#"_RTN", outs, ins, pattern>,
2588 AtomicNoRet <NAME, 1>;
2590 def _ci : FLAT_Real_ci <op.CI, NAME#"_RTN", outs, ins, asm>;
2592 def _vi : FLAT_Real_vi <op.VI, NAME#"_RTN", outs, ins, asm>;
2595 multiclass FLAT_Load_Helper <flat op, string asm_name,
2596 RegisterClass regClass,
2597 dag outs = (outs regClass:$vdst),
2598 dag ins = (ins VReg_64:$addr, glc_flat:$glc, slc_flat:$slc, tfe_flat:$tfe),
2599 string asm = asm_name#" $vdst, $addr"#"$glc"#"$slc"#"$tfe"> {
2601 let data = 0, mayLoad = 1 in {
2603 def "" : FLAT_Pseudo <NAME, outs, ins, []>;
2605 def _ci : FLAT_Real_ci <op.CI, NAME, outs, ins, asm>;
2607 def _vi : FLAT_Real_vi <op.VI, NAME, outs, ins, asm>;
2611 multiclass FLAT_Store_Helper <flat op, string asm_name,
2612 RegisterClass vdataClass,
2614 dag ins = (ins vdataClass:$data, VReg_64:$addr, glc_flat:$glc,
2615 slc_flat:$slc, tfe_flat:$tfe),
2616 string asm = asm_name#" $data, $addr"#"$glc"#"$slc"#"$tfe"> {
2618 let mayLoad = 0, mayStore = 1, vdst = 0 in {
2620 def "" : FLAT_Pseudo <NAME, outs, ins, []>;
2622 def _ci : FLAT_Real_ci <op.CI, NAME, outs, ins, asm>;
2624 def _vi : FLAT_Real_vi <op.VI, NAME, outs, ins, asm>;
2628 multiclass FLAT_ATOMIC <flat op, string asm_name, RegisterClass vdst_rc,
2629 RegisterClass data_rc = vdst_rc,
2630 dag outs_noret = (outs),
2631 string asm_noret = asm_name#" $addr, $data"#"$slc"#"$tfe"> {
2633 let mayLoad = 1, mayStore = 1, glc = 0, vdst = 0 in {
2634 def "" : FLAT_Pseudo <NAME, outs_noret,
2635 (ins VReg_64:$addr, data_rc:$data,
2636 slc_flat_atomic:$slc, tfe_flat_atomic:$tfe), []>,
2637 AtomicNoRet <NAME, 0>;
2639 def _ci : FLAT_Real_ci <op.CI, NAME, outs_noret,
2640 (ins VReg_64:$addr, data_rc:$data,
2641 slc_flat_atomic:$slc, tfe_flat_atomic:$tfe),
2644 def _vi : FLAT_Real_vi <op.VI, NAME, outs_noret,
2645 (ins VReg_64:$addr, data_rc:$data,
2646 slc_flat_atomic:$slc, tfe_flat_atomic:$tfe),
2650 let glc = 1, hasPostISelHook = 1 in {
2651 defm _RTN : FLAT_AtomicRet_m <op, (outs vdst_rc:$vdst),
2652 (ins VReg_64:$addr, data_rc:$data, slc_flat_atomic:$slc,
2653 tfe_flat_atomic:$tfe),
2654 asm_name#" $vdst, $addr, $data glc"#"$slc"#"$tfe", []>;
2658 class MIMG_Mask <string op, int channels> {
2660 int Channels = channels;
2663 class MIMG_NoSampler_Helper <bits<7> op, string asm,
2664 RegisterClass dst_rc,
2665 RegisterClass src_rc> : MIMG <
2667 (outs dst_rc:$vdata),
2668 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2669 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2671 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2672 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
2677 let hasPostISelHook = 1;
2680 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
2681 RegisterClass dst_rc,
2683 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
2684 MIMG_Mask<asm#"_V1", channels>;
2685 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
2686 MIMG_Mask<asm#"_V2", channels>;
2687 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
2688 MIMG_Mask<asm#"_V4", channels>;
2691 multiclass MIMG_NoSampler <bits<7> op, string asm> {
2692 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
2693 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
2694 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
2695 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
2698 class MIMG_Sampler_Helper <bits<7> op, string asm,
2699 RegisterClass dst_rc,
2700 RegisterClass src_rc, int wqm> : MIMG <
2702 (outs dst_rc:$vdata),
2703 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2704 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2705 SReg_256:$srsrc, SReg_128:$ssamp),
2706 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2707 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2711 let hasPostISelHook = 1;
2715 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2716 RegisterClass dst_rc,
2717 int channels, int wqm> {
2718 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2719 MIMG_Mask<asm#"_V1", channels>;
2720 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2721 MIMG_Mask<asm#"_V2", channels>;
2722 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2723 MIMG_Mask<asm#"_V4", channels>;
2724 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2725 MIMG_Mask<asm#"_V8", channels>;
2726 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2727 MIMG_Mask<asm#"_V16", channels>;
2730 multiclass MIMG_Sampler <bits<7> op, string asm> {
2731 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2732 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2733 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2734 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2737 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2738 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2739 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2740 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2741 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2744 class MIMG_Gather_Helper <bits<7> op, string asm,
2745 RegisterClass dst_rc,
2746 RegisterClass src_rc, int wqm> : MIMG <
2748 (outs dst_rc:$vdata),
2749 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2750 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2751 SReg_256:$srsrc, SReg_128:$ssamp),
2752 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2753 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2758 // DMASK was repurposed for GATHER4. 4 components are always
2759 // returned and DMASK works like a swizzle - it selects
2760 // the component to fetch. The only useful DMASK values are
2761 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2762 // (red,red,red,red) etc.) The ISA document doesn't mention
2764 // Therefore, disable all code which updates DMASK by setting these two:
2766 let hasPostISelHook = 0;
2770 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2771 RegisterClass dst_rc,
2772 int channels, int wqm> {
2773 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2774 MIMG_Mask<asm#"_V1", channels>;
2775 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2776 MIMG_Mask<asm#"_V2", channels>;
2777 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2778 MIMG_Mask<asm#"_V4", channels>;
2779 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2780 MIMG_Mask<asm#"_V8", channels>;
2781 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2782 MIMG_Mask<asm#"_V16", channels>;
2785 multiclass MIMG_Gather <bits<7> op, string asm> {
2786 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2787 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2788 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2789 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2792 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2793 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2794 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2795 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2796 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2799 //===----------------------------------------------------------------------===//
2800 // Vector instruction mappings
2801 //===----------------------------------------------------------------------===//
2803 // Maps an opcode in e32 form to its e64 equivalent
2804 def getVOPe64 : InstrMapping {
2805 let FilterClass = "VOP";
2806 let RowFields = ["OpName"];
2807 let ColFields = ["Size"];
2809 let ValueCols = [["8"]];
2812 // Maps an opcode in e64 form to its e32 equivalent
2813 def getVOPe32 : InstrMapping {
2814 let FilterClass = "VOP";
2815 let RowFields = ["OpName"];
2816 let ColFields = ["Size"];
2818 let ValueCols = [["4"]];
2821 def getMaskedMIMGOp : InstrMapping {
2822 let FilterClass = "MIMG_Mask";
2823 let RowFields = ["Op"];
2824 let ColFields = ["Channels"];
2826 let ValueCols = [["1"], ["2"], ["3"] ];
2829 // Maps an commuted opcode to its original version
2830 def getCommuteOrig : InstrMapping {
2831 let FilterClass = "VOP2_REV";
2832 let RowFields = ["RevOp"];
2833 let ColFields = ["IsOrig"];
2835 let ValueCols = [["1"]];
2838 // Maps an original opcode to its commuted version
2839 def getCommuteRev : InstrMapping {
2840 let FilterClass = "VOP2_REV";
2841 let RowFields = ["RevOp"];
2842 let ColFields = ["IsOrig"];
2844 let ValueCols = [["0"]];
2847 def getCommuteCmpOrig : InstrMapping {
2848 let FilterClass = "VOP2_REV";
2849 let RowFields = ["RevOp"];
2850 let ColFields = ["IsOrig"];
2852 let ValueCols = [["1"]];
2855 // Maps an original opcode to its commuted version
2856 def getCommuteCmpRev : InstrMapping {
2857 let FilterClass = "VOP2_REV";
2858 let RowFields = ["RevOp"];
2859 let ColFields = ["IsOrig"];
2861 let ValueCols = [["0"]];
2865 def getMCOpcodeGen : InstrMapping {
2866 let FilterClass = "SIMCInstr";
2867 let RowFields = ["PseudoInstr"];
2868 let ColFields = ["Subtarget"];
2869 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2870 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2873 def getAddr64Inst : InstrMapping {
2874 let FilterClass = "MUBUFAddr64Table";
2875 let RowFields = ["OpName"];
2876 let ColFields = ["IsAddr64"];
2878 let ValueCols = [["1"]];
2881 // Maps an atomic opcode to its version with a return value.
2882 def getAtomicRetOp : InstrMapping {
2883 let FilterClass = "AtomicNoRet";
2884 let RowFields = ["NoRetOp"];
2885 let ColFields = ["IsRet"];
2887 let ValueCols = [["1"]];
2890 // Maps an atomic opcode to its returnless version.
2891 def getAtomicNoRetOp : InstrMapping {
2892 let FilterClass = "AtomicNoRet";
2893 let RowFields = ["NoRetOp"];
2894 let ColFields = ["IsRet"];
2896 let ValueCols = [["0"]];
2899 include "SIInstructions.td"
2900 include "CIInstructions.td"
2901 include "VIInstructions.td"