1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 def isCI : Predicate<"Subtarget->getGeneration() "
10 ">= AMDGPUSubtarget::SEA_ISLANDS">;
11 def isVI : Predicate <
12 "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
13 AssemblerPredicate<"FeatureGCN3Encoding">;
15 def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">;
22 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
23 field bits<8> SI = si;
24 field bits<8> VI = vi;
26 field bits<9> SI3 = {0, si{7-0}};
27 field bits<10> VI3 = {0, 0, vi{7-0}};
30 class vop1 <bits<8> si, bits<8> vi = si> : vop {
31 field bits<8> SI = si;
32 field bits<8> VI = vi;
34 field bits<9> SI3 = {1, 1, si{6-0}};
35 field bits<10> VI3 = !add(0x140, vi);
38 class vop2 <bits<6> si, bits<6> vi = si> : vop {
39 field bits<6> SI = si;
40 field bits<6> VI = vi;
42 field bits<9> SI3 = {1, 0, 0, si{5-0}};
43 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
46 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
47 // that doesn't have VOP2 encoding on VI
48 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
52 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
57 class sop1 <bits<8> si, bits<8> vi = si> {
58 field bits<8> SI = si;
59 field bits<8> VI = vi;
62 class sop2 <bits<7> si, bits<7> vi = si> {
63 field bits<7> SI = si;
64 field bits<7> VI = vi;
67 class sopk <bits<5> si, bits<5> vi = si> {
68 field bits<5> SI = si;
69 field bits<5> VI = vi;
72 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
73 // in AMDGPUInstrInfo.cpp
80 //===----------------------------------------------------------------------===//
82 //===----------------------------------------------------------------------===//
84 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
85 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
86 [SDNPMayLoad, SDNPMemOperand]
89 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
91 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
92 SDTCisVT<1, iAny>, // vdata(VGPR)
93 SDTCisVT<2, i32>, // num_channels(imm)
94 SDTCisVT<3, i32>, // vaddr(VGPR)
95 SDTCisVT<4, i32>, // soffset(SGPR)
96 SDTCisVT<5, i32>, // inst_offset(imm)
97 SDTCisVT<6, i32>, // dfmt(imm)
98 SDTCisVT<7, i32>, // nfmt(imm)
99 SDTCisVT<8, i32>, // offen(imm)
100 SDTCisVT<9, i32>, // idxen(imm)
101 SDTCisVT<10, i32>, // glc(imm)
102 SDTCisVT<11, i32>, // slc(imm)
103 SDTCisVT<12, i32> // tfe(imm)
105 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
108 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
109 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
113 class SDSample<string opcode> : SDNode <opcode,
114 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
115 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
118 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
119 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
120 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
121 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
123 def SIconstdata_ptr : SDNode<
124 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
127 //===----------------------------------------------------------------------===//
128 // SDNodes and PatFrag for local loads and stores to enable s_mov_b32 m0, -1
129 // to be glued to the memory instructions.
130 //===----------------------------------------------------------------------===//
132 def SIld_local : SDNode <"ISD::LOAD", SDTLoad,
133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
136 def si_ld_local : PatFrag <(ops node:$ptr), (SIld_local node:$ptr), [{
137 return isLocalLoad(cast<LoadSDNode>(N));
140 def si_load_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{
141 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
142 cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
145 def si_load_local_align8 : Aligned8Bytes <
146 (ops node:$ptr), (si_load_local node:$ptr)
149 def si_sextload_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{
150 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
152 def si_az_extload_local : AZExtLoadBase <si_ld_local>;
154 multiclass SIExtLoadLocal <PatFrag ld_node> {
156 def _i8 : PatFrag <(ops node:$ptr), (ld_node node:$ptr),
157 [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;}]
160 def _i16 : PatFrag <(ops node:$ptr), (ld_node node:$ptr),
161 [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;}]
165 defm si_sextload_local : SIExtLoadLocal <si_sextload_local>;
166 defm si_az_extload_local : SIExtLoadLocal <si_az_extload_local>;
168 def SIst_local : SDNode <"ISD::STORE", SDTStore,
169 [SDNPHasChain, SDNPMayStore, SDNPMemOperand, SDNPInGlue]
172 def si_st_local : PatFrag <
173 (ops node:$val, node:$ptr), (SIst_local node:$val, node:$ptr), [{
174 return isLocalStore(cast<StoreSDNode>(N));
177 def si_store_local : PatFrag <
178 (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{
179 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
180 !cast<StoreSDNode>(N)->isTruncatingStore();
183 def si_store_local_align8 : Aligned8Bytes <
184 (ops node:$val, node:$ptr), (si_store_local node:$val, node:$ptr)
187 def si_truncstore_local : PatFrag <
188 (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{
189 return cast<StoreSDNode>(N)->isTruncatingStore();
192 def si_truncstore_local_i8 : PatFrag <
193 (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{
194 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
197 def si_truncstore_local_i16 : PatFrag <
198 (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{
199 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
202 multiclass SIAtomicM0Glue2 <string op_name> {
204 def _glue : SDNode <"ISD::ATOMIC_"#op_name, SDTAtomic2,
205 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
208 def _local : local_binary_atomic_op <!cast<SDNode>(NAME#"_glue")>;
211 defm si_atomic_load_add : SIAtomicM0Glue2 <"LOAD_ADD">;
212 defm si_atomic_load_and : SIAtomicM0Glue2 <"LOAD_AND">;
213 defm si_atomic_load_min : SIAtomicM0Glue2 <"LOAD_MIN">;
214 defm si_atomic_load_max : SIAtomicM0Glue2 <"LOAD_MAX">;
215 defm si_atomic_load_or : SIAtomicM0Glue2 <"LOAD_OR">;
216 defm si_atomic_load_sub : SIAtomicM0Glue2 <"LOAD_SUB">;
217 defm si_atomic_load_xor : SIAtomicM0Glue2 <"LOAD_XOR">;
218 defm si_atomic_load_umin : SIAtomicM0Glue2 <"LOAD_UMIN">;
219 defm si_atomic_load_umax : SIAtomicM0Glue2 <"LOAD_UMAX">;
220 defm si_atomic_swap : SIAtomicM0Glue2 <"SWAP">;
222 def si_atomic_cmp_swap_glue : SDNode <"ISD::ATOMIC_CMP_SWAP", SDTAtomic3,
223 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
226 defm si_atomic_cmp_swap : AtomicCmpSwapLocal <si_atomic_cmp_swap_glue>;
228 // Transformation function, extract the lower 32bit of a 64bit immediate
229 def LO32 : SDNodeXForm<imm, [{
230 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, SDLoc(N),
234 def LO32f : SDNodeXForm<fpimm, [{
235 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
236 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
239 // Transformation function, extract the upper 32bit of a 64bit immediate
240 def HI32 : SDNodeXForm<imm, [{
241 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, SDLoc(N), MVT::i32);
244 def HI32f : SDNodeXForm<fpimm, [{
245 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
246 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), SDLoc(N),
250 def IMM8bitDWORD : PatLeaf <(imm),
251 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
254 def as_dword_i32imm : SDNodeXForm<imm, [{
255 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, SDLoc(N), MVT::i32);
258 def as_i1imm : SDNodeXForm<imm, [{
259 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i1);
262 def as_i8imm : SDNodeXForm<imm, [{
263 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i8);
266 def as_i16imm : SDNodeXForm<imm, [{
267 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
270 def as_i32imm: SDNodeXForm<imm, [{
271 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
274 def as_i64imm: SDNodeXForm<imm, [{
275 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
278 // Copied from the AArch64 backend:
279 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
280 return CurDAG->getTargetConstant(
281 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
284 // Copied from the AArch64 backend:
285 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
286 return CurDAG->getTargetConstant(
287 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
290 def IMM8bit : PatLeaf <(imm),
291 [{return isUInt<8>(N->getZExtValue());}]
294 def IMM12bit : PatLeaf <(imm),
295 [{return isUInt<12>(N->getZExtValue());}]
298 def IMM16bit : PatLeaf <(imm),
299 [{return isUInt<16>(N->getZExtValue());}]
302 def IMM20bit : PatLeaf <(imm),
303 [{return isUInt<20>(N->getZExtValue());}]
306 def IMM32bit : PatLeaf <(imm),
307 [{return isUInt<32>(N->getZExtValue());}]
310 def mubuf_vaddr_offset : PatFrag<
311 (ops node:$ptr, node:$offset, node:$imm_offset),
312 (add (add node:$ptr, node:$offset), node:$imm_offset)
315 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
316 return isInlineImmediate(N);
319 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
320 return isInlineImmediate(N);
323 class SGPRImm <dag frag> : PatLeaf<frag, [{
324 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
327 const SIRegisterInfo *SIRI =
328 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
329 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
331 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
338 //===----------------------------------------------------------------------===//
340 //===----------------------------------------------------------------------===//
342 def FRAMEri32 : Operand<iPTR> {
343 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
346 def SoppBrTarget : AsmOperandClass {
347 let Name = "SoppBrTarget";
348 let ParserMethod = "parseSOppBrTarget";
351 def sopp_brtarget : Operand<OtherVT> {
352 let EncoderMethod = "getSOPPBrEncoding";
353 let OperandType = "OPERAND_PCREL";
354 let ParserMatchClass = SoppBrTarget;
357 include "SIInstrFormats.td"
358 include "VIInstrFormats.td"
360 def MubufOffsetMatchClass : AsmOperandClass {
361 let Name = "MubufOffset";
362 let ParserMethod = "parseMubufOptionalOps";
363 let RenderMethod = "addImmOperands";
366 class DSOffsetBaseMatchClass <string parser> : AsmOperandClass {
367 let Name = "DSOffset"#parser;
368 let ParserMethod = parser;
369 let RenderMethod = "addImmOperands";
370 let PredicateMethod = "isDSOffset";
373 def DSOffsetMatchClass : DSOffsetBaseMatchClass <"parseDSOptionalOps">;
374 def DSOffsetGDSMatchClass : DSOffsetBaseMatchClass <"parseDSOffsetOptional">;
376 def DSOffset01MatchClass : AsmOperandClass {
377 let Name = "DSOffset1";
378 let ParserMethod = "parseDSOff01OptionalOps";
379 let RenderMethod = "addImmOperands";
380 let PredicateMethod = "isDSOffset01";
383 class GDSBaseMatchClass <string parser> : AsmOperandClass {
384 let Name = "GDS"#parser;
385 let PredicateMethod = "isImm";
386 let ParserMethod = parser;
387 let RenderMethod = "addImmOperands";
390 def GDSMatchClass : GDSBaseMatchClass <"parseDSOptionalOps">;
391 def GDS01MatchClass : GDSBaseMatchClass <"parseDSOff01OptionalOps">;
393 class GLCBaseMatchClass <string parser> : AsmOperandClass {
394 let Name = "GLC"#parser;
395 let PredicateMethod = "isImm";
396 let ParserMethod = parser;
397 let RenderMethod = "addImmOperands";
400 def GLCMubufMatchClass : GLCBaseMatchClass <"parseMubufOptionalOps">;
401 def GLCFlatMatchClass : GLCBaseMatchClass <"parseFlatOptionalOps">;
403 class SLCBaseMatchClass <string parser> : AsmOperandClass {
404 let Name = "SLC"#parser;
405 let PredicateMethod = "isImm";
406 let ParserMethod = parser;
407 let RenderMethod = "addImmOperands";
410 def SLCMubufMatchClass : SLCBaseMatchClass <"parseMubufOptionalOps">;
411 def SLCFlatMatchClass : SLCBaseMatchClass <"parseFlatOptionalOps">;
412 def SLCFlatAtomicMatchClass : SLCBaseMatchClass <"parseFlatAtomicOptionalOps">;
414 class TFEBaseMatchClass <string parser> : AsmOperandClass {
415 let Name = "TFE"#parser;
416 let PredicateMethod = "isImm";
417 let ParserMethod = parser;
418 let RenderMethod = "addImmOperands";
421 def TFEMubufMatchClass : TFEBaseMatchClass <"parseMubufOptionalOps">;
422 def TFEFlatMatchClass : TFEBaseMatchClass <"parseFlatOptionalOps">;
423 def TFEFlatAtomicMatchClass : TFEBaseMatchClass <"parseFlatAtomicOptionalOps">;
425 def OModMatchClass : AsmOperandClass {
427 let PredicateMethod = "isImm";
428 let ParserMethod = "parseVOP3OptionalOps";
429 let RenderMethod = "addImmOperands";
432 def ClampMatchClass : AsmOperandClass {
434 let PredicateMethod = "isImm";
435 let ParserMethod = "parseVOP3OptionalOps";
436 let RenderMethod = "addImmOperands";
439 let OperandType = "OPERAND_IMMEDIATE" in {
441 def offen : Operand<i1> {
442 let PrintMethod = "printOffen";
444 def idxen : Operand<i1> {
445 let PrintMethod = "printIdxen";
447 def addr64 : Operand<i1> {
448 let PrintMethod = "printAddr64";
450 def mbuf_offset : Operand<i16> {
451 let PrintMethod = "printMBUFOffset";
452 let ParserMatchClass = MubufOffsetMatchClass;
454 class ds_offset_base <AsmOperandClass mc> : Operand<i16> {
455 let PrintMethod = "printDSOffset";
456 let ParserMatchClass = mc;
458 def ds_offset : ds_offset_base <DSOffsetMatchClass>;
459 def ds_offset_gds : ds_offset_base <DSOffsetGDSMatchClass>;
461 def ds_offset0 : Operand<i8> {
462 let PrintMethod = "printDSOffset0";
463 let ParserMatchClass = DSOffset01MatchClass;
465 def ds_offset1 : Operand<i8> {
466 let PrintMethod = "printDSOffset1";
467 let ParserMatchClass = DSOffset01MatchClass;
469 class gds_base <AsmOperandClass mc> : Operand <i1> {
470 let PrintMethod = "printGDS";
471 let ParserMatchClass = mc;
473 def gds : gds_base <GDSMatchClass>;
475 def gds01 : gds_base <GDS01MatchClass>;
477 class glc_base <AsmOperandClass mc> : Operand <i1> {
478 let PrintMethod = "printGLC";
479 let ParserMatchClass = mc;
482 def glc : glc_base <GLCMubufMatchClass>;
483 def glc_flat : glc_base <GLCFlatMatchClass>;
485 class slc_base <AsmOperandClass mc> : Operand <i1> {
486 let PrintMethod = "printSLC";
487 let ParserMatchClass = mc;
490 def slc : slc_base <SLCMubufMatchClass>;
491 def slc_flat : slc_base <SLCFlatMatchClass>;
492 def slc_flat_atomic : slc_base <SLCFlatAtomicMatchClass>;
494 class tfe_base <AsmOperandClass mc> : Operand <i1> {
495 let PrintMethod = "printTFE";
496 let ParserMatchClass = mc;
499 def tfe : tfe_base <TFEMubufMatchClass>;
500 def tfe_flat : tfe_base <TFEFlatMatchClass>;
501 def tfe_flat_atomic : tfe_base <TFEFlatAtomicMatchClass>;
503 def omod : Operand <i32> {
504 let PrintMethod = "printOModSI";
505 let ParserMatchClass = OModMatchClass;
508 def ClampMod : Operand <i1> {
509 let PrintMethod = "printClampSI";
510 let ParserMatchClass = ClampMatchClass;
513 } // End OperandType = "OPERAND_IMMEDIATE"
515 def VOPDstS64 : VOPDstOperand <SReg_64>;
517 //===----------------------------------------------------------------------===//
519 //===----------------------------------------------------------------------===//
521 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
522 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
524 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
525 def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">;
526 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
527 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
528 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
529 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
531 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
532 def VOP3NoMods0 : ComplexPattern<untyped, 4, "SelectVOP3NoMods0">;
533 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
534 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
535 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
536 def VOP3NoMods : ComplexPattern<untyped, 2, "SelectVOP3NoMods">;
538 //===----------------------------------------------------------------------===//
539 // SI assembler operands
540 //===----------------------------------------------------------------------===//
561 //===----------------------------------------------------------------------===//
563 // SI Instruction multiclass helpers.
565 // Instructions with _32 take 32-bit operands.
566 // Instructions with _64 take 64-bit operands.
568 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
569 // encoding is the standard encoding, but instruction that make use of
570 // any of the instruction modifiers must use the 64-bit encoding.
572 // Instructions with _e32 use the 32-bit encoding.
573 // Instructions with _e64 use the 64-bit encoding.
575 //===----------------------------------------------------------------------===//
577 class SIMCInstr <string pseudo, int subtarget> {
578 string PseudoInstr = pseudo;
579 int Subtarget = subtarget;
582 //===----------------------------------------------------------------------===//
584 //===----------------------------------------------------------------------===//
586 class EXPCommon : InstSI<
588 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
589 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
590 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
599 let isPseudo = 1, isCodeGenOnly = 1 in {
600 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
603 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
605 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
608 //===----------------------------------------------------------------------===//
610 //===----------------------------------------------------------------------===//
612 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
613 SOP1 <outs, ins, "", pattern>,
614 SIMCInstr<opName, SISubtarget.NONE> {
616 let isCodeGenOnly = 1;
619 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
620 SOP1 <outs, ins, asm, []>,
622 SIMCInstr<opName, SISubtarget.SI> {
623 let isCodeGenOnly = 0;
624 let AssemblerPredicates = [isSICI];
627 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
628 SOP1 <outs, ins, asm, []>,
630 SIMCInstr<opName, SISubtarget.VI> {
631 let isCodeGenOnly = 0;
632 let AssemblerPredicates = [isVI];
635 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
638 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
640 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
642 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
646 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
647 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
648 opName#" $dst, $src0", pattern
651 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
652 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
653 opName#" $dst, $src0", pattern
656 // no input, 64-bit output.
657 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
658 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
660 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
665 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
671 // 64-bit input, no output
672 multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
673 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
675 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
680 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
686 // 64-bit input, 32-bit output.
687 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
688 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
689 opName#" $dst, $src0", pattern
692 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
693 SOP2<outs, ins, "", pattern>,
694 SIMCInstr<opName, SISubtarget.NONE> {
696 let isCodeGenOnly = 1;
699 // Pseudo instructions have no encodings, but adding this field here allows
701 // let sdst = xxx in {
702 // for multiclasses that include both real and pseudo instructions.
703 field bits<7> sdst = 0;
706 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
707 SOP2<outs, ins, asm, []>,
709 SIMCInstr<opName, SISubtarget.SI> {
710 let AssemblerPredicates = [isSICI];
713 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
714 SOP2<outs, ins, asm, []>,
716 SIMCInstr<opName, SISubtarget.VI> {
717 let AssemblerPredicates = [isVI];
720 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
721 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
722 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
724 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
725 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
726 opName#" $dst, $src0, $src1 [$scc]">;
728 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
729 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
730 opName#" $dst, $src0, $src1 [$scc]">;
733 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
736 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
738 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
740 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
744 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
745 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
746 opName#" $dst, $src0, $src1", pattern
749 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
750 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
751 opName#" $dst, $src0, $src1", pattern
754 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
755 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
756 opName#" $dst, $src0, $src1", pattern
759 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
760 string opName, PatLeaf cond> : SOPC <
761 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
762 opName#" $src0, $src1", []>;
764 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
765 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
767 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
768 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
770 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
771 SOPK <outs, ins, "", pattern>,
772 SIMCInstr<opName, SISubtarget.NONE> {
774 let isCodeGenOnly = 1;
777 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
778 SOPK <outs, ins, asm, []>,
780 SIMCInstr<opName, SISubtarget.SI> {
781 let AssemblerPredicates = [isSICI];
782 let isCodeGenOnly = 0;
785 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
786 SOPK <outs, ins, asm, []>,
788 SIMCInstr<opName, SISubtarget.VI> {
789 let AssemblerPredicates = [isVI];
790 let isCodeGenOnly = 0;
793 multiclass SOPK_m <sopk op, string opName, dag outs, dag ins, string opAsm,
794 string asm = opName#opAsm> {
795 def "" : SOPK_Pseudo <opName, outs, ins, []>;
797 def _si : SOPK_Real_si <op, opName, outs, ins, asm>;
799 def _vi : SOPK_Real_vi <op, opName, outs, ins, asm>;
803 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
804 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
807 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
808 opName#" $dst, $src0">;
810 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
811 opName#" $dst, $src0">;
814 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
815 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
816 (ins SReg_32:$src0, u16imm:$src1), pattern>;
818 let DisableEncoding = "$dst" in {
819 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
820 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16">;
822 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
823 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16">;
827 multiclass SOPK_32TIE <sopk op, string opName, list<dag> pattern> : SOPK_m <
828 op, opName, (outs SReg_32:$sdst), (ins SReg_32:$src0, u16imm:$simm16),
832 multiclass SOPK_IMM32 <sopk op, string opName, dag outs, dag ins,
833 string argAsm, string asm = opName#argAsm> {
835 def "" : SOPK_Pseudo <opName, outs, ins, []>;
837 def _si : SOPK <outs, ins, asm, []>,
839 SIMCInstr<opName, SISubtarget.SI> {
840 let AssemblerPredicates = [isSICI];
841 let isCodeGenOnly = 0;
844 def _vi : SOPK <outs, ins, asm, []>,
846 SIMCInstr<opName, SISubtarget.VI> {
847 let AssemblerPredicates = [isVI];
848 let isCodeGenOnly = 0;
851 //===----------------------------------------------------------------------===//
853 //===----------------------------------------------------------------------===//
855 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
856 SMRD <outs, ins, "", pattern>,
857 SIMCInstr<opName, SISubtarget.NONE> {
859 let isCodeGenOnly = 1;
862 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
864 SMRD <outs, ins, asm, []>,
866 SIMCInstr<opName, SISubtarget.SI> {
867 let AssemblerPredicates = [isSICI];
870 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
872 SMRD <outs, ins, asm, []>,
874 SIMCInstr<opName, SISubtarget.VI> {
875 let AssemblerPredicates = [isVI];
878 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
879 string asm, list<dag> pattern> {
881 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
883 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
885 // glc is only applicable to scalar stores, which are not yet
888 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
892 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
893 RegisterClass dstClass> {
895 op, opName#"_IMM", 1, (outs dstClass:$dst),
896 (ins baseClass:$sbase, u32imm:$offset),
897 opName#" $dst, $sbase, $offset", []
900 defm _SGPR : SMRD_m <
901 op, opName#"_SGPR", 0, (outs dstClass:$dst),
902 (ins baseClass:$sbase, SReg_32:$soff),
903 opName#" $dst, $sbase, $soff", []
907 //===----------------------------------------------------------------------===//
908 // Vector ALU classes
909 //===----------------------------------------------------------------------===//
911 // This must always be right before the operand being input modified.
912 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
913 let PrintMethod = "printOperandAndMods";
916 def InputModsMatchClass : AsmOperandClass {
917 let Name = "RegWithInputMods";
920 def InputModsNoDefault : Operand <i32> {
921 let PrintMethod = "printOperandAndMods";
922 let ParserMatchClass = InputModsMatchClass;
925 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
927 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
928 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
932 // Returns the register class to use for the destination of VOP[123C]
933 // instructions for the given VT.
934 class getVALUDstForVT<ValueType VT> {
935 RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
936 !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
937 VOPDstOperand<SReg_64>)); // else VT == i1
940 // Returns the register class to use for source 0 of VOP[12C]
941 // instructions for the given VT.
942 class getVOPSrc0ForVT<ValueType VT> {
943 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
946 // Returns the register class to use for source 1 of VOP[12C] for the
948 class getVOPSrc1ForVT<ValueType VT> {
949 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
952 // Returns the register class to use for sources of VOP3 instructions for the
954 class getVOP3SrcForVT<ValueType VT> {
955 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
958 // Returns 1 if the source arguments have modifiers, 0 if they do not.
959 class hasModifiers<ValueType SrcVT> {
960 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
961 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
964 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
965 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
966 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
967 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
971 // Returns the input arguments for VOP3 instructions for the given SrcVT.
972 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
973 RegisterOperand Src2RC, int NumSrcArgs,
977 !if (!eq(NumSrcArgs, 1),
978 !if (!eq(HasModifiers, 1),
979 // VOP1 with modifiers
980 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
981 ClampMod:$clamp, omod:$omod)
983 // VOP1 without modifiers
986 !if (!eq(NumSrcArgs, 2),
987 !if (!eq(HasModifiers, 1),
988 // VOP 2 with modifiers
989 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
990 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
991 ClampMod:$clamp, omod:$omod)
993 // VOP2 without modifiers
994 (ins Src0RC:$src0, Src1RC:$src1)
996 /* NumSrcArgs == 3 */,
997 !if (!eq(HasModifiers, 1),
998 // VOP3 with modifiers
999 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
1000 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
1001 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
1002 ClampMod:$clamp, omod:$omod)
1004 // VOP3 without modifiers
1005 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
1009 // Returns the assembly string for the inputs and outputs of a VOP[12C]
1010 // instruction. This does not add the _e32 suffix, so it can be reused
1012 class getAsm32 <int NumSrcArgs> {
1013 string src1 = ", $src1";
1014 string src2 = ", $src2";
1015 string ret = "$dst, $src0"#
1016 !if(!eq(NumSrcArgs, 1), "", src1)#
1017 !if(!eq(NumSrcArgs, 3), src2, "");
1020 // Returns the assembly string for the inputs and outputs of a VOP3
1022 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
1023 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
1024 string src1 = !if(!eq(NumSrcArgs, 1), "",
1025 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
1026 " $src1_modifiers,"));
1027 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
1029 !if(!eq(HasModifiers, 0),
1030 getAsm32<NumSrcArgs>.ret,
1031 "$dst, "#src0#src1#src2#"$clamp"#"$omod");
1035 class VOPProfile <list<ValueType> _ArgVT> {
1037 field list<ValueType> ArgVT = _ArgVT;
1039 field ValueType DstVT = ArgVT[0];
1040 field ValueType Src0VT = ArgVT[1];
1041 field ValueType Src1VT = ArgVT[2];
1042 field ValueType Src2VT = ArgVT[3];
1043 field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
1044 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
1045 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
1046 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
1047 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
1048 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
1050 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
1051 field bit HasModifiers = hasModifiers<Src0VT>.ret;
1053 field dag Outs = (outs DstRC:$dst);
1055 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
1056 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
1059 field string Asm32 = getAsm32<NumSrcArgs>.ret;
1060 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
1063 // FIXME: I think these F16/I16 profiles will need to use f16/i16 types in order
1064 // for the instruction patterns to work.
1065 def VOP_F16_F16 : VOPProfile <[f32, f32, untyped, untyped]>;
1066 def VOP_F16_I16 : VOPProfile <[f32, i32, untyped, untyped]>;
1067 def VOP_I16_F16 : VOPProfile <[i32, f32, untyped, untyped]>;
1069 def VOP_F16_F16_F16 : VOPProfile <[f32, f32, f32, untyped]>;
1070 def VOP_F16_F16_I16 : VOPProfile <[f32, f32, i32, untyped]>;
1071 def VOP_I16_I16_I16 : VOPProfile <[i32, i32, i32, untyped]>;
1073 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
1074 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
1075 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
1076 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
1077 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
1078 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
1079 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
1080 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
1081 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
1083 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
1084 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
1085 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
1086 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
1087 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
1088 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
1089 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
1090 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
1091 let Src0RC32 = VCSrc_32;
1094 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
1095 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
1096 let Asm64 = "$dst, $src0_modifiers, $src1";
1099 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
1100 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
1101 let Asm64 = "$dst, $src0_modifiers, $src1";
1104 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
1105 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
1106 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
1107 def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> {
1108 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VCCReg:$src2);
1109 let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
1110 let Asm64 = "$dst, $src0, $src1, $src2";
1113 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
1114 def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {
1115 field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
1116 field string Asm = "$dst, $src0, $vsrc1, $src2";
1118 def VOP_MAC : VOPProfile <[f32, f32, f32, f32]> {
1119 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);
1120 let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3,
1122 let Asm32 = getAsm32<2>.ret;
1123 let Asm64 = getAsm64<2, HasModifiers>.ret;
1125 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
1126 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
1127 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
1130 class VOP <string opName> {
1131 string OpName = opName;
1134 class VOP2_REV <string revOp, bit isOrig> {
1135 string RevOp = revOp;
1136 bit IsOrig = isOrig;
1139 class AtomicNoRet <string noRetOp, bit isRet> {
1140 string NoRetOp = noRetOp;
1144 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1145 VOP1Common <outs, ins, "", pattern>,
1147 SIMCInstr <opName#"_e32", SISubtarget.NONE>,
1148 MnemonicAlias<opName#"_e32", opName> {
1150 let isCodeGenOnly = 1;
1156 class VOP1_Real_si <string opName, vop1 op, dag outs, dag ins, string asm> :
1157 VOP1<op.SI, outs, ins, asm, []>,
1158 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1159 let AssemblerPredicate = SIAssemblerPredicate;
1162 class VOP1_Real_vi <string opName, vop1 op, dag outs, dag ins, string asm> :
1163 VOP1<op.VI, outs, ins, asm, []>,
1164 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1165 let AssemblerPredicates = [isVI];
1168 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
1170 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
1172 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
1174 def _vi : VOP1_Real_vi <opName, op, outs, ins, asm>;
1177 multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
1179 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
1181 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
1184 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1185 VOP2Common <outs, ins, "", pattern>,
1187 SIMCInstr<opName#"_e32", SISubtarget.NONE>,
1188 MnemonicAlias<opName#"_e32", opName> {
1190 let isCodeGenOnly = 1;
1193 class VOP2_Real_si <string opName, vop2 op, dag outs, dag ins, string asm> :
1194 VOP2 <op.SI, outs, ins, opName#asm, []>,
1195 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1196 let AssemblerPredicates = [isSICI];
1199 class VOP2_Real_vi <string opName, vop2 op, dag outs, dag ins, string asm> :
1200 VOP2 <op.VI, outs, ins, opName#asm, []>,
1201 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1202 let AssemblerPredicates = [isVI];
1205 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
1206 string opName, string revOp> {
1207 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
1208 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
1210 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
1213 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
1214 string opName, string revOp> {
1215 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
1216 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
1218 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
1220 def _vi : VOP2_Real_vi <opName, op, outs, ins, asm>;
1224 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
1226 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
1227 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
1228 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0);
1229 bits<2> omod = !if(HasModifiers, ?, 0);
1230 bits<1> clamp = !if(HasModifiers, ?, 0);
1231 bits<9> src1 = !if(HasSrc1, ?, 0);
1232 bits<9> src2 = !if(HasSrc2, ?, 0);
1235 class VOP3DisableModFields <bit HasSrc0Mods,
1236 bit HasSrc1Mods = 0,
1237 bit HasSrc2Mods = 0,
1238 bit HasOutputMods = 0> {
1239 bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0);
1240 bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0);
1241 bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0);
1242 bits<2> omod = !if(HasOutputMods, ?, 0);
1243 bits<1> clamp = !if(HasOutputMods, ?, 0);
1246 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1247 VOP3Common <outs, ins, "", pattern>,
1249 SIMCInstr<opName#"_e64", SISubtarget.NONE>,
1250 MnemonicAlias<opName#"_e64", opName> {
1252 let isCodeGenOnly = 1;
1255 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1256 VOP3Common <outs, ins, asm, []>,
1258 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1259 let AssemblerPredicates = [isSICI];
1262 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1263 VOP3Common <outs, ins, asm, []>,
1265 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1266 let AssemblerPredicates = [isVI];
1269 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1270 VOP3Common <outs, ins, asm, []>,
1272 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1273 let AssemblerPredicates = [isSICI];
1276 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1277 VOP3Common <outs, ins, asm, []>,
1279 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1280 let AssemblerPredicates = [isVI];
1283 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
1284 string opName, int NumSrcArgs, bit HasMods = 1> {
1286 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1288 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1289 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1290 !if(!eq(NumSrcArgs, 2), 0, 1),
1292 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1293 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1294 !if(!eq(NumSrcArgs, 2), 0, 1),
1298 // VOP3_m without source modifiers
1299 multiclass VOP3_m_nomods <vop op, dag outs, dag ins, string asm, list<dag> pattern,
1300 string opName, int NumSrcArgs, bit HasMods = 1> {
1302 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1304 let src0_modifiers = 0,
1309 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
1310 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
1314 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
1315 list<dag> pattern, string opName, bit HasMods = 1> {
1317 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1319 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1320 VOP3DisableFields<0, 0, HasMods>;
1322 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1323 VOP3DisableFields<0, 0, HasMods>;
1326 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
1327 list<dag> pattern, string opName, bit HasMods = 1> {
1329 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1331 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1332 VOP3DisableFields<0, 0, HasMods>;
1333 // No VI instruction. This class is for SI only.
1336 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
1337 list<dag> pattern, string opName, string revOp,
1338 bit HasMods = 1, bit UseFullOp = 0> {
1340 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1341 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1343 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1344 VOP3DisableFields<1, 0, HasMods>;
1346 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1347 VOP3DisableFields<1, 0, HasMods>;
1350 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
1351 list<dag> pattern, string opName, string revOp,
1352 bit HasMods = 1, bit UseFullOp = 0> {
1354 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1355 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1357 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1358 VOP3DisableFields<1, 0, HasMods>;
1360 // No VI instruction. This class is for SI only.
1363 // XXX - Is v_div_scale_{f32|f64} only available in vop3b without
1364 // option of implicit vcc use?
1365 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
1366 list<dag> pattern, string opName, string revOp,
1367 bit HasMods = 1, bit UseFullOp = 0> {
1368 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1369 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1371 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
1372 // can write it into any SGPR. We currently don't use the carry out,
1373 // so for now hardcode it to VCC as well.
1374 let sdst = SIOperand.VCC, Defs = [VCC] in {
1375 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1376 VOP3DisableFields<1, 0, HasMods>;
1378 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1379 VOP3DisableFields<1, 0, HasMods>;
1380 } // End sdst = SIOperand.VCC, Defs = [VCC]
1383 multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
1384 list<dag> pattern, string opName, string revOp,
1385 bit HasMods = 1, bit UseFullOp = 0> {
1386 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1389 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1390 VOP3DisableFields<1, 1, HasMods>;
1392 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1393 VOP3DisableFields<1, 1, HasMods>;
1396 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1397 list<dag> pattern, string opName,
1398 bit HasMods, bit defExec, string revOp> {
1400 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1401 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1403 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1404 VOP3DisableFields<1, 0, HasMods> {
1405 let Defs = !if(defExec, [EXEC], []);
1408 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1409 VOP3DisableFields<1, 0, HasMods> {
1410 let Defs = !if(defExec, [EXEC], []);
1414 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1415 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1416 string asm, list<dag> pattern = []> {
1417 let isPseudo = 1, isCodeGenOnly = 1 in {
1418 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1419 SIMCInstr<opName, SISubtarget.NONE>;
1422 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1423 SIMCInstr <opName, SISubtarget.SI> {
1424 let AssemblerPredicates = [isSICI];
1427 def _vi : VOP3Common <outs, ins, asm, []>,
1429 VOP3DisableFields <1, 0, 0>,
1430 SIMCInstr <opName, SISubtarget.VI> {
1431 let AssemblerPredicates = [isVI];
1435 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1436 dag ins32, string asm32, list<dag> pat32,
1437 dag ins64, string asm64, list<dag> pat64,
1440 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1442 defm _e64 : VOP3_1_m <op, outs, ins64, opName#asm64, pat64, opName, HasMods>;
1445 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1446 SDPatternOperator node = null_frag> : VOP1_Helper <
1448 P.Ins32, P.Asm32, [],
1451 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1452 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1453 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1457 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1458 SDPatternOperator node = null_frag> {
1460 defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>;
1462 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1464 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1465 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1466 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1467 opName, P.HasModifiers>;
1470 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1471 dag ins32, string asm32, list<dag> pat32,
1472 dag ins64, string asm64, list<dag> pat64,
1473 string revOp, bit HasMods> {
1474 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1476 defm _e64 : VOP3_2_m <op,
1477 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1481 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1482 SDPatternOperator node = null_frag,
1483 string revOp = opName> : VOP2_Helper <
1485 P.Ins32, P.Asm32, [],
1489 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1490 i1:$clamp, i32:$omod)),
1491 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1492 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1493 revOp, P.HasModifiers
1496 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1497 SDPatternOperator node = null_frag,
1498 string revOp = opName> {
1499 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1501 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1504 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1505 i1:$clamp, i32:$omod)),
1506 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1507 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1508 opName, revOp, P.HasModifiers>;
1511 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1512 dag ins32, string asm32, list<dag> pat32,
1513 dag ins64, string asm64, list<dag> pat64,
1514 string revOp, bit HasMods> {
1516 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1518 defm _e64 : VOP3b_2_m <op,
1519 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1523 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1524 SDPatternOperator node = null_frag,
1525 string revOp = opName> : VOP2b_Helper <
1527 P.Ins32, P.Asm32, [],
1531 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1532 i1:$clamp, i32:$omod)),
1533 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1534 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1535 revOp, P.HasModifiers
1538 // A VOP2 instruction that is VOP3-only on VI.
1539 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1540 dag ins32, string asm32, list<dag> pat32,
1541 dag ins64, string asm64, list<dag> pat64,
1542 string revOp, bit HasMods> {
1543 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1545 defm _e64 : VOP3_2_m <op, outs, ins64, opName#asm64, pat64, opName,
1549 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1550 SDPatternOperator node = null_frag,
1551 string revOp = opName>
1554 P.Ins32, P.Asm32, [],
1558 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1559 i1:$clamp, i32:$omod)),
1560 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1561 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1562 revOp, P.HasModifiers
1565 multiclass VOP2MADK <vop2 op, string opName, list<dag> pattern = []> {
1567 def "" : VOP2_Pseudo <VOP_MADK.Outs, VOP_MADK.Ins, pattern, opName>;
1569 let isCodeGenOnly = 0 in {
1570 def _si : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1571 !strconcat(opName, VOP_MADK.Asm), []>,
1572 SIMCInstr <opName#"_e32", SISubtarget.SI>,
1573 VOP2_MADKe <op.SI> {
1574 let AssemblerPredicates = [isSICI];
1577 def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1578 !strconcat(opName, VOP_MADK.Asm), []>,
1579 SIMCInstr <opName#"_e32", SISubtarget.VI>,
1580 VOP2_MADKe <op.VI> {
1581 let AssemblerPredicates = [isVI];
1583 } // End isCodeGenOnly = 0
1586 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1587 VOPCCommon <ins, "", pattern>,
1589 SIMCInstr<opName#"_e32", SISubtarget.NONE>,
1590 MnemonicAlias<opName#"_e32", opName> {
1592 let isCodeGenOnly = 1;
1595 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1596 string opName, bit DefExec, string revOpName = ""> {
1597 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1599 def _si : VOPC<op.SI, ins, asm, []>,
1600 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1601 let Defs = !if(DefExec, [EXEC], []);
1602 let hasSideEffects = DefExec;
1605 def _vi : VOPC<op.VI, ins, asm, []>,
1606 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1607 let Defs = !if(DefExec, [EXEC], []);
1608 let hasSideEffects = DefExec;
1612 multiclass VOPC_Helper <vopc op, string opName,
1613 dag ins32, string asm32, list<dag> pat32,
1614 dag out64, dag ins64, string asm64, list<dag> pat64,
1615 bit HasMods, bit DefExec, string revOp> {
1616 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1618 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1619 opName, HasMods, DefExec, revOp>;
1622 // Special case for class instructions which only have modifiers on
1623 // the 1st source operand.
1624 multiclass VOPC_Class_Helper <vopc op, string opName,
1625 dag ins32, string asm32, list<dag> pat32,
1626 dag out64, dag ins64, string asm64, list<dag> pat64,
1627 bit HasMods, bit DefExec, string revOp> {
1628 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1630 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1631 opName, HasMods, DefExec, revOp>,
1632 VOP3DisableModFields<1, 0, 0>;
1635 multiclass VOPCInst <vopc op, string opName,
1636 VOPProfile P, PatLeaf cond = COND_NULL,
1637 string revOp = opName,
1638 bit DefExec = 0> : VOPC_Helper <
1640 P.Ins32, P.Asm32, [],
1641 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1644 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1645 i1:$clamp, i32:$omod)),
1646 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1648 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1649 P.HasModifiers, DefExec, revOp
1652 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1653 bit DefExec = 0> : VOPC_Class_Helper <
1655 P.Ins32, P.Asm32, [],
1656 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1659 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1660 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1661 P.HasModifiers, DefExec, opName
1665 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1666 VOPCInst <op, opName, VOP_F32_F32_F32, cond, revOp>;
1668 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1669 VOPCInst <op, opName, VOP_F64_F64_F64, cond, revOp>;
1671 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1672 VOPCInst <op, opName, VOP_I32_I32_I32, cond, revOp>;
1674 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1675 VOPCInst <op, opName, VOP_I64_I64_I64, cond, revOp>;
1678 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1679 PatLeaf cond = COND_NULL,
1681 : VOPCInst <op, opName, P, cond, revOp, 1>;
1683 multiclass VOPCX_F32 <vopc op, string opName, string revOp = opName> :
1684 VOPCX <op, opName, VOP_F32_F32_F32, COND_NULL, revOp>;
1686 multiclass VOPCX_F64 <vopc op, string opName, string revOp = opName> :
1687 VOPCX <op, opName, VOP_F64_F64_F64, COND_NULL, revOp>;
1689 multiclass VOPCX_I32 <vopc op, string opName, string revOp = opName> :
1690 VOPCX <op, opName, VOP_I32_I32_I32, COND_NULL, revOp>;
1692 multiclass VOPCX_I64 <vopc op, string opName, string revOp = opName> :
1693 VOPCX <op, opName, VOP_I64_I64_I64, COND_NULL, revOp>;
1695 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1696 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1697 op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods
1700 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1701 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1703 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1704 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1706 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1707 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1709 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1710 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1712 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1713 SDPatternOperator node = null_frag> : VOP3_Helper <
1714 op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64,
1715 !if(!eq(P.NumSrcArgs, 3),
1718 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1719 i1:$clamp, i32:$omod)),
1720 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1721 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1722 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1724 !if(!eq(P.NumSrcArgs, 2),
1727 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1728 i1:$clamp, i32:$omod)),
1729 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1730 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1731 /* P.NumSrcArgs == 1 */,
1734 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1735 i1:$clamp, i32:$omod))))],
1736 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1737 P.NumSrcArgs, P.HasModifiers
1740 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1741 // only VOP instruction that implicitly reads VCC.
1742 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1744 SDPatternOperator node = null_frag> : VOP3_Helper <
1746 (outs P.DstRC.RegClass:$dst),
1747 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1748 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1749 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1752 "$dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1754 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1755 i1:$clamp, i32:$omod)),
1756 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1757 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1762 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1763 string opName, list<dag> pattern> :
1765 op, (outs vrc:$vdst, SReg_64:$sdst),
1766 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1767 InputModsNoDefault:$src1_modifiers, arc:$src1,
1768 InputModsNoDefault:$src2_modifiers, arc:$src2,
1769 ClampMod:$clamp, omod:$omod),
1770 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1771 opName, opName, 1, 1
1774 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1775 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1777 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1778 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1781 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1782 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1783 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1784 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1785 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1786 i32:$src1_modifiers, P.Src1VT:$src1,
1787 i32:$src2_modifiers, P.Src2VT:$src2,
1791 //===----------------------------------------------------------------------===//
1792 // Interpolation opcodes
1793 //===----------------------------------------------------------------------===//
1795 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1796 VINTRPCommon <outs, ins, "", pattern>,
1797 SIMCInstr<opName, SISubtarget.NONE> {
1799 let isCodeGenOnly = 1;
1802 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1804 VINTRPCommon <outs, ins, asm, []>,
1806 SIMCInstr<opName, SISubtarget.SI>;
1808 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1810 VINTRPCommon <outs, ins, asm, []>,
1812 SIMCInstr<opName, SISubtarget.VI>;
1814 multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
1815 list<dag> pattern = []> {
1816 def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
1818 def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>;
1820 def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
1823 //===----------------------------------------------------------------------===//
1824 // Vector I/O classes
1825 //===----------------------------------------------------------------------===//
1827 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1828 DS <outs, ins, "", pattern>,
1829 SIMCInstr <opName, SISubtarget.NONE> {
1831 let isCodeGenOnly = 1;
1834 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1835 DS <outs, ins, asm, []>,
1837 SIMCInstr <opName, SISubtarget.SI> {
1838 let isCodeGenOnly = 0;
1841 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1842 DS <outs, ins, asm, []>,
1844 SIMCInstr <opName, SISubtarget.VI>;
1846 class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1847 DS_Real_si <op,opName, outs, ins, asm> {
1849 // Single load interpret the 2 i8imm operands as a single i16 offset.
1851 let offset0 = offset{7-0};
1852 let offset1 = offset{15-8};
1853 let isCodeGenOnly = 0;
1856 class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1857 DS_Real_vi <op, opName, outs, ins, asm> {
1859 // Single load interpret the 2 i8imm operands as a single i16 offset.
1861 let offset0 = offset{7-0};
1862 let offset1 = offset{15-8};
1865 multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc,
1866 dag outs = (outs rc:$vdst),
1867 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds),
1868 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
1870 def "" : DS_Pseudo <opName, outs, ins, []>;
1872 let data0 = 0, data1 = 0 in {
1873 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1874 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1878 multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc,
1879 dag outs = (outs rc:$vdst),
1880 dag ins = (ins VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1882 string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> {
1884 def "" : DS_Pseudo <opName, outs, ins, []>;
1886 let data0 = 0, data1 = 0, AsmMatchConverter = "cvtDSOffset01" in {
1887 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1888 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1892 multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc,
1894 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds),
1895 string asm = opName#" $addr, $data0"#"$offset$gds"> {
1897 def "" : DS_Pseudo <opName, outs, ins, []>,
1898 AtomicNoRet<opName, 0>;
1900 let data1 = 0, vdst = 0 in {
1901 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1902 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1906 multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc,
1908 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1909 ds_offset0:$offset0, ds_offset1:$offset1, gds01:$gds),
1910 string asm = opName#" $addr, $data0, $data1"#"$offset0"#"$offset1"#"$gds"> {
1912 def "" : DS_Pseudo <opName, outs, ins, []>;
1914 let vdst = 0, AsmMatchConverter = "cvtDSOffset01" in {
1915 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1916 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1920 multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc,
1921 string noRetOp = "",
1922 dag outs = (outs rc:$vdst),
1923 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds),
1924 string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> {
1926 def "" : DS_Pseudo <opName, outs, ins, []>,
1927 AtomicNoRet<noRetOp, 1>;
1930 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1931 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1935 multiclass DS_1A2D_RET_m <bits<8> op, string opName, RegisterClass rc,
1936 string noRetOp = "", dag ins,
1937 dag outs = (outs rc:$vdst),
1938 string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"#"$gds"> {
1940 def "" : DS_Pseudo <opName, outs, ins, []>,
1941 AtomicNoRet<noRetOp, 1>;
1943 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1944 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1947 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1948 string noRetOp = "", RegisterClass src = rc> :
1949 DS_1A2D_RET_m <op, asm, rc, noRetOp,
1950 (ins VGPR_32:$addr, src:$data0, src:$data1,
1951 ds_offset:$offset, gds:$gds)
1954 multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc,
1955 string noRetOp = opName,
1957 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1958 ds_offset:$offset, gds:$gds),
1959 string asm = opName#" $addr, $data0, $data1"#"$offset"#"$gds"> {
1961 def "" : DS_Pseudo <opName, outs, ins, []>,
1962 AtomicNoRet<noRetOp, 0>;
1965 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1966 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1970 multiclass DS_0A_RET <bits<8> op, string opName,
1971 dag outs = (outs VGPR_32:$vdst),
1972 dag ins = (ins ds_offset:$offset, gds:$gds),
1973 string asm = opName#" $vdst"#"$offset"#"$gds"> {
1975 let mayLoad = 1, mayStore = 1 in {
1976 def "" : DS_Pseudo <opName, outs, ins, []>;
1978 let addr = 0, data0 = 0, data1 = 0 in {
1979 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1980 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1981 } // end addr = 0, data0 = 0, data1 = 0
1982 } // end mayLoad = 1, mayStore = 1
1985 multiclass DS_1A_RET_GDS <bits<8> op, string opName,
1986 dag outs = (outs VGPR_32:$vdst),
1987 dag ins = (ins VGPR_32:$addr, ds_offset_gds:$offset),
1988 string asm = opName#" $vdst, $addr"#"$offset gds"> {
1990 def "" : DS_Pseudo <opName, outs, ins, []>;
1992 let data0 = 0, data1 = 0, gds = 1 in {
1993 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1994 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1995 } // end data0 = 0, data1 = 0, gds = 1
1998 multiclass DS_1A_GDS <bits<8> op, string opName,
2000 dag ins = (ins VGPR_32:$addr),
2001 string asm = opName#" $addr gds"> {
2003 def "" : DS_Pseudo <opName, outs, ins, []>;
2005 let vdst = 0, data0 = 0, data1 = 0, offset0 = 0, offset1 = 0, gds = 1 in {
2006 def _si : DS_Real_si <op, opName, outs, ins, asm>;
2007 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
2008 } // end vdst = 0, data = 0, data1 = 0, gds = 1
2011 multiclass DS_1A <bits<8> op, string opName,
2013 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds),
2014 string asm = opName#" $addr"#"$offset"#"$gds"> {
2016 let mayLoad = 1, mayStore = 1 in {
2017 def "" : DS_Pseudo <opName, outs, ins, []>;
2019 let vdst = 0, data0 = 0, data1 = 0 in {
2020 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2021 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2022 } // let vdst = 0, data0 = 0, data1 = 0
2023 } // end mayLoad = 1, mayStore = 1
2026 //===----------------------------------------------------------------------===//
2028 //===----------------------------------------------------------------------===//
2030 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2031 MTBUF <outs, ins, "", pattern>,
2032 SIMCInstr<opName, SISubtarget.NONE> {
2034 let isCodeGenOnly = 1;
2037 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
2039 MTBUF <outs, ins, asm, []>,
2041 SIMCInstr<opName, SISubtarget.SI>;
2043 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
2044 MTBUF <outs, ins, asm, []>,
2046 SIMCInstr <opName, SISubtarget.VI>;
2048 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
2049 list<dag> pattern> {
2051 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
2053 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
2055 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
2059 let mayStore = 1, mayLoad = 0 in {
2061 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
2062 RegisterClass regClass> : MTBUF_m <
2064 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
2065 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
2066 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2067 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
2068 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2071 } // mayStore = 1, mayLoad = 0
2073 let mayLoad = 1, mayStore = 0 in {
2075 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
2076 RegisterClass regClass> : MTBUF_m <
2077 op, opName, (outs regClass:$dst),
2078 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
2079 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
2080 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2081 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
2082 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2085 } // mayLoad = 1, mayStore = 0
2087 //===----------------------------------------------------------------------===//
2089 //===----------------------------------------------------------------------===//
2091 class mubuf <bits<7> si, bits<7> vi = si> {
2092 field bits<7> SI = si;
2093 field bits<7> VI = vi;
2096 let isCodeGenOnly = 0 in {
2098 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
2099 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
2103 } // End let isCodeGenOnly = 0
2105 class MUBUF_vi <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
2106 MUBUF <outs, ins, asm, pattern>, MUBUFe_vi <op> {
2110 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
2111 bit IsAddr64 = is_addr64;
2112 string OpName = NAME # suffix;
2115 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2116 MUBUF <outs, ins, "", pattern>,
2117 SIMCInstr<opName, SISubtarget.NONE> {
2119 let isCodeGenOnly = 1;
2121 // dummy fields, so that we can use let statements around multiclasses
2131 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
2133 MUBUF <outs, ins, asm, []>,
2135 SIMCInstr<opName, SISubtarget.SI> {
2139 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
2141 MUBUF <outs, ins, asm, []>,
2143 SIMCInstr<opName, SISubtarget.VI> {
2147 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
2148 list<dag> pattern> {
2150 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2151 MUBUFAddr64Table <0>;
2153 let addr64 = 0, isCodeGenOnly = 0 in {
2154 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2157 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2160 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
2161 dag ins, string asm, list<dag> pattern> {
2163 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2164 MUBUFAddr64Table <1>;
2166 let addr64 = 1, isCodeGenOnly = 0 in {
2167 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2170 // There is no VI version. If the pseudo is selected, it should be lowered
2171 // for VI appropriately.
2174 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
2175 string asm, list<dag> pattern, bit is_return> {
2177 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2178 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
2179 AtomicNoRet<NAME#"_OFFSET", is_return>;
2181 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
2183 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2186 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2190 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
2191 string asm, list<dag> pattern, bit is_return> {
2193 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2194 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
2195 AtomicNoRet<NAME#"_ADDR64", is_return>;
2197 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
2198 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2201 // There is no VI version. If the pseudo is selected, it should be lowered
2202 // for VI appropriately.
2205 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
2206 ValueType vt, SDPatternOperator atomic> {
2208 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
2210 // No return variants
2213 defm _ADDR64 : MUBUFAtomicAddr64_m <
2214 op, name#"_addr64", (outs),
2215 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
2216 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2217 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
2220 defm _OFFSET : MUBUFAtomicOffset_m <
2221 op, name#"_offset", (outs),
2222 (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset,
2224 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
2228 // Variant that return values
2229 let glc = 1, Constraints = "$vdata = $vdata_in",
2230 DisableEncoding = "$vdata_in" in {
2232 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
2233 op, name#"_rtn_addr64", (outs rc:$vdata),
2234 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
2235 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2236 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
2238 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
2239 i16:$offset, i1:$slc), vt:$vdata_in))], 1
2242 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
2243 op, name#"_rtn_offset", (outs rc:$vdata),
2244 (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset,
2245 mbuf_offset:$offset, slc:$slc),
2246 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
2248 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
2249 i1:$slc), vt:$vdata_in))], 1
2254 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
2257 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
2258 ValueType load_vt = i32,
2259 SDPatternOperator ld = null_frag> {
2261 let mayLoad = 1, mayStore = 0 in {
2262 let offen = 0, idxen = 0, vaddr = 0 in {
2263 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
2264 (ins SReg_128:$srsrc, SCSrc_32:$soffset,
2265 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2266 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2267 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
2268 i32:$soffset, i16:$offset,
2269 i1:$glc, i1:$slc, i1:$tfe)))]>;
2272 let offen = 1, idxen = 0 in {
2273 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
2274 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2275 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
2277 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2280 let offen = 0, idxen = 1 in {
2281 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
2282 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2283 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2284 slc:$slc, tfe:$tfe),
2285 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2288 let offen = 1, idxen = 1 in {
2289 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
2290 (ins VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2291 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2292 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2295 let offen = 0, idxen = 0 in {
2296 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
2297 (ins VReg_64:$vaddr, SReg_128:$srsrc,
2298 SCSrc_32:$soffset, mbuf_offset:$offset,
2299 glc:$glc, slc:$slc, tfe:$tfe),
2300 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#
2301 "$glc"#"$slc"#"$tfe",
2302 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
2303 i64:$vaddr, i32:$soffset,
2304 i16:$offset, i1:$glc, i1:$slc,
2310 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
2311 ValueType store_vt = i32, SDPatternOperator st = null_frag> {
2312 let mayLoad = 0, mayStore = 1 in {
2313 defm : MUBUF_m <op, name, (outs),
2314 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2315 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
2317 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
2318 "$glc"#"$slc"#"$tfe", []>;
2320 let offen = 0, idxen = 0, vaddr = 0 in {
2321 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
2322 (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset,
2323 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2324 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2325 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
2326 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
2327 } // offen = 0, idxen = 0, vaddr = 0
2329 let offen = 1, idxen = 0 in {
2330 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
2331 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2332 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2333 slc:$slc, tfe:$tfe),
2334 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
2335 "$glc"#"$slc"#"$tfe", []>;
2336 } // end offen = 1, idxen = 0
2338 let offen = 0, idxen = 1 in {
2339 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs),
2340 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2341 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2342 slc:$slc, tfe:$tfe),
2343 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2346 let offen = 1, idxen = 1 in {
2347 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs),
2348 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2349 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2350 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2353 let offen = 0, idxen = 0 in {
2354 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
2355 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc,
2357 mbuf_offset:$offset, glc:$glc, slc:$slc,
2359 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#
2360 "$offset"#"$glc"#"$slc"#"$tfe",
2361 [(st store_vt:$vdata,
2362 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
2363 i32:$soffset, i16:$offset,
2364 i1:$glc, i1:$slc, i1:$tfe))]>;
2366 } // End mayLoad = 0, mayStore = 1
2369 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
2370 FLAT <op, (outs regClass:$vdst),
2371 (ins VReg_64:$addr, glc_flat:$glc, slc_flat:$slc, tfe_flat:$tfe),
2372 asm#" $vdst, $addr"#"$glc"#"$slc"#"$tfe", []> {
2377 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
2378 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr,
2379 glc_flat:$glc, slc_flat:$slc, tfe_flat:$tfe),
2380 name#" $data, $addr"#"$glc"#"$slc"#"$tfe",
2390 multiclass FLAT_ATOMIC <bits<7> op, string name, RegisterClass vdst_rc,
2391 RegisterClass data_rc = vdst_rc> {
2393 let mayLoad = 1, mayStore = 1 in {
2394 def "" : FLAT <op, (outs),
2395 (ins VReg_64:$addr, data_rc:$data, slc_flat_atomic:$slc,
2396 tfe_flat_atomic:$tfe),
2397 name#" $addr, $data"#"$slc"#"$tfe", []>,
2398 AtomicNoRet <NAME, 0> {
2403 def _RTN : FLAT <op, (outs vdst_rc:$vdst),
2404 (ins VReg_64:$addr, data_rc:$data, slc_flat_atomic:$slc,
2405 tfe_flat_atomic:$tfe),
2406 name#" $vdst, $addr, $data glc"#"$slc"#"$tfe", []>,
2407 AtomicNoRet <NAME, 1> {
2413 class MIMG_Mask <string op, int channels> {
2415 int Channels = channels;
2418 class MIMG_NoSampler_Helper <bits<7> op, string asm,
2419 RegisterClass dst_rc,
2420 RegisterClass src_rc> : MIMG <
2422 (outs dst_rc:$vdata),
2423 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2424 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2426 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2427 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
2432 let hasPostISelHook = 1;
2435 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
2436 RegisterClass dst_rc,
2438 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
2439 MIMG_Mask<asm#"_V1", channels>;
2440 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
2441 MIMG_Mask<asm#"_V2", channels>;
2442 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
2443 MIMG_Mask<asm#"_V4", channels>;
2446 multiclass MIMG_NoSampler <bits<7> op, string asm> {
2447 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
2448 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
2449 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
2450 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
2453 class MIMG_Sampler_Helper <bits<7> op, string asm,
2454 RegisterClass dst_rc,
2455 RegisterClass src_rc, int wqm> : MIMG <
2457 (outs dst_rc:$vdata),
2458 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2459 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2460 SReg_256:$srsrc, SReg_128:$ssamp),
2461 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2462 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2466 let hasPostISelHook = 1;
2470 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2471 RegisterClass dst_rc,
2472 int channels, int wqm> {
2473 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2474 MIMG_Mask<asm#"_V1", channels>;
2475 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2476 MIMG_Mask<asm#"_V2", channels>;
2477 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2478 MIMG_Mask<asm#"_V4", channels>;
2479 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2480 MIMG_Mask<asm#"_V8", channels>;
2481 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2482 MIMG_Mask<asm#"_V16", channels>;
2485 multiclass MIMG_Sampler <bits<7> op, string asm> {
2486 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2487 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2488 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2489 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2492 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2493 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2494 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2495 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2496 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2499 class MIMG_Gather_Helper <bits<7> op, string asm,
2500 RegisterClass dst_rc,
2501 RegisterClass src_rc, int wqm> : MIMG <
2503 (outs dst_rc:$vdata),
2504 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2505 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2506 SReg_256:$srsrc, SReg_128:$ssamp),
2507 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2508 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2513 // DMASK was repurposed for GATHER4. 4 components are always
2514 // returned and DMASK works like a swizzle - it selects
2515 // the component to fetch. The only useful DMASK values are
2516 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2517 // (red,red,red,red) etc.) The ISA document doesn't mention
2519 // Therefore, disable all code which updates DMASK by setting these two:
2521 let hasPostISelHook = 0;
2525 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2526 RegisterClass dst_rc,
2527 int channels, int wqm> {
2528 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2529 MIMG_Mask<asm#"_V1", channels>;
2530 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2531 MIMG_Mask<asm#"_V2", channels>;
2532 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2533 MIMG_Mask<asm#"_V4", channels>;
2534 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2535 MIMG_Mask<asm#"_V8", channels>;
2536 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2537 MIMG_Mask<asm#"_V16", channels>;
2540 multiclass MIMG_Gather <bits<7> op, string asm> {
2541 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2542 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2543 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2544 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2547 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2548 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2549 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2550 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2551 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2554 //===----------------------------------------------------------------------===//
2555 // Vector instruction mappings
2556 //===----------------------------------------------------------------------===//
2558 // Maps an opcode in e32 form to its e64 equivalent
2559 def getVOPe64 : InstrMapping {
2560 let FilterClass = "VOP";
2561 let RowFields = ["OpName"];
2562 let ColFields = ["Size"];
2564 let ValueCols = [["8"]];
2567 // Maps an opcode in e64 form to its e32 equivalent
2568 def getVOPe32 : InstrMapping {
2569 let FilterClass = "VOP";
2570 let RowFields = ["OpName"];
2571 let ColFields = ["Size"];
2573 let ValueCols = [["4"]];
2576 def getMaskedMIMGOp : InstrMapping {
2577 let FilterClass = "MIMG_Mask";
2578 let RowFields = ["Op"];
2579 let ColFields = ["Channels"];
2581 let ValueCols = [["1"], ["2"], ["3"] ];
2584 // Maps an commuted opcode to its original version
2585 def getCommuteOrig : InstrMapping {
2586 let FilterClass = "VOP2_REV";
2587 let RowFields = ["RevOp"];
2588 let ColFields = ["IsOrig"];
2590 let ValueCols = [["1"]];
2593 // Maps an original opcode to its commuted version
2594 def getCommuteRev : InstrMapping {
2595 let FilterClass = "VOP2_REV";
2596 let RowFields = ["RevOp"];
2597 let ColFields = ["IsOrig"];
2599 let ValueCols = [["0"]];
2602 def getCommuteCmpOrig : InstrMapping {
2603 let FilterClass = "VOP2_REV";
2604 let RowFields = ["RevOp"];
2605 let ColFields = ["IsOrig"];
2607 let ValueCols = [["1"]];
2610 // Maps an original opcode to its commuted version
2611 def getCommuteCmpRev : InstrMapping {
2612 let FilterClass = "VOP2_REV";
2613 let RowFields = ["RevOp"];
2614 let ColFields = ["IsOrig"];
2616 let ValueCols = [["0"]];
2620 def getMCOpcodeGen : InstrMapping {
2621 let FilterClass = "SIMCInstr";
2622 let RowFields = ["PseudoInstr"];
2623 let ColFields = ["Subtarget"];
2624 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2625 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2628 def getAddr64Inst : InstrMapping {
2629 let FilterClass = "MUBUFAddr64Table";
2630 let RowFields = ["OpName"];
2631 let ColFields = ["IsAddr64"];
2633 let ValueCols = [["1"]];
2636 // Maps an atomic opcode to its version with a return value.
2637 def getAtomicRetOp : InstrMapping {
2638 let FilterClass = "AtomicNoRet";
2639 let RowFields = ["NoRetOp"];
2640 let ColFields = ["IsRet"];
2642 let ValueCols = [["1"]];
2645 // Maps an atomic opcode to its returnless version.
2646 def getAtomicNoRetOp : InstrMapping {
2647 let FilterClass = "AtomicNoRet";
2648 let RowFields = ["NoRetOp"];
2649 let ColFields = ["IsRet"];
2651 let ValueCols = [["0"]];
2654 include "SIInstructions.td"
2655 include "CIInstructions.td"
2656 include "VIInstructions.td"