1 //===-- SIInstrInfo.td - SI Instruction Encodings ---------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
13 AMDGPUInst<outs, ins, asm, pattern> {
15 field bits<4> EncodingType = 0;
16 field bits<1> NeedWait = 0;
18 let TSFlags{3-0} = EncodingType;
19 let TSFlags{4} = NeedWait;
23 class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
24 InstSI <outs, ins, asm, pattern> {
29 class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
30 InstSI <outs, ins, asm, pattern> {
35 class SIOperand <ValueType vt, dag opInfo>: Operand <vt> {
36 let EncoderMethod = "encodeOperand";
37 let MIOperandInfo = opInfo;
40 def IMM8bit : ImmLeaf <
42 [{return (int32_t)Imm >= 0 && (int32_t)Imm <= 0xff;}]
45 def IMM12bit : ImmLeaf <
47 [{return (int16_t)Imm >= 0 && (int16_t)Imm <= 0xfff;}]
50 class GPR4Align <RegisterClass rc> : Operand <vAny> {
51 let EncoderMethod = "GPR4AlignEncode";
52 let MIOperandInfo = (ops rc:$reg);
55 class GPR2Align <RegisterClass rc, ValueType vt> : Operand <vt> {
56 let EncoderMethod = "GPR2AlignEncode";
57 let MIOperandInfo = (ops rc:$reg);
60 def i32Literal : Operand <i32> {
61 let EncoderMethod = "i32LiteralEncode";
64 def SMRDmemrr : Operand<iPTR> {
65 let MIOperandInfo = (ops SReg_64, SReg_32);
66 let EncoderMethod = "GPR2AlignEncode";
69 def SMRDmemri : Operand<iPTR> {
70 let MIOperandInfo = (ops SReg_64, i32imm);
71 let EncoderMethod = "SMRDmemriEncode";
74 def ADDR_Reg : ComplexPattern<i64, 2, "SelectADDRReg", [], []>;
75 def ADDR_Offset8 : ComplexPattern<i64, 2, "SelectADDR8BitOffset", [], []>;
79 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
80 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
81 "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
99 let Inst{31-26} = 0x3e;
100 let Inst{39-32} = VSRC0;
101 let Inst{47-40} = VSRC1;
102 let Inst{55-48} = VSRC2;
103 let Inst{63-56} = VSRC3;
104 let EncodingType = 0; //SIInstrEncodingType::EXP
107 let usesCustomInserter = 1;
110 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
111 Enc64 <outs, ins, asm, pattern> {
126 let Inst{11-8} = DMASK;
127 let Inst{12} = UNORM;
133 let Inst{24-18} = op;
135 let Inst{31-26} = 0x3c;
136 let Inst{39-32} = VADDR;
137 let Inst{47-40} = VDATA;
138 let Inst{52-48} = SRSRC;
139 let Inst{57-53} = SSAMP;
141 let EncodingType = 2; //SIInstrEncodingType::MIMG
144 let usesCustomInserter = 1;
147 class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
148 Enc64<outs, ins, asm, pattern> {
164 let Inst{11-0} = OFFSET;
165 let Inst{12} = OFFEN;
166 let Inst{13} = IDXEN;
168 let Inst{15} = ADDR64;
169 let Inst{18-16} = op;
170 let Inst{22-19} = DFMT;
171 let Inst{25-23} = NFMT;
172 let Inst{31-26} = 0x3a; //encoding
173 let Inst{39-32} = VADDR;
174 let Inst{47-40} = VDATA;
175 let Inst{52-48} = SRSRC;
178 let Inst{63-56} = SOFFSET;
179 let EncodingType = 3; //SIInstrEncodingType::MTBUF
182 let usesCustomInserter = 1;
183 let neverHasSideEffects = 1;
186 class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
187 Enc64<outs, ins, asm, pattern> {
202 let Inst{11-0} = OFFSET;
203 let Inst{12} = OFFEN;
204 let Inst{13} = IDXEN;
206 let Inst{15} = ADDR64;
208 let Inst{24-18} = op;
209 let Inst{31-26} = 0x38; //encoding
210 let Inst{39-32} = VADDR;
211 let Inst{47-40} = VDATA;
212 let Inst{52-48} = SRSRC;
215 let Inst{63-56} = SOFFSET;
216 let EncodingType = 4; //SIInstrEncodingType::MUBUF
219 let usesCustomInserter = 1;
220 let neverHasSideEffects = 1;
223 class SMRD <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
224 Enc32<outs, ins, asm, pattern> {
228 bits<8> OFFSET = PTR{7-0};
229 bits<1> IMM = PTR{8};
230 bits<6> SBASE = PTR{14-9};
232 let Inst{7-0} = OFFSET;
234 let Inst{14-9} = SBASE;
235 let Inst{21-15} = SDST;
236 let Inst{26-22} = op;
237 let Inst{31-27} = 0x18; //encoding
238 let EncodingType = 5; //SIInstrEncodingType::SMRD
241 let usesCustomInserter = 1;
244 class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
245 Enc32<outs, ins, asm, pattern> {
250 let Inst{7-0} = SSRC0;
252 let Inst{22-16} = SDST;
253 let Inst{31-23} = 0x17d; //encoding;
254 let EncodingType = 6; //SIInstrEncodingType::SOP1
257 class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
258 Enc32 <outs, ins, asm, pattern> {
264 let Inst{7-0} = SSRC0;
265 let Inst{15-8} = SSRC1;
266 let Inst{22-16} = SDST;
267 let Inst{29-23} = op;
268 let Inst{31-30} = 0x2; // encoding
269 let EncodingType = 7; // SIInstrEncodingType::SOP2
272 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
273 Enc32<outs, ins, asm, pattern> {
278 let Inst{7-0} = SSRC0;
279 let Inst{15-8} = SSRC1;
280 let Inst{22-16} = op;
281 let Inst{31-23} = 0x17e;
282 let EncodingType = 8; // SIInstrEncodingType::SOPC
285 class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
286 Enc32 <outs, ins , asm, pattern> {
291 let Inst{15-0} = SIMM16;
292 let Inst{22-16} = SDST;
293 let Inst{27-23} = op;
294 let Inst{31-28} = 0xb; //encoding
295 let EncodingType = 9; // SIInstrEncodingType::SOPK
298 class SOPP <bits<7> op, dag ins, string asm> : Enc32 <
306 let Inst{15-0} = SIMM16;
307 let Inst{22-16} = op;
308 let Inst{31-23} = 0x17f; // encoding
309 let EncodingType = 10; // SIInstrEncodingType::SOPP
313 class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
314 Enc32 <outs, ins, asm, pattern> {
321 let Inst{7-0} = VSRC;
322 let Inst{9-8} = ATTRCHAN;
323 let Inst{15-10} = ATTR;
324 let Inst{17-16} = op;
325 let Inst{25-18} = VDST;
326 let Inst{31-26} = 0x32; // encoding
327 let EncodingType = 11; // SIInstrEncodingType::VINTRP
332 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
333 Enc32 <outs, ins, asm, pattern> {
338 let Inst{8-0} = SRC0;
340 let Inst{24-17} = VDST;
341 let Inst{31-25} = 0x3f; //encoding
343 let EncodingType = 12; // SIInstrEncodingType::VOP1
344 let PostEncoderMethod = "VOPPostEncode";
347 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
348 Enc32 <outs, ins, asm, pattern> {
354 let Inst{8-0} = SRC0;
355 let Inst{16-9} = VSRC1;
356 let Inst{24-17} = VDST;
357 let Inst{30-25} = op;
358 let Inst{31} = 0x0; //encoding
360 let EncodingType = 13; // SIInstrEncodingType::VOP2
361 let PostEncoderMethod = "VOPPostEncode";
364 class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
365 Enc64 <outs, ins, asm, pattern> {
376 let Inst{7-0} = VDST;
377 let Inst{10-8} = ABS;
378 let Inst{11} = CLAMP;
379 let Inst{25-17} = op;
380 let Inst{31-26} = 0x34; //encoding
381 let Inst{40-32} = SRC0;
382 let Inst{49-41} = SRC1;
383 let Inst{58-50} = SRC2;
384 let Inst{60-59} = OMOD;
385 let Inst{63-61} = NEG;
387 let EncodingType = 14; // SIInstrEncodingType::VOP3
388 let PostEncoderMethod = "VOPPostEncode";
391 class VOPC <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
392 Enc32 <outs, ins, asm, pattern> {
397 let Inst{8-0} = SRC0;
398 let Inst{16-9} = VSRC1;
399 let Inst{24-17} = op;
400 let Inst{31-25} = 0x3e;
402 let EncodingType = 15; //SIInstrEncodingType::VOPC
403 let PostEncoderMethod = "VOPPostEncode";
408 class MIMG_Load_Helper <bits<7> op, string asm> : MIMG <
410 (outs VReg_128:$vdata),
411 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
412 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_128:$vaddr,
413 GPR4Align<SReg_256>:$srsrc, GPR4Align<SReg_128>:$ssamp),
418 class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF <
420 (outs regClass:$dst),
421 (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
422 i1imm:$lds, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc, i1imm:$slc,
423 i1imm:$tfe, SReg_32:$soffset),
429 class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
431 (outs regClass:$dst),
432 (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
433 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc,
434 i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
440 class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
443 (ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
444 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
445 GPR4Align<SReg_128>:$srsrc, i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
451 multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass,
456 (outs dstClass:$dst),
457 (ins SMRDmemrr:$src0),
459 [(set (vt dstClass:$dst), (constant_load ADDR_Reg:$src0))]
464 (outs dstClass:$dst),
465 (ins SMRDmemri:$src0),
467 [(set (vt dstClass:$dst), (constant_load ADDR_Offset8:$src0))]
471 multiclass SMRD_32 <bits<5> op, string asm, RegisterClass dstClass> {
472 defm _F32 : SMRD_Helper <op, asm, dstClass, f32>;
473 defm _I32 : SMRD_Helper <op, asm, dstClass, i32>;
476 include "SIInstrFormats.td"
477 include "SIInstructions.td"