1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 def isCI : Predicate<"Subtarget->getGeneration() "
10 ">= AMDGPUSubtarget::SEA_ISLANDS">;
11 def isCIOnly : Predicate<"Subtarget->getGeneration() =="
12 "AMDGPUSubtarget::SEA_ISLANDS">,
13 AssemblerPredicate <"FeatureSeaIslands">;
14 def isVI : Predicate <
15 "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
16 AssemblerPredicate<"FeatureGCN3Encoding">;
18 def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">;
25 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
26 field bits<8> SI = si;
27 field bits<8> VI = vi;
29 field bits<9> SI3 = {0, si{7-0}};
30 field bits<10> VI3 = {0, 0, vi{7-0}};
33 class vop1 <bits<8> si, bits<8> vi = si> : vop {
34 field bits<8> SI = si;
35 field bits<8> VI = vi;
37 field bits<9> SI3 = {1, 1, si{6-0}};
38 field bits<10> VI3 = !add(0x140, vi);
41 class vop2 <bits<6> si, bits<6> vi = si> : vop {
42 field bits<6> SI = si;
43 field bits<6> VI = vi;
45 field bits<9> SI3 = {1, 0, 0, si{5-0}};
46 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
49 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
50 // that doesn't have VOP2 encoding on VI
51 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
55 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
60 class sop1 <bits<8> si, bits<8> vi = si> {
61 field bits<8> SI = si;
62 field bits<8> VI = vi;
65 class sop2 <bits<7> si, bits<7> vi = si> {
66 field bits<7> SI = si;
67 field bits<7> VI = vi;
70 class sopk <bits<5> si, bits<5> vi = si> {
71 field bits<5> SI = si;
72 field bits<5> VI = vi;
75 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
76 // in AMDGPUInstrInfo.cpp
83 //===----------------------------------------------------------------------===//
85 //===----------------------------------------------------------------------===//
87 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
88 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
89 [SDNPMayLoad, SDNPMemOperand]
92 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
94 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
95 SDTCisVT<1, iAny>, // vdata(VGPR)
96 SDTCisVT<2, i32>, // num_channels(imm)
97 SDTCisVT<3, i32>, // vaddr(VGPR)
98 SDTCisVT<4, i32>, // soffset(SGPR)
99 SDTCisVT<5, i32>, // inst_offset(imm)
100 SDTCisVT<6, i32>, // dfmt(imm)
101 SDTCisVT<7, i32>, // nfmt(imm)
102 SDTCisVT<8, i32>, // offen(imm)
103 SDTCisVT<9, i32>, // idxen(imm)
104 SDTCisVT<10, i32>, // glc(imm)
105 SDTCisVT<11, i32>, // slc(imm)
106 SDTCisVT<12, i32> // tfe(imm)
108 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
111 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
112 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
116 class SDSample<string opcode> : SDNode <opcode,
117 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
118 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
121 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
122 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
123 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
124 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
126 def SIconstdata_ptr : SDNode<
127 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
130 //===----------------------------------------------------------------------===//
131 // SDNodes and PatFrag for local loads and stores to enable s_mov_b32 m0, -1
132 // to be glued to the memory instructions.
133 //===----------------------------------------------------------------------===//
135 def SIld_local : SDNode <"ISD::LOAD", SDTLoad,
136 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
139 def si_ld_local : PatFrag <(ops node:$ptr), (SIld_local node:$ptr), [{
140 return isLocalLoad(cast<LoadSDNode>(N));
143 def si_load_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{
144 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
145 cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
148 def si_load_local_align8 : Aligned8Bytes <
149 (ops node:$ptr), (si_load_local node:$ptr)
152 def si_sextload_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{
153 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
155 def si_az_extload_local : AZExtLoadBase <si_ld_local>;
157 multiclass SIExtLoadLocal <PatFrag ld_node> {
159 def _i8 : PatFrag <(ops node:$ptr), (ld_node node:$ptr),
160 [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;}]
163 def _i16 : PatFrag <(ops node:$ptr), (ld_node node:$ptr),
164 [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;}]
168 defm si_sextload_local : SIExtLoadLocal <si_sextload_local>;
169 defm si_az_extload_local : SIExtLoadLocal <si_az_extload_local>;
171 def SIst_local : SDNode <"ISD::STORE", SDTStore,
172 [SDNPHasChain, SDNPMayStore, SDNPMemOperand, SDNPInGlue]
175 def si_st_local : PatFrag <
176 (ops node:$val, node:$ptr), (SIst_local node:$val, node:$ptr), [{
177 return isLocalStore(cast<StoreSDNode>(N));
180 def si_store_local : PatFrag <
181 (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{
182 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
183 !cast<StoreSDNode>(N)->isTruncatingStore();
186 def si_store_local_align8 : Aligned8Bytes <
187 (ops node:$val, node:$ptr), (si_store_local node:$val, node:$ptr)
190 def si_truncstore_local : PatFrag <
191 (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{
192 return cast<StoreSDNode>(N)->isTruncatingStore();
195 def si_truncstore_local_i8 : PatFrag <
196 (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{
197 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
200 def si_truncstore_local_i16 : PatFrag <
201 (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{
202 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
205 multiclass SIAtomicM0Glue2 <string op_name> {
207 def _glue : SDNode <"ISD::ATOMIC_"#op_name, SDTAtomic2,
208 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
211 def _local : local_binary_atomic_op <!cast<SDNode>(NAME#"_glue")>;
214 defm si_atomic_load_add : SIAtomicM0Glue2 <"LOAD_ADD">;
215 defm si_atomic_load_and : SIAtomicM0Glue2 <"LOAD_AND">;
216 defm si_atomic_load_min : SIAtomicM0Glue2 <"LOAD_MIN">;
217 defm si_atomic_load_max : SIAtomicM0Glue2 <"LOAD_MAX">;
218 defm si_atomic_load_or : SIAtomicM0Glue2 <"LOAD_OR">;
219 defm si_atomic_load_sub : SIAtomicM0Glue2 <"LOAD_SUB">;
220 defm si_atomic_load_xor : SIAtomicM0Glue2 <"LOAD_XOR">;
221 defm si_atomic_load_umin : SIAtomicM0Glue2 <"LOAD_UMIN">;
222 defm si_atomic_load_umax : SIAtomicM0Glue2 <"LOAD_UMAX">;
223 defm si_atomic_swap : SIAtomicM0Glue2 <"SWAP">;
225 def si_atomic_cmp_swap_glue : SDNode <"ISD::ATOMIC_CMP_SWAP", SDTAtomic3,
226 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
229 defm si_atomic_cmp_swap : AtomicCmpSwapLocal <si_atomic_cmp_swap_glue>;
231 // Transformation function, extract the lower 32bit of a 64bit immediate
232 def LO32 : SDNodeXForm<imm, [{
233 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, SDLoc(N),
237 def LO32f : SDNodeXForm<fpimm, [{
238 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
239 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
242 // Transformation function, extract the upper 32bit of a 64bit immediate
243 def HI32 : SDNodeXForm<imm, [{
244 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, SDLoc(N), MVT::i32);
247 def HI32f : SDNodeXForm<fpimm, [{
248 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
249 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), SDLoc(N),
253 def IMM8bitDWORD : PatLeaf <(imm),
254 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
257 def as_dword_i32imm : SDNodeXForm<imm, [{
258 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, SDLoc(N), MVT::i32);
261 def as_i1imm : SDNodeXForm<imm, [{
262 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i1);
265 def as_i8imm : SDNodeXForm<imm, [{
266 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i8);
269 def as_i16imm : SDNodeXForm<imm, [{
270 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
273 def as_i32imm: SDNodeXForm<imm, [{
274 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
277 def as_i64imm: SDNodeXForm<imm, [{
278 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
281 // Copied from the AArch64 backend:
282 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
283 return CurDAG->getTargetConstant(
284 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
287 // Copied from the AArch64 backend:
288 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
289 return CurDAG->getTargetConstant(
290 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
293 def IMM8bit : PatLeaf <(imm),
294 [{return isUInt<8>(N->getZExtValue());}]
297 def IMM12bit : PatLeaf <(imm),
298 [{return isUInt<12>(N->getZExtValue());}]
301 def IMM16bit : PatLeaf <(imm),
302 [{return isUInt<16>(N->getZExtValue());}]
305 def IMM20bit : PatLeaf <(imm),
306 [{return isUInt<20>(N->getZExtValue());}]
309 def IMM32bit : PatLeaf <(imm),
310 [{return isUInt<32>(N->getZExtValue());}]
313 def mubuf_vaddr_offset : PatFrag<
314 (ops node:$ptr, node:$offset, node:$imm_offset),
315 (add (add node:$ptr, node:$offset), node:$imm_offset)
318 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
319 return isInlineImmediate(N);
322 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
323 return isInlineImmediate(N);
326 class SGPRImm <dag frag> : PatLeaf<frag, [{
327 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
330 const SIRegisterInfo *SIRI =
331 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
332 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
334 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
341 //===----------------------------------------------------------------------===//
343 //===----------------------------------------------------------------------===//
345 def FRAMEri32 : Operand<iPTR> {
346 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
349 def SoppBrTarget : AsmOperandClass {
350 let Name = "SoppBrTarget";
351 let ParserMethod = "parseSOppBrTarget";
354 def sopp_brtarget : Operand<OtherVT> {
355 let EncoderMethod = "getSOPPBrEncoding";
356 let OperandType = "OPERAND_PCREL";
357 let ParserMatchClass = SoppBrTarget;
360 include "SIInstrFormats.td"
361 include "VIInstrFormats.td"
363 def MubufOffsetMatchClass : AsmOperandClass {
364 let Name = "MubufOffset";
365 let ParserMethod = "parseMubufOptionalOps";
366 let RenderMethod = "addImmOperands";
369 class DSOffsetBaseMatchClass <string parser> : AsmOperandClass {
370 let Name = "DSOffset"#parser;
371 let ParserMethod = parser;
372 let RenderMethod = "addImmOperands";
373 let PredicateMethod = "isDSOffset";
376 def DSOffsetMatchClass : DSOffsetBaseMatchClass <"parseDSOptionalOps">;
377 def DSOffsetGDSMatchClass : DSOffsetBaseMatchClass <"parseDSOffsetOptional">;
379 def DSOffset01MatchClass : AsmOperandClass {
380 let Name = "DSOffset1";
381 let ParserMethod = "parseDSOff01OptionalOps";
382 let RenderMethod = "addImmOperands";
383 let PredicateMethod = "isDSOffset01";
386 class GDSBaseMatchClass <string parser> : AsmOperandClass {
387 let Name = "GDS"#parser;
388 let PredicateMethod = "isImm";
389 let ParserMethod = parser;
390 let RenderMethod = "addImmOperands";
393 def GDSMatchClass : GDSBaseMatchClass <"parseDSOptionalOps">;
394 def GDS01MatchClass : GDSBaseMatchClass <"parseDSOff01OptionalOps">;
396 class GLCBaseMatchClass <string parser> : AsmOperandClass {
397 let Name = "GLC"#parser;
398 let PredicateMethod = "isImm";
399 let ParserMethod = parser;
400 let RenderMethod = "addImmOperands";
403 def GLCMubufMatchClass : GLCBaseMatchClass <"parseMubufOptionalOps">;
404 def GLCFlatMatchClass : GLCBaseMatchClass <"parseFlatOptionalOps">;
406 class SLCBaseMatchClass <string parser> : AsmOperandClass {
407 let Name = "SLC"#parser;
408 let PredicateMethod = "isImm";
409 let ParserMethod = parser;
410 let RenderMethod = "addImmOperands";
413 def SLCMubufMatchClass : SLCBaseMatchClass <"parseMubufOptionalOps">;
414 def SLCFlatMatchClass : SLCBaseMatchClass <"parseFlatOptionalOps">;
415 def SLCFlatAtomicMatchClass : SLCBaseMatchClass <"parseFlatAtomicOptionalOps">;
417 class TFEBaseMatchClass <string parser> : AsmOperandClass {
418 let Name = "TFE"#parser;
419 let PredicateMethod = "isImm";
420 let ParserMethod = parser;
421 let RenderMethod = "addImmOperands";
424 def TFEMubufMatchClass : TFEBaseMatchClass <"parseMubufOptionalOps">;
425 def TFEFlatMatchClass : TFEBaseMatchClass <"parseFlatOptionalOps">;
426 def TFEFlatAtomicMatchClass : TFEBaseMatchClass <"parseFlatAtomicOptionalOps">;
428 def OModMatchClass : AsmOperandClass {
430 let PredicateMethod = "isImm";
431 let ParserMethod = "parseVOP3OptionalOps";
432 let RenderMethod = "addImmOperands";
435 def ClampMatchClass : AsmOperandClass {
437 let PredicateMethod = "isImm";
438 let ParserMethod = "parseVOP3OptionalOps";
439 let RenderMethod = "addImmOperands";
442 class SMRDOffsetBaseMatchClass <string predicate> : AsmOperandClass {
443 let Name = "SMRDOffset"#predicate;
444 let PredicateMethod = predicate;
445 let RenderMethod = "addImmOperands";
448 def SMRDOffsetMatchClass : SMRDOffsetBaseMatchClass <"isSMRDOffset">;
449 def SMRDLiteralOffsetMatchClass : SMRDOffsetBaseMatchClass <
450 "isSMRDLiteralOffset"
453 let OperandType = "OPERAND_IMMEDIATE" in {
455 def offen : Operand<i1> {
456 let PrintMethod = "printOffen";
458 def idxen : Operand<i1> {
459 let PrintMethod = "printIdxen";
461 def addr64 : Operand<i1> {
462 let PrintMethod = "printAddr64";
464 def mbuf_offset : Operand<i16> {
465 let PrintMethod = "printMBUFOffset";
466 let ParserMatchClass = MubufOffsetMatchClass;
468 class ds_offset_base <AsmOperandClass mc> : Operand<i16> {
469 let PrintMethod = "printDSOffset";
470 let ParserMatchClass = mc;
472 def ds_offset : ds_offset_base <DSOffsetMatchClass>;
473 def ds_offset_gds : ds_offset_base <DSOffsetGDSMatchClass>;
475 def ds_offset0 : Operand<i8> {
476 let PrintMethod = "printDSOffset0";
477 let ParserMatchClass = DSOffset01MatchClass;
479 def ds_offset1 : Operand<i8> {
480 let PrintMethod = "printDSOffset1";
481 let ParserMatchClass = DSOffset01MatchClass;
483 class gds_base <AsmOperandClass mc> : Operand <i1> {
484 let PrintMethod = "printGDS";
485 let ParserMatchClass = mc;
487 def gds : gds_base <GDSMatchClass>;
489 def gds01 : gds_base <GDS01MatchClass>;
491 class glc_base <AsmOperandClass mc> : Operand <i1> {
492 let PrintMethod = "printGLC";
493 let ParserMatchClass = mc;
496 def glc : glc_base <GLCMubufMatchClass>;
497 def glc_flat : glc_base <GLCFlatMatchClass>;
499 class slc_base <AsmOperandClass mc> : Operand <i1> {
500 let PrintMethod = "printSLC";
501 let ParserMatchClass = mc;
504 def slc : slc_base <SLCMubufMatchClass>;
505 def slc_flat : slc_base <SLCFlatMatchClass>;
506 def slc_flat_atomic : slc_base <SLCFlatAtomicMatchClass>;
508 class tfe_base <AsmOperandClass mc> : Operand <i1> {
509 let PrintMethod = "printTFE";
510 let ParserMatchClass = mc;
513 def tfe : tfe_base <TFEMubufMatchClass>;
514 def tfe_flat : tfe_base <TFEFlatMatchClass>;
515 def tfe_flat_atomic : tfe_base <TFEFlatAtomicMatchClass>;
517 def omod : Operand <i32> {
518 let PrintMethod = "printOModSI";
519 let ParserMatchClass = OModMatchClass;
522 def ClampMod : Operand <i1> {
523 let PrintMethod = "printClampSI";
524 let ParserMatchClass = ClampMatchClass;
527 def smrd_offset : Operand <i32> {
528 let PrintMethod = "printU32ImmOperand";
529 let ParserMatchClass = SMRDOffsetMatchClass;
532 def smrd_literal_offset : Operand <i32> {
533 let PrintMethod = "printU32ImmOperand";
534 let ParserMatchClass = SMRDLiteralOffsetMatchClass;
537 } // End OperandType = "OPERAND_IMMEDIATE"
539 def VOPDstS64 : VOPDstOperand <SReg_64>;
541 //===----------------------------------------------------------------------===//
543 //===----------------------------------------------------------------------===//
545 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
546 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
548 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
549 def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">;
550 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
551 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
552 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
553 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
555 def SMRDImm : ComplexPattern<i64, 2, "SelectSMRDImm">;
556 def SMRDImm32 : ComplexPattern<i64, 2, "SelectSMRDImm32">;
557 def SMRDSgpr : ComplexPattern<i64, 2, "SelectSMRDSgpr">;
558 def SMRDBufferImm : ComplexPattern<i32, 1, "SelectSMRDBufferImm">;
559 def SMRDBufferImm32 : ComplexPattern<i32, 1, "SelectSMRDBufferImm32">;
560 def SMRDBufferSgpr : ComplexPattern<i32, 1, "SelectSMRDBufferSgpr">;
562 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
563 def VOP3NoMods0 : ComplexPattern<untyped, 4, "SelectVOP3NoMods0">;
564 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
565 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
566 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
567 def VOP3NoMods : ComplexPattern<untyped, 2, "SelectVOP3NoMods">;
569 //===----------------------------------------------------------------------===//
570 // SI assembler operands
571 //===----------------------------------------------------------------------===//
592 //===----------------------------------------------------------------------===//
594 // SI Instruction multiclass helpers.
596 // Instructions with _32 take 32-bit operands.
597 // Instructions with _64 take 64-bit operands.
599 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
600 // encoding is the standard encoding, but instruction that make use of
601 // any of the instruction modifiers must use the 64-bit encoding.
603 // Instructions with _e32 use the 32-bit encoding.
604 // Instructions with _e64 use the 64-bit encoding.
606 //===----------------------------------------------------------------------===//
608 class SIMCInstr <string pseudo, int subtarget> {
609 string PseudoInstr = pseudo;
610 int Subtarget = subtarget;
613 //===----------------------------------------------------------------------===//
615 //===----------------------------------------------------------------------===//
617 class EXPCommon : InstSI<
619 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
620 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
621 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
630 let isPseudo = 1, isCodeGenOnly = 1 in {
631 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
634 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
636 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
639 //===----------------------------------------------------------------------===//
641 //===----------------------------------------------------------------------===//
643 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
644 SOP1 <outs, ins, "", pattern>,
645 SIMCInstr<opName, SISubtarget.NONE> {
647 let isCodeGenOnly = 1;
650 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
651 SOP1 <outs, ins, asm, []>,
653 SIMCInstr<opName, SISubtarget.SI> {
654 let isCodeGenOnly = 0;
655 let AssemblerPredicates = [isSICI];
658 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
659 SOP1 <outs, ins, asm, []>,
661 SIMCInstr<opName, SISubtarget.VI> {
662 let isCodeGenOnly = 0;
663 let AssemblerPredicates = [isVI];
666 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
669 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
671 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
673 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
677 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
678 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
679 opName#" $dst, $src0", pattern
682 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
683 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
684 opName#" $dst, $src0", pattern
687 // no input, 64-bit output.
688 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
689 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
691 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
696 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
702 // 64-bit input, no output
703 multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
704 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
706 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
711 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
717 // 64-bit input, 32-bit output.
718 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
719 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
720 opName#" $dst, $src0", pattern
723 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
724 SOP2<outs, ins, "", pattern>,
725 SIMCInstr<opName, SISubtarget.NONE> {
727 let isCodeGenOnly = 1;
730 // Pseudo instructions have no encodings, but adding this field here allows
732 // let sdst = xxx in {
733 // for multiclasses that include both real and pseudo instructions.
734 field bits<7> sdst = 0;
737 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
738 SOP2<outs, ins, asm, []>,
740 SIMCInstr<opName, SISubtarget.SI> {
741 let AssemblerPredicates = [isSICI];
744 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
745 SOP2<outs, ins, asm, []>,
747 SIMCInstr<opName, SISubtarget.VI> {
748 let AssemblerPredicates = [isVI];
751 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
754 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
756 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
758 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
762 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
763 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
764 opName#" $dst, $src0, $src1", pattern
767 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
768 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
769 opName#" $dst, $src0, $src1", pattern
772 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
773 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
774 opName#" $dst, $src0, $src1", pattern
777 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
778 string opName, PatLeaf cond> : SOPC <
779 op, (outs), (ins rc:$src0, rc:$src1),
780 opName#" $src0, $src1", []> {
784 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
785 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
787 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
788 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
790 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
791 SOPK <outs, ins, "", pattern>,
792 SIMCInstr<opName, SISubtarget.NONE> {
794 let isCodeGenOnly = 1;
797 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
798 SOPK <outs, ins, asm, []>,
800 SIMCInstr<opName, SISubtarget.SI> {
801 let AssemblerPredicates = [isSICI];
802 let isCodeGenOnly = 0;
805 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
806 SOPK <outs, ins, asm, []>,
808 SIMCInstr<opName, SISubtarget.VI> {
809 let AssemblerPredicates = [isVI];
810 let isCodeGenOnly = 0;
813 multiclass SOPK_m <sopk op, string opName, dag outs, dag ins, string opAsm,
814 string asm = opName#opAsm> {
815 def "" : SOPK_Pseudo <opName, outs, ins, []>;
817 def _si : SOPK_Real_si <op, opName, outs, ins, asm>;
819 def _vi : SOPK_Real_vi <op, opName, outs, ins, asm>;
823 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
824 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
827 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
828 opName#" $dst, $src0">;
830 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
831 opName#" $dst, $src0">;
834 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
835 def "" : SOPK_Pseudo <opName, (outs),
836 (ins SReg_32:$src0, u16imm:$src1), pattern> {
841 def _si : SOPK_Real_si <op, opName, (outs),
842 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16"> {
846 def _vi : SOPK_Real_vi <op, opName, (outs),
847 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16"> {
852 multiclass SOPK_32TIE <sopk op, string opName, list<dag> pattern> : SOPK_m <
853 op, opName, (outs SReg_32:$sdst), (ins SReg_32:$src0, u16imm:$simm16),
857 multiclass SOPK_IMM32 <sopk op, string opName, dag outs, dag ins,
858 string argAsm, string asm = opName#argAsm> {
860 def "" : SOPK_Pseudo <opName, outs, ins, []>;
862 def _si : SOPK <outs, ins, asm, []>,
864 SIMCInstr<opName, SISubtarget.SI> {
865 let AssemblerPredicates = [isSICI];
866 let isCodeGenOnly = 0;
869 def _vi : SOPK <outs, ins, asm, []>,
871 SIMCInstr<opName, SISubtarget.VI> {
872 let AssemblerPredicates = [isVI];
873 let isCodeGenOnly = 0;
876 //===----------------------------------------------------------------------===//
878 //===----------------------------------------------------------------------===//
880 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
881 SMRD <outs, ins, "", pattern>,
882 SIMCInstr<opName, SISubtarget.NONE> {
884 let isCodeGenOnly = 1;
887 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
889 SMRD <outs, ins, asm, []>,
891 SIMCInstr<opName, SISubtarget.SI> {
892 let AssemblerPredicates = [isSICI];
895 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
897 SMRD <outs, ins, asm, []>,
899 SIMCInstr<opName, SISubtarget.VI> {
900 let AssemblerPredicates = [isVI];
903 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
904 string asm, list<dag> pattern> {
906 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
908 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
910 // glc is only applicable to scalar stores, which are not yet
913 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
917 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
918 RegisterClass dstClass> {
920 op, opName#"_IMM", 1, (outs dstClass:$dst),
921 (ins baseClass:$sbase, smrd_offset:$offset),
922 opName#" $dst, $sbase, $offset", []
926 (outs dstClass:$dst), (ins baseClass:$sbase, smrd_literal_offset:$offset),
927 opName#" $dst, $sbase, $offset", []>, SMRD_IMMe_ci <op> {
928 let AssemblerPredicates = [isCIOnly];
931 defm _SGPR : SMRD_m <
932 op, opName#"_SGPR", 0, (outs dstClass:$dst),
933 (ins baseClass:$sbase, SReg_32:$soff),
934 opName#" $dst, $sbase, $soff", []
938 //===----------------------------------------------------------------------===//
939 // Vector ALU classes
940 //===----------------------------------------------------------------------===//
942 // This must always be right before the operand being input modified.
943 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
944 let PrintMethod = "printOperandAndMods";
947 def InputModsMatchClass : AsmOperandClass {
948 let Name = "RegWithInputMods";
951 def InputModsNoDefault : Operand <i32> {
952 let PrintMethod = "printOperandAndMods";
953 let ParserMatchClass = InputModsMatchClass;
956 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
958 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
959 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
963 // Returns the register class to use for the destination of VOP[123C]
964 // instructions for the given VT.
965 class getVALUDstForVT<ValueType VT> {
966 RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
967 !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
968 VOPDstOperand<SReg_64>)); // else VT == i1
971 // Returns the register class to use for source 0 of VOP[12C]
972 // instructions for the given VT.
973 class getVOPSrc0ForVT<ValueType VT> {
974 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
977 // Returns the register class to use for source 1 of VOP[12C] for the
979 class getVOPSrc1ForVT<ValueType VT> {
980 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
983 // Returns the register class to use for sources of VOP3 instructions for the
985 class getVOP3SrcForVT<ValueType VT> {
986 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
989 // Returns 1 if the source arguments have modifiers, 0 if they do not.
990 class hasModifiers<ValueType SrcVT> {
991 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
992 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
995 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
996 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
997 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
998 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1002 // Returns the input arguments for VOP3 instructions for the given SrcVT.
1003 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
1004 RegisterOperand Src2RC, int NumSrcArgs,
1008 !if (!eq(NumSrcArgs, 1),
1009 !if (!eq(HasModifiers, 1),
1010 // VOP1 with modifiers
1011 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
1012 ClampMod:$clamp, omod:$omod)
1014 // VOP1 without modifiers
1017 !if (!eq(NumSrcArgs, 2),
1018 !if (!eq(HasModifiers, 1),
1019 // VOP 2 with modifiers
1020 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
1021 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
1022 ClampMod:$clamp, omod:$omod)
1024 // VOP2 without modifiers
1025 (ins Src0RC:$src0, Src1RC:$src1)
1027 /* NumSrcArgs == 3 */,
1028 !if (!eq(HasModifiers, 1),
1029 // VOP3 with modifiers
1030 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
1031 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
1032 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
1033 ClampMod:$clamp, omod:$omod)
1035 // VOP3 without modifiers
1036 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
1040 // Returns the assembly string for the inputs and outputs of a VOP[12C]
1041 // instruction. This does not add the _e32 suffix, so it can be reused
1043 class getAsm32 <int NumSrcArgs> {
1044 string src1 = ", $src1";
1045 string src2 = ", $src2";
1046 string ret = "$dst, $src0"#
1047 !if(!eq(NumSrcArgs, 1), "", src1)#
1048 !if(!eq(NumSrcArgs, 3), src2, "");
1051 // Returns the assembly string for the inputs and outputs of a VOP3
1053 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
1054 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
1055 string src1 = !if(!eq(NumSrcArgs, 1), "",
1056 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
1057 " $src1_modifiers,"));
1058 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
1060 !if(!eq(HasModifiers, 0),
1061 getAsm32<NumSrcArgs>.ret,
1062 "$dst, "#src0#src1#src2#"$clamp"#"$omod");
1066 class VOPProfile <list<ValueType> _ArgVT> {
1068 field list<ValueType> ArgVT = _ArgVT;
1070 field ValueType DstVT = ArgVT[0];
1071 field ValueType Src0VT = ArgVT[1];
1072 field ValueType Src1VT = ArgVT[2];
1073 field ValueType Src2VT = ArgVT[3];
1074 field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
1075 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
1076 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
1077 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
1078 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
1079 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
1081 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
1082 field bit HasModifiers = hasModifiers<Src0VT>.ret;
1084 field dag Outs = (outs DstRC:$dst);
1086 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
1087 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
1090 field string Asm32 = getAsm32<NumSrcArgs>.ret;
1091 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
1094 // FIXME: I think these F16/I16 profiles will need to use f16/i16 types in order
1095 // for the instruction patterns to work.
1096 def VOP_F16_F16 : VOPProfile <[f32, f32, untyped, untyped]>;
1097 def VOP_F16_I16 : VOPProfile <[f32, i32, untyped, untyped]>;
1098 def VOP_I16_F16 : VOPProfile <[i32, f32, untyped, untyped]>;
1100 def VOP_F16_F16_F16 : VOPProfile <[f32, f32, f32, untyped]>;
1101 def VOP_F16_F16_I16 : VOPProfile <[f32, f32, i32, untyped]>;
1102 def VOP_I16_I16_I16 : VOPProfile <[i32, i32, i32, untyped]>;
1104 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
1105 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
1106 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
1107 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
1108 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
1109 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
1110 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
1111 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
1112 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
1114 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
1115 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
1116 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
1117 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
1118 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
1119 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
1120 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
1121 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
1122 let Src0RC32 = VCSrc_32;
1125 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
1126 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
1127 let Asm64 = "$dst, $src0_modifiers, $src1";
1130 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
1131 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
1132 let Asm64 = "$dst, $src0_modifiers, $src1";
1135 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
1136 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
1137 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
1138 def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> {
1139 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VCCReg:$src2);
1140 let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
1141 let Asm64 = "$dst, $src0, $src1, $src2";
1144 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
1145 def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {
1146 field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
1147 field string Asm = "$dst, $src0, $vsrc1, $src2";
1149 def VOP_MAC : VOPProfile <[f32, f32, f32, f32]> {
1150 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);
1151 let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3,
1153 let Asm32 = getAsm32<2>.ret;
1154 let Asm64 = getAsm64<2, HasModifiers>.ret;
1156 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
1157 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
1158 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
1161 class VOP <string opName> {
1162 string OpName = opName;
1165 class VOP2_REV <string revOp, bit isOrig> {
1166 string RevOp = revOp;
1167 bit IsOrig = isOrig;
1170 class AtomicNoRet <string noRetOp, bit isRet> {
1171 string NoRetOp = noRetOp;
1175 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1176 VOP1Common <outs, ins, "", pattern>,
1178 SIMCInstr <opName#"_e32", SISubtarget.NONE>,
1179 MnemonicAlias<opName#"_e32", opName> {
1181 let isCodeGenOnly = 1;
1187 class VOP1_Real_si <string opName, vop1 op, dag outs, dag ins, string asm> :
1188 VOP1<op.SI, outs, ins, asm, []>,
1189 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1190 let AssemblerPredicate = SIAssemblerPredicate;
1193 class VOP1_Real_vi <string opName, vop1 op, dag outs, dag ins, string asm> :
1194 VOP1<op.VI, outs, ins, asm, []>,
1195 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1196 let AssemblerPredicates = [isVI];
1199 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
1201 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
1203 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
1205 def _vi : VOP1_Real_vi <opName, op, outs, ins, asm>;
1208 multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
1210 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
1212 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
1215 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1216 VOP2Common <outs, ins, "", pattern>,
1218 SIMCInstr<opName#"_e32", SISubtarget.NONE>,
1219 MnemonicAlias<opName#"_e32", opName> {
1221 let isCodeGenOnly = 1;
1224 class VOP2_Real_si <string opName, vop2 op, dag outs, dag ins, string asm> :
1225 VOP2 <op.SI, outs, ins, opName#asm, []>,
1226 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1227 let AssemblerPredicates = [isSICI];
1230 class VOP2_Real_vi <string opName, vop2 op, dag outs, dag ins, string asm> :
1231 VOP2 <op.VI, outs, ins, opName#asm, []>,
1232 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1233 let AssemblerPredicates = [isVI];
1236 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
1237 string opName, string revOp> {
1238 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
1239 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
1241 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
1244 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
1245 string opName, string revOp> {
1246 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
1247 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
1249 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
1251 def _vi : VOP2_Real_vi <opName, op, outs, ins, asm>;
1255 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
1257 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
1258 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
1259 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0);
1260 bits<2> omod = !if(HasModifiers, ?, 0);
1261 bits<1> clamp = !if(HasModifiers, ?, 0);
1262 bits<9> src1 = !if(HasSrc1, ?, 0);
1263 bits<9> src2 = !if(HasSrc2, ?, 0);
1266 class VOP3DisableModFields <bit HasSrc0Mods,
1267 bit HasSrc1Mods = 0,
1268 bit HasSrc2Mods = 0,
1269 bit HasOutputMods = 0> {
1270 bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0);
1271 bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0);
1272 bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0);
1273 bits<2> omod = !if(HasOutputMods, ?, 0);
1274 bits<1> clamp = !if(HasOutputMods, ?, 0);
1277 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1278 VOP3Common <outs, ins, "", pattern>,
1280 SIMCInstr<opName#"_e64", SISubtarget.NONE>,
1281 MnemonicAlias<opName#"_e64", opName> {
1283 let isCodeGenOnly = 1;
1286 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1287 VOP3Common <outs, ins, asm, []>,
1289 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1290 let AssemblerPredicates = [isSICI];
1293 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1294 VOP3Common <outs, ins, asm, []>,
1296 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1297 let AssemblerPredicates = [isVI];
1300 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1301 VOP3Common <outs, ins, asm, []>,
1303 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1304 let AssemblerPredicates = [isSICI];
1307 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1308 VOP3Common <outs, ins, asm, []>,
1310 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1311 let AssemblerPredicates = [isVI];
1314 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
1315 string opName, int NumSrcArgs, bit HasMods = 1> {
1317 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1319 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1320 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1321 !if(!eq(NumSrcArgs, 2), 0, 1),
1323 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1324 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1325 !if(!eq(NumSrcArgs, 2), 0, 1),
1329 // VOP3_m without source modifiers
1330 multiclass VOP3_m_nomods <vop op, dag outs, dag ins, string asm, list<dag> pattern,
1331 string opName, int NumSrcArgs, bit HasMods = 1> {
1333 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1335 let src0_modifiers = 0,
1340 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
1341 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
1345 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
1346 list<dag> pattern, string opName, bit HasMods = 1> {
1348 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1350 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1351 VOP3DisableFields<0, 0, HasMods>;
1353 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1354 VOP3DisableFields<0, 0, HasMods>;
1357 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
1358 list<dag> pattern, string opName, bit HasMods = 1> {
1360 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1362 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1363 VOP3DisableFields<0, 0, HasMods>;
1364 // No VI instruction. This class is for SI only.
1367 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
1368 list<dag> pattern, string opName, string revOp,
1369 bit HasMods = 1, bit UseFullOp = 0> {
1371 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1372 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1374 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1375 VOP3DisableFields<1, 0, HasMods>;
1377 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1378 VOP3DisableFields<1, 0, HasMods>;
1381 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
1382 list<dag> pattern, string opName, string revOp,
1383 bit HasMods = 1, bit UseFullOp = 0> {
1385 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1386 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1388 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1389 VOP3DisableFields<1, 0, HasMods>;
1391 // No VI instruction. This class is for SI only.
1394 // XXX - Is v_div_scale_{f32|f64} only available in vop3b without
1395 // option of implicit vcc use?
1396 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
1397 list<dag> pattern, string opName, string revOp,
1398 bit HasMods = 1, bit UseFullOp = 0> {
1399 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1400 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1402 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
1403 // can write it into any SGPR. We currently don't use the carry out,
1404 // so for now hardcode it to VCC as well.
1405 let sdst = SIOperand.VCC, Defs = [VCC] in {
1406 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1407 VOP3DisableFields<1, 0, HasMods>;
1409 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1410 VOP3DisableFields<1, 0, HasMods>;
1411 } // End sdst = SIOperand.VCC, Defs = [VCC]
1414 multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
1415 list<dag> pattern, string opName, string revOp,
1416 bit HasMods = 1, bit UseFullOp = 0> {
1417 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1420 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1421 VOP3DisableFields<1, 1, HasMods>;
1423 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1424 VOP3DisableFields<1, 1, HasMods>;
1427 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1428 list<dag> pattern, string opName,
1429 bit HasMods, bit defExec, string revOp> {
1431 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1432 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1434 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1435 VOP3DisableFields<1, 0, HasMods> {
1436 let Defs = !if(defExec, [EXEC], []);
1439 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1440 VOP3DisableFields<1, 0, HasMods> {
1441 let Defs = !if(defExec, [EXEC], []);
1445 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1446 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1447 string asm, list<dag> pattern = []> {
1448 let isPseudo = 1, isCodeGenOnly = 1 in {
1449 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1450 SIMCInstr<opName, SISubtarget.NONE>;
1453 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1454 SIMCInstr <opName, SISubtarget.SI> {
1455 let AssemblerPredicates = [isSICI];
1458 def _vi : VOP3Common <outs, ins, asm, []>,
1460 VOP3DisableFields <1, 0, 0>,
1461 SIMCInstr <opName, SISubtarget.VI> {
1462 let AssemblerPredicates = [isVI];
1466 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1467 dag ins32, string asm32, list<dag> pat32,
1468 dag ins64, string asm64, list<dag> pat64,
1471 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1473 defm _e64 : VOP3_1_m <op, outs, ins64, opName#asm64, pat64, opName, HasMods>;
1476 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1477 SDPatternOperator node = null_frag> : VOP1_Helper <
1479 P.Ins32, P.Asm32, [],
1482 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1483 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1484 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1488 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1489 SDPatternOperator node = null_frag> {
1491 defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>;
1493 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1495 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1496 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1497 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1498 opName, P.HasModifiers>;
1501 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1502 dag ins32, string asm32, list<dag> pat32,
1503 dag ins64, string asm64, list<dag> pat64,
1504 string revOp, bit HasMods> {
1505 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1507 defm _e64 : VOP3_2_m <op,
1508 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1512 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1513 SDPatternOperator node = null_frag,
1514 string revOp = opName> : VOP2_Helper <
1516 P.Ins32, P.Asm32, [],
1520 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1521 i1:$clamp, i32:$omod)),
1522 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1523 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1524 revOp, P.HasModifiers
1527 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1528 SDPatternOperator node = null_frag,
1529 string revOp = opName> {
1530 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1532 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1535 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1536 i1:$clamp, i32:$omod)),
1537 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1538 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1539 opName, revOp, P.HasModifiers>;
1542 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1543 dag ins32, string asm32, list<dag> pat32,
1544 dag ins64, string asm64, list<dag> pat64,
1545 string revOp, bit HasMods> {
1547 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1549 defm _e64 : VOP3b_2_m <op,
1550 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1554 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1555 SDPatternOperator node = null_frag,
1556 string revOp = opName> : VOP2b_Helper <
1558 P.Ins32, P.Asm32, [],
1562 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1563 i1:$clamp, i32:$omod)),
1564 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1565 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1566 revOp, P.HasModifiers
1569 // A VOP2 instruction that is VOP3-only on VI.
1570 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1571 dag ins32, string asm32, list<dag> pat32,
1572 dag ins64, string asm64, list<dag> pat64,
1573 string revOp, bit HasMods> {
1574 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1576 defm _e64 : VOP3_2_m <op, outs, ins64, opName#asm64, pat64, opName,
1580 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1581 SDPatternOperator node = null_frag,
1582 string revOp = opName>
1585 P.Ins32, P.Asm32, [],
1589 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1590 i1:$clamp, i32:$omod)),
1591 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1592 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1593 revOp, P.HasModifiers
1596 multiclass VOP2MADK <vop2 op, string opName, list<dag> pattern = []> {
1598 def "" : VOP2_Pseudo <VOP_MADK.Outs, VOP_MADK.Ins, pattern, opName>;
1600 let isCodeGenOnly = 0 in {
1601 def _si : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1602 !strconcat(opName, VOP_MADK.Asm), []>,
1603 SIMCInstr <opName#"_e32", SISubtarget.SI>,
1604 VOP2_MADKe <op.SI> {
1605 let AssemblerPredicates = [isSICI];
1608 def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1609 !strconcat(opName, VOP_MADK.Asm), []>,
1610 SIMCInstr <opName#"_e32", SISubtarget.VI>,
1611 VOP2_MADKe <op.VI> {
1612 let AssemblerPredicates = [isVI];
1614 } // End isCodeGenOnly = 0
1617 class VOPC_Pseudo <dag ins, list<dag> pattern, string opName> :
1618 VOPCCommon <ins, "", pattern>,
1620 SIMCInstr<opName#"_e32", SISubtarget.NONE>,
1621 MnemonicAlias<opName#"_e32", opName> {
1623 let isCodeGenOnly = 1;
1626 multiclass VOPC_m <vopc op, dag ins, string asm, list<dag> pattern,
1627 string opName, bit DefExec, string revOpName = ""> {
1628 def "" : VOPC_Pseudo <ins, pattern, opName>;
1630 def _si : VOPC<op.SI, ins, asm, []>,
1631 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1632 let Defs = !if(DefExec, [EXEC], []);
1633 let hasSideEffects = DefExec;
1636 def _vi : VOPC<op.VI, ins, asm, []>,
1637 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1638 let Defs = !if(DefExec, [EXEC], []);
1639 let hasSideEffects = DefExec;
1643 multiclass VOPC_Helper <vopc op, string opName,
1644 dag ins32, string asm32, list<dag> pat32,
1645 dag out64, dag ins64, string asm64, list<dag> pat64,
1646 bit HasMods, bit DefExec, string revOp> {
1647 defm _e32 : VOPC_m <op, ins32, opName#asm32, pat32, opName, DefExec>;
1649 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1650 opName, HasMods, DefExec, revOp>;
1653 // Special case for class instructions which only have modifiers on
1654 // the 1st source operand.
1655 multiclass VOPC_Class_Helper <vopc op, string opName,
1656 dag ins32, string asm32, list<dag> pat32,
1657 dag out64, dag ins64, string asm64, list<dag> pat64,
1658 bit HasMods, bit DefExec, string revOp> {
1659 defm _e32 : VOPC_m <op, ins32, opName#asm32, pat32, opName, DefExec>;
1661 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1662 opName, HasMods, DefExec, revOp>,
1663 VOP3DisableModFields<1, 0, 0>;
1666 multiclass VOPCInst <vopc op, string opName,
1667 VOPProfile P, PatLeaf cond = COND_NULL,
1668 string revOp = opName,
1669 bit DefExec = 0> : VOPC_Helper <
1671 P.Ins32, P.Asm32, [],
1672 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1675 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1676 i1:$clamp, i32:$omod)),
1677 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1679 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1680 P.HasModifiers, DefExec, revOp
1683 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1684 bit DefExec = 0> : VOPC_Class_Helper <
1686 P.Ins32, P.Asm32, [],
1687 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1690 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1691 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1692 P.HasModifiers, DefExec, opName
1696 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1697 VOPCInst <op, opName, VOP_F32_F32_F32, cond, revOp>;
1699 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1700 VOPCInst <op, opName, VOP_F64_F64_F64, cond, revOp>;
1702 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1703 VOPCInst <op, opName, VOP_I32_I32_I32, cond, revOp>;
1705 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1706 VOPCInst <op, opName, VOP_I64_I64_I64, cond, revOp>;
1709 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1710 PatLeaf cond = COND_NULL,
1712 : VOPCInst <op, opName, P, cond, revOp, 1>;
1714 multiclass VOPCX_F32 <vopc op, string opName, string revOp = opName> :
1715 VOPCX <op, opName, VOP_F32_F32_F32, COND_NULL, revOp>;
1717 multiclass VOPCX_F64 <vopc op, string opName, string revOp = opName> :
1718 VOPCX <op, opName, VOP_F64_F64_F64, COND_NULL, revOp>;
1720 multiclass VOPCX_I32 <vopc op, string opName, string revOp = opName> :
1721 VOPCX <op, opName, VOP_I32_I32_I32, COND_NULL, revOp>;
1723 multiclass VOPCX_I64 <vopc op, string opName, string revOp = opName> :
1724 VOPCX <op, opName, VOP_I64_I64_I64, COND_NULL, revOp>;
1726 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1727 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1728 op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods
1731 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1732 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1734 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1735 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1737 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1738 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1740 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1741 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1743 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1744 SDPatternOperator node = null_frag> : VOP3_Helper <
1745 op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64,
1746 !if(!eq(P.NumSrcArgs, 3),
1749 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1750 i1:$clamp, i32:$omod)),
1751 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1752 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1753 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1755 !if(!eq(P.NumSrcArgs, 2),
1758 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1759 i1:$clamp, i32:$omod)),
1760 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1761 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1762 /* P.NumSrcArgs == 1 */,
1765 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1766 i1:$clamp, i32:$omod))))],
1767 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1768 P.NumSrcArgs, P.HasModifiers
1771 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1772 // only VOP instruction that implicitly reads VCC.
1773 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1775 SDPatternOperator node = null_frag> : VOP3_Helper <
1777 (outs P.DstRC.RegClass:$dst),
1778 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1779 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1780 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1783 "$dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1785 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1786 i1:$clamp, i32:$omod)),
1787 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1788 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1793 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1794 string opName, list<dag> pattern> :
1796 op, (outs vrc:$vdst, SReg_64:$sdst),
1797 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1798 InputModsNoDefault:$src1_modifiers, arc:$src1,
1799 InputModsNoDefault:$src2_modifiers, arc:$src2,
1800 ClampMod:$clamp, omod:$omod),
1801 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1802 opName, opName, 1, 1
1805 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1806 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1808 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1809 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1812 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1813 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1814 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1815 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1816 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1817 i32:$src1_modifiers, P.Src1VT:$src1,
1818 i32:$src2_modifiers, P.Src2VT:$src2,
1822 //===----------------------------------------------------------------------===//
1823 // Interpolation opcodes
1824 //===----------------------------------------------------------------------===//
1826 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1827 VINTRPCommon <outs, ins, "", pattern>,
1828 SIMCInstr<opName, SISubtarget.NONE> {
1830 let isCodeGenOnly = 1;
1833 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1835 VINTRPCommon <outs, ins, asm, []>,
1837 SIMCInstr<opName, SISubtarget.SI>;
1839 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1841 VINTRPCommon <outs, ins, asm, []>,
1843 SIMCInstr<opName, SISubtarget.VI>;
1845 multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
1846 list<dag> pattern = []> {
1847 def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
1849 def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>;
1851 def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
1854 //===----------------------------------------------------------------------===//
1855 // Vector I/O classes
1856 //===----------------------------------------------------------------------===//
1858 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1859 DS <outs, ins, "", pattern>,
1860 SIMCInstr <opName, SISubtarget.NONE> {
1862 let isCodeGenOnly = 1;
1865 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1866 DS <outs, ins, asm, []>,
1868 SIMCInstr <opName, SISubtarget.SI> {
1869 let isCodeGenOnly = 0;
1872 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1873 DS <outs, ins, asm, []>,
1875 SIMCInstr <opName, SISubtarget.VI>;
1877 class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1878 DS_Real_si <op,opName, outs, ins, asm> {
1880 // Single load interpret the 2 i8imm operands as a single i16 offset.
1882 let offset0 = offset{7-0};
1883 let offset1 = offset{15-8};
1884 let isCodeGenOnly = 0;
1887 class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1888 DS_Real_vi <op, opName, outs, ins, asm> {
1890 // Single load interpret the 2 i8imm operands as a single i16 offset.
1892 let offset0 = offset{7-0};
1893 let offset1 = offset{15-8};
1896 multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc,
1897 dag outs = (outs rc:$vdst),
1898 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds),
1899 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
1901 def "" : DS_Pseudo <opName, outs, ins, []>;
1903 let data0 = 0, data1 = 0 in {
1904 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1905 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1909 multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc,
1910 dag outs = (outs rc:$vdst),
1911 dag ins = (ins VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1913 string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> {
1915 def "" : DS_Pseudo <opName, outs, ins, []>;
1917 let data0 = 0, data1 = 0, AsmMatchConverter = "cvtDSOffset01" in {
1918 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1919 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1923 multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc,
1925 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds),
1926 string asm = opName#" $addr, $data0"#"$offset$gds"> {
1928 def "" : DS_Pseudo <opName, outs, ins, []>,
1929 AtomicNoRet<opName, 0>;
1931 let data1 = 0, vdst = 0 in {
1932 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1933 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1937 multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc,
1939 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1940 ds_offset0:$offset0, ds_offset1:$offset1, gds01:$gds),
1941 string asm = opName#" $addr, $data0, $data1"#"$offset0"#"$offset1"#"$gds"> {
1943 def "" : DS_Pseudo <opName, outs, ins, []>;
1945 let vdst = 0, AsmMatchConverter = "cvtDSOffset01" in {
1946 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1947 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1951 multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc,
1952 string noRetOp = "",
1953 dag outs = (outs rc:$vdst),
1954 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds),
1955 string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> {
1957 def "" : DS_Pseudo <opName, outs, ins, []>,
1958 AtomicNoRet<noRetOp, 1>;
1961 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1962 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1966 multiclass DS_1A2D_RET_m <bits<8> op, string opName, RegisterClass rc,
1967 string noRetOp = "", dag ins,
1968 dag outs = (outs rc:$vdst),
1969 string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"#"$gds"> {
1971 def "" : DS_Pseudo <opName, outs, ins, []>,
1972 AtomicNoRet<noRetOp, 1>;
1974 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1975 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1978 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1979 string noRetOp = "", RegisterClass src = rc> :
1980 DS_1A2D_RET_m <op, asm, rc, noRetOp,
1981 (ins VGPR_32:$addr, src:$data0, src:$data1,
1982 ds_offset:$offset, gds:$gds)
1985 multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc,
1986 string noRetOp = opName,
1988 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1989 ds_offset:$offset, gds:$gds),
1990 string asm = opName#" $addr, $data0, $data1"#"$offset"#"$gds"> {
1992 def "" : DS_Pseudo <opName, outs, ins, []>,
1993 AtomicNoRet<noRetOp, 0>;
1996 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1997 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2001 multiclass DS_0A_RET <bits<8> op, string opName,
2002 dag outs = (outs VGPR_32:$vdst),
2003 dag ins = (ins ds_offset:$offset, gds:$gds),
2004 string asm = opName#" $vdst"#"$offset"#"$gds"> {
2006 let mayLoad = 1, mayStore = 1 in {
2007 def "" : DS_Pseudo <opName, outs, ins, []>;
2009 let addr = 0, data0 = 0, data1 = 0 in {
2010 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2011 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2012 } // end addr = 0, data0 = 0, data1 = 0
2013 } // end mayLoad = 1, mayStore = 1
2016 multiclass DS_1A_RET_GDS <bits<8> op, string opName,
2017 dag outs = (outs VGPR_32:$vdst),
2018 dag ins = (ins VGPR_32:$addr, ds_offset_gds:$offset),
2019 string asm = opName#" $vdst, $addr"#"$offset gds"> {
2021 def "" : DS_Pseudo <opName, outs, ins, []>;
2023 let data0 = 0, data1 = 0, gds = 1 in {
2024 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2025 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2026 } // end data0 = 0, data1 = 0, gds = 1
2029 multiclass DS_1A_GDS <bits<8> op, string opName,
2031 dag ins = (ins VGPR_32:$addr),
2032 string asm = opName#" $addr gds"> {
2034 def "" : DS_Pseudo <opName, outs, ins, []>;
2036 let vdst = 0, data0 = 0, data1 = 0, offset0 = 0, offset1 = 0, gds = 1 in {
2037 def _si : DS_Real_si <op, opName, outs, ins, asm>;
2038 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
2039 } // end vdst = 0, data = 0, data1 = 0, gds = 1
2042 multiclass DS_1A <bits<8> op, string opName,
2044 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds),
2045 string asm = opName#" $addr"#"$offset"#"$gds"> {
2047 let mayLoad = 1, mayStore = 1 in {
2048 def "" : DS_Pseudo <opName, outs, ins, []>;
2050 let vdst = 0, data0 = 0, data1 = 0 in {
2051 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2052 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2053 } // let vdst = 0, data0 = 0, data1 = 0
2054 } // end mayLoad = 1, mayStore = 1
2057 //===----------------------------------------------------------------------===//
2059 //===----------------------------------------------------------------------===//
2061 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2062 MTBUF <outs, ins, "", pattern>,
2063 SIMCInstr<opName, SISubtarget.NONE> {
2065 let isCodeGenOnly = 1;
2068 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
2070 MTBUF <outs, ins, asm, []>,
2072 SIMCInstr<opName, SISubtarget.SI>;
2074 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
2075 MTBUF <outs, ins, asm, []>,
2077 SIMCInstr <opName, SISubtarget.VI>;
2079 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
2080 list<dag> pattern> {
2082 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
2084 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
2086 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
2090 let mayStore = 1, mayLoad = 0 in {
2092 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
2093 RegisterClass regClass> : MTBUF_m <
2095 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
2096 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
2097 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2098 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
2099 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2102 } // mayStore = 1, mayLoad = 0
2104 let mayLoad = 1, mayStore = 0 in {
2106 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
2107 RegisterClass regClass> : MTBUF_m <
2108 op, opName, (outs regClass:$dst),
2109 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
2110 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
2111 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2112 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
2113 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2116 } // mayLoad = 1, mayStore = 0
2118 //===----------------------------------------------------------------------===//
2120 //===----------------------------------------------------------------------===//
2122 class mubuf <bits<7> si, bits<7> vi = si> {
2123 field bits<7> SI = si;
2124 field bits<7> VI = vi;
2127 let isCodeGenOnly = 0 in {
2129 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
2130 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
2134 } // End let isCodeGenOnly = 0
2136 class MUBUF_vi <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
2137 MUBUF <outs, ins, asm, pattern>, MUBUFe_vi <op> {
2141 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
2142 bit IsAddr64 = is_addr64;
2143 string OpName = NAME # suffix;
2146 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2147 MUBUF <outs, ins, "", pattern>,
2148 SIMCInstr<opName, SISubtarget.NONE> {
2150 let isCodeGenOnly = 1;
2152 // dummy fields, so that we can use let statements around multiclasses
2162 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
2164 MUBUF <outs, ins, asm, []>,
2166 SIMCInstr<opName, SISubtarget.SI> {
2170 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
2172 MUBUF <outs, ins, asm, []>,
2174 SIMCInstr<opName, SISubtarget.VI> {
2178 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
2179 list<dag> pattern> {
2181 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2182 MUBUFAddr64Table <0>;
2184 let addr64 = 0, isCodeGenOnly = 0 in {
2185 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2188 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2191 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
2192 dag ins, string asm, list<dag> pattern> {
2194 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2195 MUBUFAddr64Table <1>;
2197 let addr64 = 1, isCodeGenOnly = 0 in {
2198 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2201 // There is no VI version. If the pseudo is selected, it should be lowered
2202 // for VI appropriately.
2205 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
2206 string asm, list<dag> pattern, bit is_return> {
2208 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2209 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
2210 AtomicNoRet<NAME#"_OFFSET", is_return>;
2212 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
2214 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2217 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2221 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
2222 string asm, list<dag> pattern, bit is_return> {
2224 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2225 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
2226 AtomicNoRet<NAME#"_ADDR64", is_return>;
2228 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
2229 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2232 // There is no VI version. If the pseudo is selected, it should be lowered
2233 // for VI appropriately.
2236 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
2237 ValueType vt, SDPatternOperator atomic> {
2239 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
2241 // No return variants
2244 defm _ADDR64 : MUBUFAtomicAddr64_m <
2245 op, name#"_addr64", (outs),
2246 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
2247 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2248 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
2251 defm _OFFSET : MUBUFAtomicOffset_m <
2252 op, name#"_offset", (outs),
2253 (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset,
2255 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
2259 // Variant that return values
2260 let glc = 1, Constraints = "$vdata = $vdata_in",
2261 DisableEncoding = "$vdata_in" in {
2263 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
2264 op, name#"_rtn_addr64", (outs rc:$vdata),
2265 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
2266 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2267 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
2269 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
2270 i16:$offset, i1:$slc), vt:$vdata_in))], 1
2273 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
2274 op, name#"_rtn_offset", (outs rc:$vdata),
2275 (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset,
2276 mbuf_offset:$offset, slc:$slc),
2277 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
2279 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
2280 i1:$slc), vt:$vdata_in))], 1
2285 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
2288 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
2289 ValueType load_vt = i32,
2290 SDPatternOperator ld = null_frag> {
2292 let mayLoad = 1, mayStore = 0 in {
2293 let offen = 0, idxen = 0, vaddr = 0 in {
2294 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
2295 (ins SReg_128:$srsrc, SCSrc_32:$soffset,
2296 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2297 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2298 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
2299 i32:$soffset, i16:$offset,
2300 i1:$glc, i1:$slc, i1:$tfe)))]>;
2303 let offen = 1, idxen = 0 in {
2304 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
2305 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2306 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
2308 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2311 let offen = 0, idxen = 1 in {
2312 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
2313 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2314 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2315 slc:$slc, tfe:$tfe),
2316 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2319 let offen = 1, idxen = 1 in {
2320 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
2321 (ins VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2322 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2323 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2326 let offen = 0, idxen = 0 in {
2327 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
2328 (ins VReg_64:$vaddr, SReg_128:$srsrc,
2329 SCSrc_32:$soffset, mbuf_offset:$offset,
2330 glc:$glc, slc:$slc, tfe:$tfe),
2331 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#
2332 "$glc"#"$slc"#"$tfe",
2333 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
2334 i64:$vaddr, i32:$soffset,
2335 i16:$offset, i1:$glc, i1:$slc,
2341 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
2342 ValueType store_vt = i32, SDPatternOperator st = null_frag> {
2343 let mayLoad = 0, mayStore = 1 in {
2344 defm : MUBUF_m <op, name, (outs),
2345 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2346 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
2348 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
2349 "$glc"#"$slc"#"$tfe", []>;
2351 let offen = 0, idxen = 0, vaddr = 0 in {
2352 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
2353 (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset,
2354 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2355 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2356 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
2357 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
2358 } // offen = 0, idxen = 0, vaddr = 0
2360 let offen = 1, idxen = 0 in {
2361 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
2362 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2363 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2364 slc:$slc, tfe:$tfe),
2365 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
2366 "$glc"#"$slc"#"$tfe", []>;
2367 } // end offen = 1, idxen = 0
2369 let offen = 0, idxen = 1 in {
2370 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs),
2371 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2372 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2373 slc:$slc, tfe:$tfe),
2374 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2377 let offen = 1, idxen = 1 in {
2378 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs),
2379 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2380 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2381 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2384 let offen = 0, idxen = 0 in {
2385 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
2386 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc,
2388 mbuf_offset:$offset, glc:$glc, slc:$slc,
2390 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#
2391 "$offset"#"$glc"#"$slc"#"$tfe",
2392 [(st store_vt:$vdata,
2393 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
2394 i32:$soffset, i16:$offset,
2395 i1:$glc, i1:$slc, i1:$tfe))]>;
2397 } // End mayLoad = 0, mayStore = 1
2400 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
2401 FLAT <op, (outs regClass:$vdst),
2402 (ins VReg_64:$addr, glc_flat:$glc, slc_flat:$slc, tfe_flat:$tfe),
2403 asm#" $vdst, $addr"#"$glc"#"$slc"#"$tfe", []> {
2408 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
2409 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr,
2410 glc_flat:$glc, slc_flat:$slc, tfe_flat:$tfe),
2411 name#" $data, $addr"#"$glc"#"$slc"#"$tfe",
2421 multiclass FLAT_ATOMIC <bits<7> op, string name, RegisterClass vdst_rc,
2422 RegisterClass data_rc = vdst_rc> {
2424 let mayLoad = 1, mayStore = 1 in {
2425 def "" : FLAT <op, (outs),
2426 (ins VReg_64:$addr, data_rc:$data, slc_flat_atomic:$slc,
2427 tfe_flat_atomic:$tfe),
2428 name#" $addr, $data"#"$slc"#"$tfe", []>,
2429 AtomicNoRet <NAME, 0> {
2434 def _RTN : FLAT <op, (outs vdst_rc:$vdst),
2435 (ins VReg_64:$addr, data_rc:$data, slc_flat_atomic:$slc,
2436 tfe_flat_atomic:$tfe),
2437 name#" $vdst, $addr, $data glc"#"$slc"#"$tfe", []>,
2438 AtomicNoRet <NAME, 1> {
2444 class MIMG_Mask <string op, int channels> {
2446 int Channels = channels;
2449 class MIMG_NoSampler_Helper <bits<7> op, string asm,
2450 RegisterClass dst_rc,
2451 RegisterClass src_rc> : MIMG <
2453 (outs dst_rc:$vdata),
2454 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2455 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2457 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2458 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
2463 let hasPostISelHook = 1;
2466 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
2467 RegisterClass dst_rc,
2469 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
2470 MIMG_Mask<asm#"_V1", channels>;
2471 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
2472 MIMG_Mask<asm#"_V2", channels>;
2473 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
2474 MIMG_Mask<asm#"_V4", channels>;
2477 multiclass MIMG_NoSampler <bits<7> op, string asm> {
2478 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
2479 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
2480 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
2481 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
2484 class MIMG_Sampler_Helper <bits<7> op, string asm,
2485 RegisterClass dst_rc,
2486 RegisterClass src_rc, int wqm> : MIMG <
2488 (outs dst_rc:$vdata),
2489 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2490 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2491 SReg_256:$srsrc, SReg_128:$ssamp),
2492 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2493 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2497 let hasPostISelHook = 1;
2501 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2502 RegisterClass dst_rc,
2503 int channels, int wqm> {
2504 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2505 MIMG_Mask<asm#"_V1", channels>;
2506 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2507 MIMG_Mask<asm#"_V2", channels>;
2508 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2509 MIMG_Mask<asm#"_V4", channels>;
2510 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2511 MIMG_Mask<asm#"_V8", channels>;
2512 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2513 MIMG_Mask<asm#"_V16", channels>;
2516 multiclass MIMG_Sampler <bits<7> op, string asm> {
2517 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2518 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2519 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2520 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2523 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2524 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2525 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2526 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2527 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2530 class MIMG_Gather_Helper <bits<7> op, string asm,
2531 RegisterClass dst_rc,
2532 RegisterClass src_rc, int wqm> : MIMG <
2534 (outs dst_rc:$vdata),
2535 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2536 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2537 SReg_256:$srsrc, SReg_128:$ssamp),
2538 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2539 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2544 // DMASK was repurposed for GATHER4. 4 components are always
2545 // returned and DMASK works like a swizzle - it selects
2546 // the component to fetch. The only useful DMASK values are
2547 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2548 // (red,red,red,red) etc.) The ISA document doesn't mention
2550 // Therefore, disable all code which updates DMASK by setting these two:
2552 let hasPostISelHook = 0;
2556 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2557 RegisterClass dst_rc,
2558 int channels, int wqm> {
2559 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2560 MIMG_Mask<asm#"_V1", channels>;
2561 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2562 MIMG_Mask<asm#"_V2", channels>;
2563 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2564 MIMG_Mask<asm#"_V4", channels>;
2565 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2566 MIMG_Mask<asm#"_V8", channels>;
2567 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2568 MIMG_Mask<asm#"_V16", channels>;
2571 multiclass MIMG_Gather <bits<7> op, string asm> {
2572 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2573 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2574 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2575 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2578 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2579 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2580 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2581 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2582 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2585 //===----------------------------------------------------------------------===//
2586 // Vector instruction mappings
2587 //===----------------------------------------------------------------------===//
2589 // Maps an opcode in e32 form to its e64 equivalent
2590 def getVOPe64 : InstrMapping {
2591 let FilterClass = "VOP";
2592 let RowFields = ["OpName"];
2593 let ColFields = ["Size"];
2595 let ValueCols = [["8"]];
2598 // Maps an opcode in e64 form to its e32 equivalent
2599 def getVOPe32 : InstrMapping {
2600 let FilterClass = "VOP";
2601 let RowFields = ["OpName"];
2602 let ColFields = ["Size"];
2604 let ValueCols = [["4"]];
2607 def getMaskedMIMGOp : InstrMapping {
2608 let FilterClass = "MIMG_Mask";
2609 let RowFields = ["Op"];
2610 let ColFields = ["Channels"];
2612 let ValueCols = [["1"], ["2"], ["3"] ];
2615 // Maps an commuted opcode to its original version
2616 def getCommuteOrig : InstrMapping {
2617 let FilterClass = "VOP2_REV";
2618 let RowFields = ["RevOp"];
2619 let ColFields = ["IsOrig"];
2621 let ValueCols = [["1"]];
2624 // Maps an original opcode to its commuted version
2625 def getCommuteRev : InstrMapping {
2626 let FilterClass = "VOP2_REV";
2627 let RowFields = ["RevOp"];
2628 let ColFields = ["IsOrig"];
2630 let ValueCols = [["0"]];
2633 def getCommuteCmpOrig : InstrMapping {
2634 let FilterClass = "VOP2_REV";
2635 let RowFields = ["RevOp"];
2636 let ColFields = ["IsOrig"];
2638 let ValueCols = [["1"]];
2641 // Maps an original opcode to its commuted version
2642 def getCommuteCmpRev : InstrMapping {
2643 let FilterClass = "VOP2_REV";
2644 let RowFields = ["RevOp"];
2645 let ColFields = ["IsOrig"];
2647 let ValueCols = [["0"]];
2651 def getMCOpcodeGen : InstrMapping {
2652 let FilterClass = "SIMCInstr";
2653 let RowFields = ["PseudoInstr"];
2654 let ColFields = ["Subtarget"];
2655 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2656 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2659 def getAddr64Inst : InstrMapping {
2660 let FilterClass = "MUBUFAddr64Table";
2661 let RowFields = ["OpName"];
2662 let ColFields = ["IsAddr64"];
2664 let ValueCols = [["1"]];
2667 // Maps an atomic opcode to its version with a return value.
2668 def getAtomicRetOp : InstrMapping {
2669 let FilterClass = "AtomicNoRet";
2670 let RowFields = ["NoRetOp"];
2671 let ColFields = ["IsRet"];
2673 let ValueCols = [["1"]];
2676 // Maps an atomic opcode to its returnless version.
2677 def getAtomicNoRetOp : InstrMapping {
2678 let FilterClass = "AtomicNoRet";
2679 let RowFields = ["NoRetOp"];
2680 let ColFields = ["IsRet"];
2682 let ValueCols = [["0"]];
2685 include "SIInstructions.td"
2686 include "CIInstructions.td"
2687 include "VIInstructions.td"