1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 def isCI : Predicate<"Subtarget->getGeneration() "
10 ">= AMDGPUSubtarget::SEA_ISLANDS">;
11 def isCIOnly : Predicate<"Subtarget->getGeneration() =="
12 "AMDGPUSubtarget::SEA_ISLANDS">,
13 AssemblerPredicate <"FeatureSeaIslands">;
14 def isVI : Predicate <
15 "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
16 AssemblerPredicate<"FeatureGCN3Encoding">;
18 def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">;
25 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
26 field bits<8> SI = si;
27 field bits<8> VI = vi;
29 field bits<9> SI3 = {0, si{7-0}};
30 field bits<10> VI3 = {0, 0, vi{7-0}};
33 class vop1 <bits<8> si, bits<8> vi = si> : vop {
34 field bits<8> SI = si;
35 field bits<8> VI = vi;
37 field bits<9> SI3 = {1, 1, si{6-0}};
38 field bits<10> VI3 = !add(0x140, vi);
41 class vop2 <bits<6> si, bits<6> vi = si> : vop {
42 field bits<6> SI = si;
43 field bits<6> VI = vi;
45 field bits<9> SI3 = {1, 0, 0, si{5-0}};
46 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
49 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
50 // that doesn't have VOP2 encoding on VI
51 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
55 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
60 class sop1 <bits<8> si, bits<8> vi = si> {
61 field bits<8> SI = si;
62 field bits<8> VI = vi;
65 class sop2 <bits<7> si, bits<7> vi = si> {
66 field bits<7> SI = si;
67 field bits<7> VI = vi;
70 class sopk <bits<5> si, bits<5> vi = si> {
71 field bits<5> SI = si;
72 field bits<5> VI = vi;
75 // Specify an SMRD opcode for SI and SMEM opcode for VI
77 // FIXME: This should really be bits<5> si, Tablegen crashes if
78 // parameter default value is other parameter with different bit size
79 class smrd<bits<8> si, bits<8> vi = si> {
80 field bits<5> SI = si{4-0};
81 field bits<8> VI = vi;
84 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
85 // in AMDGPUInstrInfo.cpp
92 //===----------------------------------------------------------------------===//
94 //===----------------------------------------------------------------------===//
96 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
97 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
98 [SDNPMayLoad, SDNPMemOperand]
101 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
103 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
104 SDTCisVT<1, iAny>, // vdata(VGPR)
105 SDTCisVT<2, i32>, // num_channels(imm)
106 SDTCisVT<3, i32>, // vaddr(VGPR)
107 SDTCisVT<4, i32>, // soffset(SGPR)
108 SDTCisVT<5, i32>, // inst_offset(imm)
109 SDTCisVT<6, i32>, // dfmt(imm)
110 SDTCisVT<7, i32>, // nfmt(imm)
111 SDTCisVT<8, i32>, // offen(imm)
112 SDTCisVT<9, i32>, // idxen(imm)
113 SDTCisVT<10, i32>, // glc(imm)
114 SDTCisVT<11, i32>, // slc(imm)
115 SDTCisVT<12, i32> // tfe(imm)
117 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
120 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
121 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
125 class SDSample<string opcode> : SDNode <opcode,
126 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
127 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
130 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
131 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
132 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
133 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
135 def SIconstdata_ptr : SDNode<
136 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
139 //===----------------------------------------------------------------------===//
140 // SDNodes and PatFrag for local loads and stores to enable s_mov_b32 m0, -1
141 // to be glued to the memory instructions.
142 //===----------------------------------------------------------------------===//
144 def SIld_local : SDNode <"ISD::LOAD", SDTLoad,
145 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
148 def si_ld_local : PatFrag <(ops node:$ptr), (SIld_local node:$ptr), [{
149 return isLocalLoad(cast<LoadSDNode>(N));
152 def si_load_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{
153 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
154 cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
157 def si_load_local_align8 : Aligned8Bytes <
158 (ops node:$ptr), (si_load_local node:$ptr)
161 def si_sextload_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{
162 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
164 def si_az_extload_local : AZExtLoadBase <si_ld_local>;
166 multiclass SIExtLoadLocal <PatFrag ld_node> {
168 def _i8 : PatFrag <(ops node:$ptr), (ld_node node:$ptr),
169 [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;}]
172 def _i16 : PatFrag <(ops node:$ptr), (ld_node node:$ptr),
173 [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;}]
177 defm si_sextload_local : SIExtLoadLocal <si_sextload_local>;
178 defm si_az_extload_local : SIExtLoadLocal <si_az_extload_local>;
180 def SIst_local : SDNode <"ISD::STORE", SDTStore,
181 [SDNPHasChain, SDNPMayStore, SDNPMemOperand, SDNPInGlue]
184 def si_st_local : PatFrag <
185 (ops node:$val, node:$ptr), (SIst_local node:$val, node:$ptr), [{
186 return isLocalStore(cast<StoreSDNode>(N));
189 def si_store_local : PatFrag <
190 (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{
191 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
192 !cast<StoreSDNode>(N)->isTruncatingStore();
195 def si_store_local_align8 : Aligned8Bytes <
196 (ops node:$val, node:$ptr), (si_store_local node:$val, node:$ptr)
199 def si_truncstore_local : PatFrag <
200 (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{
201 return cast<StoreSDNode>(N)->isTruncatingStore();
204 def si_truncstore_local_i8 : PatFrag <
205 (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{
206 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
209 def si_truncstore_local_i16 : PatFrag <
210 (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{
211 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
214 multiclass SIAtomicM0Glue2 <string op_name> {
216 def _glue : SDNode <"ISD::ATOMIC_"#op_name, SDTAtomic2,
217 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
220 def _local : local_binary_atomic_op <!cast<SDNode>(NAME#"_glue")>;
223 defm si_atomic_load_add : SIAtomicM0Glue2 <"LOAD_ADD">;
224 defm si_atomic_load_and : SIAtomicM0Glue2 <"LOAD_AND">;
225 defm si_atomic_load_min : SIAtomicM0Glue2 <"LOAD_MIN">;
226 defm si_atomic_load_max : SIAtomicM0Glue2 <"LOAD_MAX">;
227 defm si_atomic_load_or : SIAtomicM0Glue2 <"LOAD_OR">;
228 defm si_atomic_load_sub : SIAtomicM0Glue2 <"LOAD_SUB">;
229 defm si_atomic_load_xor : SIAtomicM0Glue2 <"LOAD_XOR">;
230 defm si_atomic_load_umin : SIAtomicM0Glue2 <"LOAD_UMIN">;
231 defm si_atomic_load_umax : SIAtomicM0Glue2 <"LOAD_UMAX">;
232 defm si_atomic_swap : SIAtomicM0Glue2 <"SWAP">;
234 def si_atomic_cmp_swap_glue : SDNode <"ISD::ATOMIC_CMP_SWAP", SDTAtomic3,
235 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
238 defm si_atomic_cmp_swap : AtomicCmpSwapLocal <si_atomic_cmp_swap_glue>;
240 // Transformation function, extract the lower 32bit of a 64bit immediate
241 def LO32 : SDNodeXForm<imm, [{
242 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, SDLoc(N),
246 def LO32f : SDNodeXForm<fpimm, [{
247 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
248 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
251 // Transformation function, extract the upper 32bit of a 64bit immediate
252 def HI32 : SDNodeXForm<imm, [{
253 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, SDLoc(N), MVT::i32);
256 def HI32f : SDNodeXForm<fpimm, [{
257 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
258 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), SDLoc(N),
262 def IMM8bitDWORD : PatLeaf <(imm),
263 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
266 def as_dword_i32imm : SDNodeXForm<imm, [{
267 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, SDLoc(N), MVT::i32);
270 def as_i1imm : SDNodeXForm<imm, [{
271 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i1);
274 def as_i8imm : SDNodeXForm<imm, [{
275 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i8);
278 def as_i16imm : SDNodeXForm<imm, [{
279 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
282 def as_i32imm: SDNodeXForm<imm, [{
283 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
286 def as_i64imm: SDNodeXForm<imm, [{
287 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
290 // Copied from the AArch64 backend:
291 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
292 return CurDAG->getTargetConstant(
293 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
296 // Copied from the AArch64 backend:
297 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
298 return CurDAG->getTargetConstant(
299 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
302 def IMM8bit : PatLeaf <(imm),
303 [{return isUInt<8>(N->getZExtValue());}]
306 def IMM12bit : PatLeaf <(imm),
307 [{return isUInt<12>(N->getZExtValue());}]
310 def IMM16bit : PatLeaf <(imm),
311 [{return isUInt<16>(N->getZExtValue());}]
314 def IMM20bit : PatLeaf <(imm),
315 [{return isUInt<20>(N->getZExtValue());}]
318 def IMM32bit : PatLeaf <(imm),
319 [{return isUInt<32>(N->getZExtValue());}]
322 def mubuf_vaddr_offset : PatFrag<
323 (ops node:$ptr, node:$offset, node:$imm_offset),
324 (add (add node:$ptr, node:$offset), node:$imm_offset)
327 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
328 return isInlineImmediate(N);
331 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
332 return isInlineImmediate(N);
335 class SGPRImm <dag frag> : PatLeaf<frag, [{
336 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
339 const SIRegisterInfo *SIRI =
340 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
341 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
343 const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());
344 if (RC && SIRI->isSGPRClass(RC))
350 //===----------------------------------------------------------------------===//
352 //===----------------------------------------------------------------------===//
354 def FRAMEri32 : Operand<iPTR> {
355 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
358 def SoppBrTarget : AsmOperandClass {
359 let Name = "SoppBrTarget";
360 let ParserMethod = "parseSOppBrTarget";
363 def sopp_brtarget : Operand<OtherVT> {
364 let EncoderMethod = "getSOPPBrEncoding";
365 let OperandType = "OPERAND_PCREL";
366 let ParserMatchClass = SoppBrTarget;
369 include "SIInstrFormats.td"
370 include "VIInstrFormats.td"
372 def MubufOffsetMatchClass : AsmOperandClass {
373 let Name = "MubufOffset";
374 let ParserMethod = "parseMubufOptionalOps";
375 let RenderMethod = "addImmOperands";
378 class DSOffsetBaseMatchClass <string parser> : AsmOperandClass {
379 let Name = "DSOffset"#parser;
380 let ParserMethod = parser;
381 let RenderMethod = "addImmOperands";
382 let PredicateMethod = "isDSOffset";
385 def DSOffsetMatchClass : DSOffsetBaseMatchClass <"parseDSOptionalOps">;
386 def DSOffsetGDSMatchClass : DSOffsetBaseMatchClass <"parseDSOffsetOptional">;
388 def DSOffset01MatchClass : AsmOperandClass {
389 let Name = "DSOffset1";
390 let ParserMethod = "parseDSOff01OptionalOps";
391 let RenderMethod = "addImmOperands";
392 let PredicateMethod = "isDSOffset01";
395 class GDSBaseMatchClass <string parser> : AsmOperandClass {
396 let Name = "GDS"#parser;
397 let PredicateMethod = "isImm";
398 let ParserMethod = parser;
399 let RenderMethod = "addImmOperands";
402 def GDSMatchClass : GDSBaseMatchClass <"parseDSOptionalOps">;
403 def GDS01MatchClass : GDSBaseMatchClass <"parseDSOff01OptionalOps">;
405 class GLCBaseMatchClass <string parser> : AsmOperandClass {
406 let Name = "GLC"#parser;
407 let PredicateMethod = "isImm";
408 let ParserMethod = parser;
409 let RenderMethod = "addImmOperands";
412 def GLCMubufMatchClass : GLCBaseMatchClass <"parseMubufOptionalOps">;
413 def GLCFlatMatchClass : GLCBaseMatchClass <"parseFlatOptionalOps">;
415 class SLCBaseMatchClass <string parser> : AsmOperandClass {
416 let Name = "SLC"#parser;
417 let PredicateMethod = "isImm";
418 let ParserMethod = parser;
419 let RenderMethod = "addImmOperands";
422 def SLCMubufMatchClass : SLCBaseMatchClass <"parseMubufOptionalOps">;
423 def SLCFlatMatchClass : SLCBaseMatchClass <"parseFlatOptionalOps">;
424 def SLCFlatAtomicMatchClass : SLCBaseMatchClass <"parseFlatAtomicOptionalOps">;
426 class TFEBaseMatchClass <string parser> : AsmOperandClass {
427 let Name = "TFE"#parser;
428 let PredicateMethod = "isImm";
429 let ParserMethod = parser;
430 let RenderMethod = "addImmOperands";
433 def TFEMubufMatchClass : TFEBaseMatchClass <"parseMubufOptionalOps">;
434 def TFEFlatMatchClass : TFEBaseMatchClass <"parseFlatOptionalOps">;
435 def TFEFlatAtomicMatchClass : TFEBaseMatchClass <"parseFlatAtomicOptionalOps">;
437 def OModMatchClass : AsmOperandClass {
439 let PredicateMethod = "isImm";
440 let ParserMethod = "parseVOP3OptionalOps";
441 let RenderMethod = "addImmOperands";
444 def ClampMatchClass : AsmOperandClass {
446 let PredicateMethod = "isImm";
447 let ParserMethod = "parseVOP3OptionalOps";
448 let RenderMethod = "addImmOperands";
451 class SMRDOffsetBaseMatchClass <string predicate> : AsmOperandClass {
452 let Name = "SMRDOffset"#predicate;
453 let PredicateMethod = predicate;
454 let RenderMethod = "addImmOperands";
457 def SMRDOffsetMatchClass : SMRDOffsetBaseMatchClass <"isSMRDOffset">;
458 def SMRDLiteralOffsetMatchClass : SMRDOffsetBaseMatchClass <
459 "isSMRDLiteralOffset"
462 let OperandType = "OPERAND_IMMEDIATE" in {
464 def offen : Operand<i1> {
465 let PrintMethod = "printOffen";
467 def idxen : Operand<i1> {
468 let PrintMethod = "printIdxen";
470 def addr64 : Operand<i1> {
471 let PrintMethod = "printAddr64";
473 def mbuf_offset : Operand<i16> {
474 let PrintMethod = "printMBUFOffset";
475 let ParserMatchClass = MubufOffsetMatchClass;
477 class ds_offset_base <AsmOperandClass mc> : Operand<i16> {
478 let PrintMethod = "printDSOffset";
479 let ParserMatchClass = mc;
481 def ds_offset : ds_offset_base <DSOffsetMatchClass>;
482 def ds_offset_gds : ds_offset_base <DSOffsetGDSMatchClass>;
484 def ds_offset0 : Operand<i8> {
485 let PrintMethod = "printDSOffset0";
486 let ParserMatchClass = DSOffset01MatchClass;
488 def ds_offset1 : Operand<i8> {
489 let PrintMethod = "printDSOffset1";
490 let ParserMatchClass = DSOffset01MatchClass;
492 class gds_base <AsmOperandClass mc> : Operand <i1> {
493 let PrintMethod = "printGDS";
494 let ParserMatchClass = mc;
496 def gds : gds_base <GDSMatchClass>;
498 def gds01 : gds_base <GDS01MatchClass>;
500 class glc_base <AsmOperandClass mc> : Operand <i1> {
501 let PrintMethod = "printGLC";
502 let ParserMatchClass = mc;
505 def glc : glc_base <GLCMubufMatchClass>;
506 def glc_flat : glc_base <GLCFlatMatchClass>;
508 class slc_base <AsmOperandClass mc> : Operand <i1> {
509 let PrintMethod = "printSLC";
510 let ParserMatchClass = mc;
513 def slc : slc_base <SLCMubufMatchClass>;
514 def slc_flat : slc_base <SLCFlatMatchClass>;
515 def slc_flat_atomic : slc_base <SLCFlatAtomicMatchClass>;
517 class tfe_base <AsmOperandClass mc> : Operand <i1> {
518 let PrintMethod = "printTFE";
519 let ParserMatchClass = mc;
522 def tfe : tfe_base <TFEMubufMatchClass>;
523 def tfe_flat : tfe_base <TFEFlatMatchClass>;
524 def tfe_flat_atomic : tfe_base <TFEFlatAtomicMatchClass>;
526 def omod : Operand <i32> {
527 let PrintMethod = "printOModSI";
528 let ParserMatchClass = OModMatchClass;
531 def ClampMod : Operand <i1> {
532 let PrintMethod = "printClampSI";
533 let ParserMatchClass = ClampMatchClass;
536 def smrd_offset : Operand <i32> {
537 let PrintMethod = "printU32ImmOperand";
538 let ParserMatchClass = SMRDOffsetMatchClass;
541 def smrd_literal_offset : Operand <i32> {
542 let PrintMethod = "printU32ImmOperand";
543 let ParserMatchClass = SMRDLiteralOffsetMatchClass;
546 } // End OperandType = "OPERAND_IMMEDIATE"
548 def VOPDstS64 : VOPDstOperand <SReg_64>;
550 //===----------------------------------------------------------------------===//
552 //===----------------------------------------------------------------------===//
554 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
555 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
557 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
558 def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">;
559 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
560 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
561 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
562 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
564 def SMRDImm : ComplexPattern<i64, 2, "SelectSMRDImm">;
565 def SMRDImm32 : ComplexPattern<i64, 2, "SelectSMRDImm32">;
566 def SMRDSgpr : ComplexPattern<i64, 2, "SelectSMRDSgpr">;
567 def SMRDBufferImm : ComplexPattern<i32, 1, "SelectSMRDBufferImm">;
568 def SMRDBufferImm32 : ComplexPattern<i32, 1, "SelectSMRDBufferImm32">;
569 def SMRDBufferSgpr : ComplexPattern<i32, 1, "SelectSMRDBufferSgpr">;
571 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
572 def VOP3NoMods0 : ComplexPattern<untyped, 4, "SelectVOP3NoMods0">;
573 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
574 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
575 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
576 def VOP3NoMods : ComplexPattern<untyped, 2, "SelectVOP3NoMods">;
578 //===----------------------------------------------------------------------===//
579 // SI assembler operands
580 //===----------------------------------------------------------------------===//
601 //===----------------------------------------------------------------------===//
603 // SI Instruction multiclass helpers.
605 // Instructions with _32 take 32-bit operands.
606 // Instructions with _64 take 64-bit operands.
608 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
609 // encoding is the standard encoding, but instruction that make use of
610 // any of the instruction modifiers must use the 64-bit encoding.
612 // Instructions with _e32 use the 32-bit encoding.
613 // Instructions with _e64 use the 64-bit encoding.
615 //===----------------------------------------------------------------------===//
617 class SIMCInstr <string pseudo, int subtarget> {
618 string PseudoInstr = pseudo;
619 int Subtarget = subtarget;
622 //===----------------------------------------------------------------------===//
624 //===----------------------------------------------------------------------===//
626 class EXPCommon : InstSI<
628 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
629 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
630 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
639 let isPseudo = 1, isCodeGenOnly = 1 in {
640 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
643 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
645 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
648 //===----------------------------------------------------------------------===//
650 //===----------------------------------------------------------------------===//
652 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
653 SOP1 <outs, ins, "", pattern>,
654 SIMCInstr<opName, SISubtarget.NONE> {
656 let isCodeGenOnly = 1;
659 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
660 SOP1 <outs, ins, asm, []>,
662 SIMCInstr<opName, SISubtarget.SI> {
663 let isCodeGenOnly = 0;
664 let AssemblerPredicates = [isSICI];
667 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
668 SOP1 <outs, ins, asm, []>,
670 SIMCInstr<opName, SISubtarget.VI> {
671 let isCodeGenOnly = 0;
672 let AssemblerPredicates = [isVI];
675 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
678 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
680 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
682 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
686 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
687 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
688 opName#" $dst, $src0", pattern
691 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
692 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
693 opName#" $dst, $src0", pattern
696 // no input, 64-bit output.
697 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
698 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
700 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
705 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
711 // 64-bit input, no output
712 multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
713 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
715 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
720 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
726 // 64-bit input, 32-bit output.
727 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
728 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
729 opName#" $dst, $src0", pattern
732 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
733 SOP2<outs, ins, "", pattern>,
734 SIMCInstr<opName, SISubtarget.NONE> {
736 let isCodeGenOnly = 1;
739 // Pseudo instructions have no encodings, but adding this field here allows
741 // let sdst = xxx in {
742 // for multiclasses that include both real and pseudo instructions.
743 field bits<7> sdst = 0;
746 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
747 SOP2<outs, ins, asm, []>,
749 SIMCInstr<opName, SISubtarget.SI> {
750 let AssemblerPredicates = [isSICI];
753 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
754 SOP2<outs, ins, asm, []>,
756 SIMCInstr<opName, SISubtarget.VI> {
757 let AssemblerPredicates = [isVI];
760 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
763 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
765 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
767 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
771 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
772 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
773 opName#" $dst, $src0, $src1", pattern
776 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
777 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
778 opName#" $dst, $src0, $src1", pattern
781 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
782 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
783 opName#" $dst, $src0, $src1", pattern
786 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
787 string opName, PatLeaf cond> : SOPC <
788 op, (outs), (ins rc:$src0, rc:$src1),
789 opName#" $src0, $src1", []> {
793 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
794 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
796 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
797 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
799 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
800 SOPK <outs, ins, "", pattern>,
801 SIMCInstr<opName, SISubtarget.NONE> {
803 let isCodeGenOnly = 1;
806 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
807 SOPK <outs, ins, asm, []>,
809 SIMCInstr<opName, SISubtarget.SI> {
810 let AssemblerPredicates = [isSICI];
811 let isCodeGenOnly = 0;
814 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
815 SOPK <outs, ins, asm, []>,
817 SIMCInstr<opName, SISubtarget.VI> {
818 let AssemblerPredicates = [isVI];
819 let isCodeGenOnly = 0;
822 multiclass SOPK_m <sopk op, string opName, dag outs, dag ins, string opAsm,
823 string asm = opName#opAsm> {
824 def "" : SOPK_Pseudo <opName, outs, ins, []>;
826 def _si : SOPK_Real_si <op, opName, outs, ins, asm>;
828 def _vi : SOPK_Real_vi <op, opName, outs, ins, asm>;
832 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
833 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
836 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
837 opName#" $dst, $src0">;
839 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
840 opName#" $dst, $src0">;
843 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
844 def "" : SOPK_Pseudo <opName, (outs),
845 (ins SReg_32:$src0, u16imm:$src1), pattern> {
850 def _si : SOPK_Real_si <op, opName, (outs),
851 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16"> {
855 def _vi : SOPK_Real_vi <op, opName, (outs),
856 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16"> {
861 multiclass SOPK_32TIE <sopk op, string opName, list<dag> pattern> : SOPK_m <
862 op, opName, (outs SReg_32:$sdst), (ins SReg_32:$src0, u16imm:$simm16),
866 multiclass SOPK_IMM32 <sopk op, string opName, dag outs, dag ins,
867 string argAsm, string asm = opName#argAsm> {
869 def "" : SOPK_Pseudo <opName, outs, ins, []>;
871 def _si : SOPK <outs, ins, asm, []>,
873 SIMCInstr<opName, SISubtarget.SI> {
874 let AssemblerPredicates = [isSICI];
875 let isCodeGenOnly = 0;
878 def _vi : SOPK <outs, ins, asm, []>,
880 SIMCInstr<opName, SISubtarget.VI> {
881 let AssemblerPredicates = [isVI];
882 let isCodeGenOnly = 0;
885 //===----------------------------------------------------------------------===//
887 //===----------------------------------------------------------------------===//
889 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
890 SMRD <outs, ins, "", pattern>,
891 SIMCInstr<opName, SISubtarget.NONE> {
893 let isCodeGenOnly = 1;
896 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
898 SMRD <outs, ins, asm, []>,
900 SIMCInstr<opName, SISubtarget.SI> {
901 let AssemblerPredicates = [isSICI];
904 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
905 string asm, list<dag> pattern = []> :
906 SMRD <outs, ins, asm, pattern>,
908 SIMCInstr<opName, SISubtarget.VI> {
909 let AssemblerPredicates = [isVI];
912 multiclass SMRD_m <smrd op, string opName, bit imm, dag outs, dag ins,
913 string asm, list<dag> pattern> {
915 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
917 def _si : SMRD_Real_si <op.SI, opName, imm, outs, ins, asm>;
919 // glc is only applicable to scalar stores, which are not yet
922 def _vi : SMRD_Real_vi <op.VI, opName, imm, outs, ins, asm>;
926 multiclass SMRD_Inval <smrd op, string opName,
927 SDPatternOperator node> {
928 let hasSideEffects = 1, mayStore = 1 in {
929 def "" : SMRD_Pseudo <opName, (outs), (ins), [(node)]>;
931 let sbase = 0, offset = 0 in {
933 def _si : SMRD_Real_si <op.SI, opName, 0, (outs), (ins), opName>;
936 let glc = 0, sdata = 0 in {
937 def _vi : SMRD_Real_vi <op.VI, opName, 0, (outs), (ins), opName>;
943 class SMEM_Inval <bits<8> op, string opName, SDPatternOperator node> :
944 SMRD_Real_vi<op, opName, 0, (outs), (ins), opName, [(node)]> {
945 let hasSideEffects = 1;
953 multiclass SMRD_Helper <smrd op, string opName, RegisterClass baseClass,
954 RegisterClass dstClass> {
956 op, opName#"_IMM", 1, (outs dstClass:$dst),
957 (ins baseClass:$sbase, smrd_offset:$offset),
958 opName#" $dst, $sbase, $offset", []
962 (outs dstClass:$dst), (ins baseClass:$sbase, smrd_literal_offset:$offset),
963 opName#" $dst, $sbase, $offset", []>, SMRD_IMMe_ci <op.SI> {
964 let AssemblerPredicates = [isCIOnly];
967 defm _SGPR : SMRD_m <
968 op, opName#"_SGPR", 0, (outs dstClass:$dst),
969 (ins baseClass:$sbase, SReg_32:$soff),
970 opName#" $dst, $sbase, $soff", []
974 //===----------------------------------------------------------------------===//
975 // Vector ALU classes
976 //===----------------------------------------------------------------------===//
978 // This must always be right before the operand being input modified.
979 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
980 let PrintMethod = "printOperandAndMods";
983 def InputModsMatchClass : AsmOperandClass {
984 let Name = "RegWithInputMods";
987 def InputModsNoDefault : Operand <i32> {
988 let PrintMethod = "printOperandAndMods";
989 let ParserMatchClass = InputModsMatchClass;
992 class getNumSrcArgs<ValueType Src0, ValueType Src1, ValueType Src2> {
994 !if (!eq(Src0.Value, untyped.Value), 0,
995 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
996 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
1000 // Returns the register class to use for the destination of VOP[123C]
1001 // instructions for the given VT.
1002 class getVALUDstForVT<ValueType VT> {
1003 RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
1004 !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
1005 !if(!eq(VT.Size, 16), VOPDstOperand<VGPR_32>,
1006 VOPDstOperand<SReg_64>))); // else VT == i1
1009 // Returns the register class to use for source 0 of VOP[12C]
1010 // instructions for the given VT.
1011 class getVOPSrc0ForVT<ValueType VT> {
1012 RegisterOperand ret = !if(!eq(VT.Size, 64), VSrc_64, VSrc_32);
1015 // Returns the register class to use for source 1 of VOP[12C] for the
1017 class getVOPSrc1ForVT<ValueType VT> {
1018 RegisterClass ret = !if(!eq(VT.Size, 64), VReg_64, VGPR_32);
1021 // Returns the register class to use for sources of VOP3 instructions for the
1023 class getVOP3SrcForVT<ValueType VT> {
1024 RegisterOperand ret =
1025 !if(!eq(VT.Size, 64),
1027 !if(!eq(VT.Value, i1.Value),
1034 // Returns 1 if the source arguments have modifiers, 0 if they do not.
1035 // XXX - do f16 instructions?
1036 class hasModifiers<ValueType SrcVT> {
1037 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
1038 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
1041 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
1042 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
1043 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
1044 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1048 // Returns the input arguments for VOP3 instructions for the given SrcVT.
1049 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
1050 RegisterOperand Src2RC, int NumSrcArgs,
1054 !if (!eq(NumSrcArgs, 1),
1055 !if (!eq(HasModifiers, 1),
1056 // VOP1 with modifiers
1057 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
1058 ClampMod:$clamp, omod:$omod)
1060 // VOP1 without modifiers
1063 !if (!eq(NumSrcArgs, 2),
1064 !if (!eq(HasModifiers, 1),
1065 // VOP 2 with modifiers
1066 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
1067 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
1068 ClampMod:$clamp, omod:$omod)
1070 // VOP2 without modifiers
1071 (ins Src0RC:$src0, Src1RC:$src1)
1073 /* NumSrcArgs == 3 */,
1074 !if (!eq(HasModifiers, 1),
1075 // VOP3 with modifiers
1076 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
1077 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
1078 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
1079 ClampMod:$clamp, omod:$omod)
1081 // VOP3 without modifiers
1082 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
1086 // Returns the assembly string for the inputs and outputs of a VOP[12C]
1087 // instruction. This does not add the _e32 suffix, so it can be reused
1089 class getAsm32 <bit HasDst, int NumSrcArgs> {
1090 string dst = "$dst";
1091 string src0 = ", $src0";
1092 string src1 = ", $src1";
1093 string src2 = ", $src2";
1094 string ret = !if(HasDst, dst, "") #
1095 !if(!eq(NumSrcArgs, 1), src0, "") #
1096 !if(!eq(NumSrcArgs, 2), src0#src1, "") #
1097 !if(!eq(NumSrcArgs, 3), src0#src1#src2, "");
1100 // Returns the assembly string for the inputs and outputs of a VOP3
1102 class getAsm64 <bit HasDst, int NumSrcArgs, bit HasModifiers> {
1103 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
1104 string src1 = !if(!eq(NumSrcArgs, 1), "",
1105 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
1106 " $src1_modifiers,"));
1107 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
1109 !if(!eq(HasModifiers, 0),
1110 getAsm32<HasDst, NumSrcArgs>.ret,
1111 "$dst, "#src0#src1#src2#"$clamp"#"$omod");
1114 class VOPProfile <list<ValueType> _ArgVT> {
1116 field list<ValueType> ArgVT = _ArgVT;
1118 field ValueType DstVT = ArgVT[0];
1119 field ValueType Src0VT = ArgVT[1];
1120 field ValueType Src1VT = ArgVT[2];
1121 field ValueType Src2VT = ArgVT[3];
1122 field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
1123 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
1124 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
1125 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
1126 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
1127 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
1129 field bit HasDst = !if(!eq(DstVT.Value, untyped.Value), 0, 1);
1130 field bit HasDst32 = HasDst;
1131 field int NumSrcArgs = getNumSrcArgs<Src0VT, Src1VT, Src2VT>.ret;
1132 field bit HasModifiers = hasModifiers<Src0VT>.ret;
1134 field dag Outs = !if(HasDst,(outs DstRC:$dst),(outs));
1136 // VOP3b instructions are a special case with a second explicit
1137 // output. This is manually overridden for them.
1138 field dag Outs32 = Outs;
1139 field dag Outs64 = Outs;
1141 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
1142 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
1145 field string Asm32 = getAsm32<HasDst, NumSrcArgs>.ret;
1146 field string Asm64 = getAsm64<HasDst, NumSrcArgs, HasModifiers>.ret;
1149 // FIXME: I think these F16/I16 profiles will need to use f16/i16 types in order
1150 // for the instruction patterns to work.
1151 def VOP_F16_F16 : VOPProfile <[f16, f16, untyped, untyped]>;
1152 def VOP_F16_I16 : VOPProfile <[f16, i32, untyped, untyped]>;
1153 def VOP_I16_F16 : VOPProfile <[i32, f16, untyped, untyped]>;
1155 def VOP_F16_F16_F16 : VOPProfile <[f16, f16, f16, untyped]>;
1156 def VOP_F16_F16_I16 : VOPProfile <[f16, f16, i32, untyped]>;
1157 def VOP_I16_I16_I16 : VOPProfile <[i32, i32, i32, untyped]>;
1159 def VOP_NONE : VOPProfile <[untyped, untyped, untyped, untyped]>;
1161 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
1162 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
1163 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
1164 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
1165 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
1166 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
1167 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
1168 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
1169 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
1171 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
1172 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
1173 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
1174 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
1175 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
1176 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
1177 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
1179 // Write out to vcc or arbitrary SGPR.
1180 def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped]> {
1181 let Asm32 = "$dst, vcc, $src0, $src1";
1182 let Asm64 = "$dst, $sdst, $src0, $src1";
1183 let Outs32 = (outs DstRC:$dst);
1184 let Outs64 = (outs DstRC:$dst, SReg_64:$sdst);
1187 // Write out to vcc or arbitrary SGPR and read in from vcc or
1189 def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1]> {
1190 // We use VCSrc_32 to exclude literal constants, even though the
1191 // encoding normally allows them since the implicit VCC use means
1192 // using one would always violate the constant bus
1193 // restriction. SGPRs are still allowed because it should
1194 // technically be possible to use VCC again as src0.
1195 let Src0RC32 = VCSrc_32;
1196 let Asm32 = "$dst, vcc, $src0, $src1, vcc";
1197 let Asm64 = "$dst, $sdst, $src0, $src1, $src2";
1198 let Outs32 = (outs DstRC:$dst);
1199 let Outs64 = (outs DstRC:$dst, SReg_64:$sdst);
1201 // Suppress src2 implied by type since the 32-bit encoding uses an
1202 // implicit VCC use.
1203 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
1206 class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> {
1207 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
1208 let Asm64 = "$vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod";
1211 def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile<f32> {
1212 // FIXME: Hack to stop printing _e64
1213 let DstRC = RegisterOperand<VGPR_32>;
1216 def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64> {
1217 // FIXME: Hack to stop printing _e64
1218 let DstRC = RegisterOperand<VReg_64>;
1221 // VOPC instructions are a special case because for the 32-bit
1222 // encoding, we want to display the implicit vcc write as if it were
1223 // an explicit $dst.
1224 class VOPC_Profile<ValueType vt0, ValueType vt1 = vt0> : VOPProfile <[i1, vt0, vt1, untyped]> {
1225 let Asm32 = "vcc, $src0, $src1";
1226 // The destination for 32-bit encoding is implicit.
1230 class VOPC_Class_Profile<ValueType vt> : VOPC_Profile<vt, i32> {
1231 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
1232 let Asm64 = "$dst, $src0_modifiers, $src1";
1235 def VOPC_I1_F32_F32 : VOPC_Profile<f32>;
1236 def VOPC_I1_F64_F64 : VOPC_Profile<f64>;
1237 def VOPC_I1_I32_I32 : VOPC_Profile<i32>;
1238 def VOPC_I1_I64_I64 : VOPC_Profile<i64>;
1240 def VOPC_I1_F32_I32 : VOPC_Class_Profile<f32>;
1241 def VOPC_I1_F64_I32 : VOPC_Class_Profile<f64>;
1243 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
1244 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
1245 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
1246 def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> {
1247 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
1248 let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
1249 let Asm64 = "$dst, $src0, $src1, $src2";
1252 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
1253 def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {
1254 field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
1255 field string Asm = "$dst, $src0, $vsrc1, $src2";
1257 def VOP_MAC : VOPProfile <[f32, f32, f32, f32]> {
1258 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);
1259 let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3,
1261 let Asm32 = getAsm32<1, 2>.ret;
1262 let Asm64 = getAsm64<1, 2, HasModifiers>.ret;
1264 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
1265 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
1266 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
1268 class SIInstAlias <string asm, Instruction inst, VOPProfile p> :
1269 InstAlias <asm, (inst)>, PredicateControl {
1271 field bit isCompare;
1272 field bit isCommutable;
1276 !if (!eq(p.NumSrcArgs, 0),
1278 (inst p.DstRC:$dst),
1279 !if (!eq(p.NumSrcArgs, 1),
1281 (inst p.DstRC:$dst, p.Src0RC32:$src0),
1282 !if (!eq(p.NumSrcArgs, 2),
1284 (inst p.DstRC:$dst, p.Src0RC32:$src0, p.Src1RC32:$src1),
1285 // else - unreachable
1288 !if (!eq(p.NumSrcArgs, 2),
1290 (inst p.Src0RC32:$src0, p.Src1RC32:$src1),
1291 !if (!eq(p.NumSrcArgs, 1),
1293 (inst p.Src0RC32:$src1),
1299 class SIInstAliasSI <string asm, string op_name, VOPProfile p> :
1300 SIInstAlias <asm, !cast<Instruction>(op_name#"_e32_si"), p> {
1301 let AssemblerPredicate = SIAssemblerPredicate;
1304 class SIInstAliasVI <string asm, string op_name, VOPProfile p> :
1305 SIInstAlias <asm, !cast<Instruction>(op_name#"_e32_vi"), p> {
1306 let AssemblerPredicates = [isVI];
1309 multiclass SIInstAliasBuilder <string asm, VOPProfile p> {
1311 def : SIInstAliasSI <asm, NAME, p>;
1313 def : SIInstAliasVI <asm, NAME, p>;
1316 class VOP <string opName> {
1317 string OpName = opName;
1320 class VOP2_REV <string revOp, bit isOrig> {
1321 string RevOp = revOp;
1322 bit IsOrig = isOrig;
1325 class AtomicNoRet <string noRetOp, bit isRet> {
1326 string NoRetOp = noRetOp;
1330 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1331 VOP1Common <outs, ins, "", pattern>,
1333 SIMCInstr <opName#"_e32", SISubtarget.NONE>,
1334 MnemonicAlias<opName#"_e32", opName> {
1336 let isCodeGenOnly = 1;
1342 class VOP1_Real_si <string opName, vop1 op, dag outs, dag ins, string asm> :
1343 VOP1<op.SI, outs, ins, asm, []>,
1344 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1345 let AssemblerPredicate = SIAssemblerPredicate;
1348 class VOP1_Real_vi <string opName, vop1 op, dag outs, dag ins, string asm> :
1349 VOP1<op.VI, outs, ins, asm, []>,
1350 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1351 let AssemblerPredicates = [isVI];
1354 multiclass VOP1_m <vop1 op, string opName, VOPProfile p, list<dag> pattern,
1355 string asm = opName#p.Asm32> {
1356 def "" : VOP1_Pseudo <p.Outs, p.Ins32, pattern, opName>;
1358 def _si : VOP1_Real_si <opName, op, p.Outs, p.Ins32, asm>;
1360 def _vi : VOP1_Real_vi <opName, op, p.Outs, p.Ins32, asm>;
1364 multiclass VOP1SI_m <vop1 op, string opName, VOPProfile p, list<dag> pattern,
1365 string asm = opName#p.Asm32> {
1367 def "" : VOP1_Pseudo <p.Outs, p.Ins32, pattern, opName>;
1369 def _si : VOP1_Real_si <opName, op, p.Outs, p.Ins32, asm>;
1372 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1373 VOP2Common <outs, ins, "", pattern>,
1375 SIMCInstr<opName#"_e32", SISubtarget.NONE>,
1376 MnemonicAlias<opName#"_e32", opName> {
1378 let isCodeGenOnly = 1;
1381 class VOP2_Real_si <string opName, vop2 op, dag outs, dag ins, string asm> :
1382 VOP2 <op.SI, outs, ins, opName#asm, []>,
1383 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1384 let AssemblerPredicates = [isSICI];
1387 class VOP2_Real_vi <string opName, vop2 op, dag outs, dag ins, string asm> :
1388 VOP2 <op.VI, outs, ins, opName#asm, []>,
1389 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1390 let AssemblerPredicates = [isVI];
1393 multiclass VOP2SI_m <vop2 op, string opName, VOPProfile p, list<dag> pattern,
1396 def "" : VOP2_Pseudo <p.Outs32, p.Ins32, pattern, opName>,
1397 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
1399 def _si : VOP2_Real_si <opName, op, p.Outs32, p.Ins32, p.Asm32>;
1402 multiclass VOP2_m <vop2 op, string opName, VOPProfile p, list <dag> pattern,
1405 def "" : VOP2_Pseudo <p.Outs32, p.Ins32, pattern, opName>,
1406 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
1408 def _si : VOP2_Real_si <opName, op, p.Outs32, p.Ins32, p.Asm32>;
1410 def _vi : VOP2_Real_vi <opName, op, p.Outs32, p.Ins32, p.Asm32>;
1414 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
1416 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
1417 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
1418 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0);
1419 bits<2> omod = !if(HasModifiers, ?, 0);
1420 bits<1> clamp = !if(HasModifiers, ?, 0);
1421 bits<9> src1 = !if(HasSrc1, ?, 0);
1422 bits<9> src2 = !if(HasSrc2, ?, 0);
1425 class VOP3DisableModFields <bit HasSrc0Mods,
1426 bit HasSrc1Mods = 0,
1427 bit HasSrc2Mods = 0,
1428 bit HasOutputMods = 0> {
1429 bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0);
1430 bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0);
1431 bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0);
1432 bits<2> omod = !if(HasOutputMods, ?, 0);
1433 bits<1> clamp = !if(HasOutputMods, ?, 0);
1436 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1437 VOP3Common <outs, ins, "", pattern>,
1439 SIMCInstr<opName#"_e64", SISubtarget.NONE>,
1440 MnemonicAlias<opName#"_e64", opName> {
1442 let isCodeGenOnly = 1;
1448 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1449 VOP3Common <outs, ins, asm, []>,
1451 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1452 let AssemblerPredicates = [isSICI];
1455 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1456 VOP3Common <outs, ins, asm, []>,
1458 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1459 let AssemblerPredicates = [isVI];
1462 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1463 VOP3Common <outs, ins, asm, []>,
1465 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1466 let AssemblerPredicates = [isSICI];
1469 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1470 VOP3Common <outs, ins, asm, []>,
1472 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1473 let AssemblerPredicates = [isVI];
1476 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
1477 string opName, int NumSrcArgs, bit HasMods = 1> {
1479 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1481 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1482 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1483 !if(!eq(NumSrcArgs, 2), 0, 1),
1485 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1486 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1487 !if(!eq(NumSrcArgs, 2), 0, 1),
1491 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
1492 list<dag> pattern, string opName, bit HasMods = 1> {
1494 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1496 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1497 VOP3DisableFields<0, 0, HasMods>;
1499 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1500 VOP3DisableFields<0, 0, HasMods>;
1503 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
1504 list<dag> pattern, string opName, bit HasMods = 1> {
1506 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1508 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1509 VOP3DisableFields<0, 0, HasMods>;
1510 // No VI instruction. This class is for SI only.
1513 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
1514 list<dag> pattern, string opName, string revOp,
1517 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1518 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1520 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1521 VOP3DisableFields<1, 0, HasMods>;
1523 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1524 VOP3DisableFields<1, 0, HasMods>;
1527 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
1528 list<dag> pattern, string opName, string revOp,
1531 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1532 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1534 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1535 VOP3DisableFields<1, 0, HasMods>;
1537 // No VI instruction. This class is for SI only.
1540 // Two operand VOP3b instruction that may have a 3rd SGPR bool operand
1541 // instead of an implicit VCC as in the VOP2b format.
1542 multiclass VOP3b_2_3_m <vop op, dag outs, dag ins, string asm,
1543 list<dag> pattern, string opName, string revOp,
1544 bit HasMods = 1, bit useSrc2Input = 0> {
1545 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1547 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1548 VOP3DisableFields<1, useSrc2Input, HasMods>;
1550 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1551 VOP3DisableFields<1, useSrc2Input, HasMods>;
1554 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1555 list<dag> pattern, string opName,
1556 bit HasMods, bit defExec,
1557 string revOp, list<SchedReadWrite> sched> {
1559 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1560 VOP2_REV<revOp#"_e64", !eq(revOp, opName)> {
1561 let Defs = !if(defExec, [EXEC], []);
1562 let SchedRW = sched;
1565 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1566 VOP3DisableFields<1, 0, HasMods> {
1567 let Defs = !if(defExec, [EXEC], []);
1568 let SchedRW = sched;
1571 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1572 VOP3DisableFields<1, 0, HasMods> {
1573 let Defs = !if(defExec, [EXEC], []);
1574 let SchedRW = sched;
1578 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1579 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1580 string asm, list<dag> pattern = []> {
1581 let isPseudo = 1, isCodeGenOnly = 1 in {
1582 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1583 SIMCInstr<opName, SISubtarget.NONE>;
1586 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1587 SIMCInstr <opName, SISubtarget.SI> {
1588 let AssemblerPredicates = [isSICI];
1591 def _vi : VOP3Common <outs, ins, asm, []>,
1593 VOP3DisableFields <1, 0, 0>,
1594 SIMCInstr <opName, SISubtarget.VI> {
1595 let AssemblerPredicates = [isVI];
1599 multiclass VOP1_Helper <vop1 op, string opName, VOPProfile p, list<dag> pat32,
1602 defm _e32 : VOP1_m <op, opName, p, pat32>;
1604 defm _e64 : VOP3_1_m <op, p.Outs, p.Ins64, opName#p.Asm64, pat64, opName,
1608 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1609 SDPatternOperator node = null_frag> : VOP1_Helper <
1612 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1613 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1614 [(set P.DstVT:$dst, (node P.Src0VT:$src0))])
1617 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1618 SDPatternOperator node = null_frag> {
1620 defm _e32 : VOP1SI_m <op, opName, P, []>;
1622 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1624 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1625 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1626 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1627 opName, P.HasModifiers>;
1630 multiclass VOP2_Helper <vop2 op, string opName, VOPProfile p, list<dag> pat32,
1631 list<dag> pat64, string revOp> {
1633 defm _e32 : VOP2_m <op, opName, p, pat32, revOp>;
1635 defm _e64 : VOP3_2_m <op, p.Outs, p.Ins64, opName#p.Asm64, pat64, opName,
1636 revOp, p.HasModifiers>;
1639 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1640 SDPatternOperator node = null_frag,
1641 string revOp = opName> : VOP2_Helper <
1645 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1646 i1:$clamp, i32:$omod)),
1647 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1648 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1652 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1653 SDPatternOperator node = null_frag,
1654 string revOp = opName> {
1656 defm _e32 : VOP2SI_m <op, opName, P, [], revOp>;
1658 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1661 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1662 i1:$clamp, i32:$omod)),
1663 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1664 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1665 opName, revOp, P.HasModifiers>;
1668 multiclass VOP2b_Helper <vop2 op, string opName, VOPProfile p,
1669 list<dag> pat32, list<dag> pat64,
1670 string revOp, bit useSGPRInput> {
1672 let SchedRW = [Write32Bit, WriteSALU] in {
1673 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in {
1674 defm _e32 : VOP2_m <op, opName, p, pat32, revOp>;
1677 defm _e64 : VOP3b_2_3_m <op, p.Outs64, p.Ins64, opName#p.Asm64, pat64,
1678 opName, revOp, p.HasModifiers, useSGPRInput>;
1682 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1683 SDPatternOperator node = null_frag,
1684 string revOp = opName> : VOP2b_Helper <
1688 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1689 i1:$clamp, i32:$omod)),
1690 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1691 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1692 revOp, !eq(P.NumSrcArgs, 3)
1695 // A VOP2 instruction that is VOP3-only on VI.
1696 multiclass VOP2_VI3_Helper <vop23 op, string opName, VOPProfile p,
1697 list<dag> pat32, list<dag> pat64, string revOp> {
1699 defm _e32 : VOP2SI_m <op, opName, p, pat32, revOp>;
1701 defm _e64 : VOP3_2_m <op, p.Outs, p.Ins64, opName#p.Asm64, pat64, opName,
1702 revOp, p.HasModifiers>;
1705 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1706 SDPatternOperator node = null_frag,
1707 string revOp = opName>
1712 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1713 i1:$clamp, i32:$omod)),
1714 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1715 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1719 multiclass VOP2MADK <vop2 op, string opName, list<dag> pattern = []> {
1721 def "" : VOP2_Pseudo <VOP_MADK.Outs, VOP_MADK.Ins, pattern, opName>;
1723 let isCodeGenOnly = 0 in {
1724 def _si : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1725 !strconcat(opName, VOP_MADK.Asm), []>,
1726 SIMCInstr <opName#"_e32", SISubtarget.SI>,
1727 VOP2_MADKe <op.SI> {
1728 let AssemblerPredicates = [isSICI];
1731 def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1732 !strconcat(opName, VOP_MADK.Asm), []>,
1733 SIMCInstr <opName#"_e32", SISubtarget.VI>,
1734 VOP2_MADKe <op.VI> {
1735 let AssemblerPredicates = [isVI];
1737 } // End isCodeGenOnly = 0
1740 class VOPC_Pseudo <dag ins, list<dag> pattern, string opName> :
1741 VOPCCommon <ins, "", pattern>,
1743 SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1745 let isCodeGenOnly = 1;
1748 multiclass VOPC_m <vopc op, dag ins, string op_asm, list<dag> pattern,
1749 string opName, bit DefExec, VOPProfile p,
1750 list<SchedReadWrite> sched,
1751 string revOpName = "", string asm = opName#"_e32 "#op_asm,
1752 string alias_asm = opName#" "#op_asm> {
1753 def "" : VOPC_Pseudo <ins, pattern, opName> {
1754 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
1755 let SchedRW = sched;
1758 let AssemblerPredicates = [isSICI] in {
1759 def _si : VOPC<op.SI, ins, asm, []>,
1760 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1761 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
1762 let hasSideEffects = DefExec;
1763 let SchedRW = sched;
1766 } // End AssemblerPredicates = [isSICI]
1768 let AssemblerPredicates = [isVI] in {
1769 def _vi : VOPC<op.VI, ins, asm, []>,
1770 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1771 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
1772 let hasSideEffects = DefExec;
1773 let SchedRW = sched;
1776 } // End AssemblerPredicates = [isVI]
1778 defm : SIInstAliasBuilder<alias_asm, p>;
1781 multiclass VOPC_Helper <vopc op, string opName, list<dag> pat32,
1782 list<dag> pat64, bit DefExec, string revOp,
1783 VOPProfile p, list<SchedReadWrite> sched> {
1784 defm _e32 : VOPC_m <op, p.Ins32, p.Asm32, pat32, opName, DefExec, p, sched>;
1786 defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$dst), p.Ins64, opName#p.Asm64, pat64,
1787 opName, p.HasModifiers, DefExec, revOp, sched>;
1790 // Special case for class instructions which only have modifiers on
1791 // the 1st source operand.
1792 multiclass VOPC_Class_Helper <vopc op, string opName, list<dag> pat32,
1793 list<dag> pat64, bit DefExec, string revOp,
1794 VOPProfile p, list<SchedReadWrite> sched> {
1795 defm _e32 : VOPC_m <op, p.Ins32, p.Asm32, pat32, opName, DefExec, p, sched>;
1797 defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$dst), p.Ins64, opName#p.Asm64, pat64,
1798 opName, p.HasModifiers, DefExec, revOp, sched>,
1799 VOP3DisableModFields<1, 0, 0>;
1802 multiclass VOPCInst <vopc op, string opName,
1803 VOPProfile P, PatLeaf cond = COND_NULL,
1804 string revOp = opName,
1806 list<SchedReadWrite> sched = [Write32Bit]> :
1811 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1812 i1:$clamp, i32:$omod)),
1813 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1815 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1816 DefExec, revOp, P, sched
1819 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1821 list<SchedReadWrite> sched> : VOPC_Class_Helper <
1825 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1826 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1827 DefExec, opName, P, sched
1831 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1832 VOPCInst <op, opName, VOPC_I1_F32_F32, cond, revOp>;
1834 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1835 VOPCInst <op, opName, VOPC_I1_F64_F64, cond, revOp, 0, [WriteDoubleAdd]>;
1837 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1838 VOPCInst <op, opName, VOPC_I1_I32_I32, cond, revOp>;
1840 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1841 VOPCInst <op, opName, VOPC_I1_I64_I64, cond, revOp, 0, [Write64Bit]>;
1844 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1845 PatLeaf cond = COND_NULL,
1846 list<SchedReadWrite> sched,
1848 : VOPCInst <op, opName, P, cond, revOp, 1, sched>;
1850 multiclass VOPCX_F32 <vopc op, string opName, string revOp = opName> :
1851 VOPCX <op, opName, VOPC_I1_F32_F32, COND_NULL, [Write32Bit], revOp>;
1853 multiclass VOPCX_F64 <vopc op, string opName, string revOp = opName> :
1854 VOPCX <op, opName, VOPC_I1_F64_F64, COND_NULL, [WriteDoubleAdd], revOp>;
1856 multiclass VOPCX_I32 <vopc op, string opName, string revOp = opName> :
1857 VOPCX <op, opName, VOPC_I1_I32_I32, COND_NULL, [Write32Bit], revOp>;
1859 multiclass VOPCX_I64 <vopc op, string opName, string revOp = opName> :
1860 VOPCX <op, opName, VOPC_I1_I64_I64, COND_NULL, [Write64Bit], revOp>;
1862 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1863 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1864 op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods
1867 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1868 VOPCClassInst <op, opName, VOPC_I1_F32_I32, 0, [Write32Bit]>;
1870 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1871 VOPCClassInst <op, opName, VOPC_I1_F32_I32, 1, [Write32Bit]>;
1873 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1874 VOPCClassInst <op, opName, VOPC_I1_F64_I32, 0, [WriteDoubleAdd]>;
1876 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1877 VOPCClassInst <op, opName, VOPC_I1_F64_I32, 1, [WriteDoubleAdd]>;
1879 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1880 SDPatternOperator node = null_frag> : VOP3_Helper <
1881 op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64,
1882 !if(!eq(P.NumSrcArgs, 3),
1885 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1886 i1:$clamp, i32:$omod)),
1887 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1888 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1889 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1891 !if(!eq(P.NumSrcArgs, 2),
1894 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1895 i1:$clamp, i32:$omod)),
1896 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1897 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1898 /* P.NumSrcArgs == 1 */,
1901 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1902 i1:$clamp, i32:$omod))))],
1903 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1904 P.NumSrcArgs, P.HasModifiers
1907 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1908 // only VOP instruction that implicitly reads VCC.
1909 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1911 SDPatternOperator node = null_frag> : VOP3_Helper <
1913 (outs P.DstRC.RegClass:$dst),
1914 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1915 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1916 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1919 "$dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1921 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1922 i1:$clamp, i32:$omod)),
1923 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1924 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1929 multiclass VOP3bInst <vop op, string opName, VOPProfile P, list<dag> pattern = []> :
1931 op, P.Outs64, P.Ins64,
1932 opName#" "#P.Asm64, pattern,
1936 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1937 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1938 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1939 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1940 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1941 i32:$src1_modifiers, P.Src1VT:$src1,
1942 i32:$src2_modifiers, P.Src2VT:$src2,
1946 //===----------------------------------------------------------------------===//
1947 // Interpolation opcodes
1948 //===----------------------------------------------------------------------===//
1950 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1951 VINTRPCommon <outs, ins, "", pattern>,
1952 SIMCInstr<opName, SISubtarget.NONE> {
1954 let isCodeGenOnly = 1;
1957 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1959 VINTRPCommon <outs, ins, asm, []>,
1961 SIMCInstr<opName, SISubtarget.SI>;
1963 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1965 VINTRPCommon <outs, ins, asm, []>,
1967 SIMCInstr<opName, SISubtarget.VI>;
1969 multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
1970 list<dag> pattern = []> {
1971 def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
1973 def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>;
1975 def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
1978 //===----------------------------------------------------------------------===//
1979 // Vector I/O classes
1980 //===----------------------------------------------------------------------===//
1982 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1983 DS <outs, ins, "", pattern>,
1984 SIMCInstr <opName, SISubtarget.NONE> {
1986 let isCodeGenOnly = 1;
1989 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1990 DS <outs, ins, asm, []>,
1992 SIMCInstr <opName, SISubtarget.SI> {
1993 let isCodeGenOnly = 0;
1996 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1997 DS <outs, ins, asm, []>,
1999 SIMCInstr <opName, SISubtarget.VI>;
2001 class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
2002 DS_Real_si <op,opName, outs, ins, asm> {
2004 // Single load interpret the 2 i8imm operands as a single i16 offset.
2006 let offset0 = offset{7-0};
2007 let offset1 = offset{15-8};
2008 let isCodeGenOnly = 0;
2011 class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
2012 DS_Real_vi <op, opName, outs, ins, asm> {
2014 // Single load interpret the 2 i8imm operands as a single i16 offset.
2016 let offset0 = offset{7-0};
2017 let offset1 = offset{15-8};
2020 multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc,
2021 dag outs = (outs rc:$vdst),
2022 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds),
2023 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
2025 def "" : DS_Pseudo <opName, outs, ins, []>;
2027 let data0 = 0, data1 = 0 in {
2028 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2029 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2033 multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc,
2034 dag outs = (outs rc:$vdst),
2035 dag ins = (ins VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
2037 string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> {
2039 def "" : DS_Pseudo <opName, outs, ins, []>;
2041 let data0 = 0, data1 = 0, AsmMatchConverter = "cvtDSOffset01" in {
2042 def _si : DS_Real_si <op, opName, outs, ins, asm>;
2043 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
2047 multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc,
2049 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds),
2050 string asm = opName#" $addr, $data0"#"$offset$gds"> {
2052 def "" : DS_Pseudo <opName, outs, ins, []>,
2053 AtomicNoRet<opName, 0>;
2055 let data1 = 0, vdst = 0 in {
2056 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2057 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2061 multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc,
2063 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
2064 ds_offset0:$offset0, ds_offset1:$offset1, gds01:$gds),
2065 string asm = opName#" $addr, $data0, $data1"#"$offset0"#"$offset1"#"$gds"> {
2067 def "" : DS_Pseudo <opName, outs, ins, []>;
2069 let vdst = 0, AsmMatchConverter = "cvtDSOffset01" in {
2070 def _si : DS_Real_si <op, opName, outs, ins, asm>;
2071 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
2075 multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc,
2076 string noRetOp = "",
2077 dag outs = (outs rc:$vdst),
2078 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds),
2079 string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> {
2081 let hasPostISelHook = 1 in {
2082 def "" : DS_Pseudo <opName, outs, ins, []>,
2083 AtomicNoRet<noRetOp, 1>;
2086 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2087 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2092 multiclass DS_1A2D_RET_m <bits<8> op, string opName, RegisterClass rc,
2093 string noRetOp = "", dag ins,
2094 dag outs = (outs rc:$vdst),
2095 string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"#"$gds"> {
2097 let hasPostISelHook = 1 in {
2098 def "" : DS_Pseudo <opName, outs, ins, []>,
2099 AtomicNoRet<noRetOp, 1>;
2101 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2102 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2106 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
2107 string noRetOp = "", RegisterClass src = rc> :
2108 DS_1A2D_RET_m <op, asm, rc, noRetOp,
2109 (ins VGPR_32:$addr, src:$data0, src:$data1,
2110 ds_offset:$offset, gds:$gds)
2113 multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc,
2114 string noRetOp = opName,
2116 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
2117 ds_offset:$offset, gds:$gds),
2118 string asm = opName#" $addr, $data0, $data1"#"$offset"#"$gds"> {
2120 def "" : DS_Pseudo <opName, outs, ins, []>,
2121 AtomicNoRet<noRetOp, 0>;
2124 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2125 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2129 multiclass DS_0A_RET <bits<8> op, string opName,
2130 dag outs = (outs VGPR_32:$vdst),
2131 dag ins = (ins ds_offset:$offset, gds:$gds),
2132 string asm = opName#" $vdst"#"$offset"#"$gds"> {
2134 let mayLoad = 1, mayStore = 1 in {
2135 def "" : DS_Pseudo <opName, outs, ins, []>;
2137 let addr = 0, data0 = 0, data1 = 0 in {
2138 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2139 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2140 } // end addr = 0, data0 = 0, data1 = 0
2141 } // end mayLoad = 1, mayStore = 1
2144 multiclass DS_1A_RET_GDS <bits<8> op, string opName,
2145 dag outs = (outs VGPR_32:$vdst),
2146 dag ins = (ins VGPR_32:$addr, ds_offset_gds:$offset),
2147 string asm = opName#" $vdst, $addr"#"$offset gds"> {
2149 def "" : DS_Pseudo <opName, outs, ins, []>;
2151 let data0 = 0, data1 = 0, gds = 1 in {
2152 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2153 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2154 } // end data0 = 0, data1 = 0, gds = 1
2157 multiclass DS_1A_GDS <bits<8> op, string opName,
2159 dag ins = (ins VGPR_32:$addr),
2160 string asm = opName#" $addr gds"> {
2162 def "" : DS_Pseudo <opName, outs, ins, []>;
2164 let vdst = 0, data0 = 0, data1 = 0, offset0 = 0, offset1 = 0, gds = 1 in {
2165 def _si : DS_Real_si <op, opName, outs, ins, asm>;
2166 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
2167 } // end vdst = 0, data = 0, data1 = 0, gds = 1
2170 multiclass DS_1A <bits<8> op, string opName,
2172 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds),
2173 string asm = opName#" $addr"#"$offset"#"$gds"> {
2175 let mayLoad = 1, mayStore = 1 in {
2176 def "" : DS_Pseudo <opName, outs, ins, []>;
2178 let vdst = 0, data0 = 0, data1 = 0 in {
2179 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2180 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2181 } // let vdst = 0, data0 = 0, data1 = 0
2182 } // end mayLoad = 1, mayStore = 1
2185 //===----------------------------------------------------------------------===//
2187 //===----------------------------------------------------------------------===//
2189 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2190 MTBUF <outs, ins, "", pattern>,
2191 SIMCInstr<opName, SISubtarget.NONE> {
2193 let isCodeGenOnly = 1;
2196 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
2198 MTBUF <outs, ins, asm, []>,
2200 SIMCInstr<opName, SISubtarget.SI>;
2202 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
2203 MTBUF <outs, ins, asm, []>,
2205 SIMCInstr <opName, SISubtarget.VI>;
2207 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
2208 list<dag> pattern> {
2210 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
2212 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
2214 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
2218 let mayStore = 1, mayLoad = 0 in {
2220 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
2221 RegisterClass regClass> : MTBUF_m <
2223 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
2224 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
2225 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2226 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
2227 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2230 } // mayStore = 1, mayLoad = 0
2232 let mayLoad = 1, mayStore = 0 in {
2234 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
2235 RegisterClass regClass> : MTBUF_m <
2236 op, opName, (outs regClass:$dst),
2237 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
2238 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
2239 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2240 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
2241 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2244 } // mayLoad = 1, mayStore = 0
2246 //===----------------------------------------------------------------------===//
2248 //===----------------------------------------------------------------------===//
2250 class mubuf <bits<7> si, bits<7> vi = si> {
2251 field bits<7> SI = si;
2252 field bits<7> VI = vi;
2255 let isCodeGenOnly = 0 in {
2257 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
2258 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
2262 } // End let isCodeGenOnly = 0
2264 class MUBUF_vi <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
2265 MUBUF <outs, ins, asm, pattern>, MUBUFe_vi <op> {
2269 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
2270 bit IsAddr64 = is_addr64;
2271 string OpName = NAME # suffix;
2274 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2275 MUBUF <outs, ins, "", pattern>,
2276 SIMCInstr<opName, SISubtarget.NONE> {
2278 let isCodeGenOnly = 1;
2280 // dummy fields, so that we can use let statements around multiclasses
2290 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
2292 MUBUF <outs, ins, asm, []>,
2294 SIMCInstr<opName, SISubtarget.SI> {
2298 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
2300 MUBUF <outs, ins, asm, []>,
2302 SIMCInstr<opName, SISubtarget.VI> {
2306 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
2307 list<dag> pattern> {
2309 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2310 MUBUFAddr64Table <0>;
2312 let addr64 = 0, isCodeGenOnly = 0 in {
2313 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2316 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2319 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
2320 dag ins, string asm, list<dag> pattern> {
2322 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2323 MUBUFAddr64Table <1>;
2325 let addr64 = 1, isCodeGenOnly = 0 in {
2326 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2329 // There is no VI version. If the pseudo is selected, it should be lowered
2330 // for VI appropriately.
2333 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
2334 string asm, list<dag> pattern, bit is_return> {
2336 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2337 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
2338 AtomicNoRet<NAME#"_OFFSET", is_return>;
2340 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
2342 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2345 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2349 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
2350 string asm, list<dag> pattern, bit is_return> {
2352 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2353 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
2354 AtomicNoRet<NAME#"_ADDR64", is_return>;
2356 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
2357 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2360 // There is no VI version. If the pseudo is selected, it should be lowered
2361 // for VI appropriately.
2364 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
2365 ValueType vt, SDPatternOperator atomic> {
2367 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
2369 // No return variants
2372 defm _ADDR64 : MUBUFAtomicAddr64_m <
2373 op, name#"_addr64", (outs),
2374 (ins rc:$vdata, VReg_64:$vaddr, SReg_128:$srsrc,
2375 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2376 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
2379 defm _OFFSET : MUBUFAtomicOffset_m <
2380 op, name#"_offset", (outs),
2381 (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset,
2383 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
2387 // Variant that return values
2388 let glc = 1, Constraints = "$vdata = $vdata_in",
2389 DisableEncoding = "$vdata_in" in {
2391 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
2392 op, name#"_rtn_addr64", (outs rc:$vdata),
2393 (ins rc:$vdata_in, VReg_64:$vaddr, SReg_128:$srsrc,
2394 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2395 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
2397 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
2398 i16:$offset, i1:$slc), vt:$vdata_in))], 1
2401 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
2402 op, name#"_rtn_offset", (outs rc:$vdata),
2403 (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset,
2404 mbuf_offset:$offset, slc:$slc),
2405 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc$slc",
2407 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
2408 i1:$slc), vt:$vdata_in))], 1
2413 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
2416 // FIXME: tfe can't be an operand because it requires a separate
2417 // opcode because it needs an N+1 register class dest register.
2418 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
2419 ValueType load_vt = i32,
2420 SDPatternOperator ld = null_frag> {
2422 let mayLoad = 1, mayStore = 0 in {
2423 let offen = 0, idxen = 0, vaddr = 0 in {
2424 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
2425 (ins SReg_128:$srsrc, SCSrc_32:$soffset,
2426 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2427 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2428 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
2429 i32:$soffset, i16:$offset,
2430 i1:$glc, i1:$slc, i1:$tfe)))]>;
2433 let offen = 1, idxen = 0 in {
2434 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
2435 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2436 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
2438 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2441 let offen = 0, idxen = 1 in {
2442 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
2443 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2444 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2445 slc:$slc, tfe:$tfe),
2446 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2449 let offen = 1, idxen = 1 in {
2450 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
2451 (ins VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2452 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2453 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2456 let offen = 0, idxen = 0 in {
2457 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
2458 (ins VReg_64:$vaddr, SReg_128:$srsrc,
2459 SCSrc_32:$soffset, mbuf_offset:$offset,
2460 glc:$glc, slc:$slc, tfe:$tfe),
2461 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#
2462 "$glc"#"$slc"#"$tfe",
2463 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
2464 i64:$vaddr, i32:$soffset,
2465 i16:$offset, i1:$glc, i1:$slc,
2471 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
2472 ValueType store_vt = i32, SDPatternOperator st = null_frag> {
2473 let mayLoad = 0, mayStore = 1 in {
2474 defm : MUBUF_m <op, name, (outs),
2475 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2476 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
2478 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
2479 "$glc"#"$slc"#"$tfe", []>;
2481 let offen = 0, idxen = 0, vaddr = 0 in {
2482 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
2483 (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset,
2484 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2485 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2486 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
2487 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
2488 } // offen = 0, idxen = 0, vaddr = 0
2490 let offen = 1, idxen = 0 in {
2491 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
2492 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2493 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2494 slc:$slc, tfe:$tfe),
2495 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
2496 "$glc"#"$slc"#"$tfe", []>;
2497 } // end offen = 1, idxen = 0
2499 let offen = 0, idxen = 1 in {
2500 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs),
2501 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2502 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2503 slc:$slc, tfe:$tfe),
2504 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2507 let offen = 1, idxen = 1 in {
2508 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs),
2509 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2510 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2511 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2514 let offen = 0, idxen = 0 in {
2515 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
2516 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc,
2518 mbuf_offset:$offset, glc:$glc, slc:$slc,
2520 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#
2521 "$offset"#"$glc"#"$slc"#"$tfe",
2522 [(st store_vt:$vdata,
2523 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
2524 i32:$soffset, i16:$offset,
2525 i1:$glc, i1:$slc, i1:$tfe))]>;
2527 } // End mayLoad = 0, mayStore = 1
2530 // For cache invalidation instructions.
2531 multiclass MUBUF_Invalidate <mubuf op, string opName, SDPatternOperator node> {
2532 let hasSideEffects = 1, mayStore = 1, AsmMatchConverter = "" in {
2533 def "" : MUBUF_Pseudo <opName, (outs), (ins), [(node)]>;
2535 // Set everything to 0.
2536 let offset = 0, offen = 0, idxen = 0, glc = 0, vaddr = 0,
2537 vdata = 0, srsrc = 0, slc = 0, tfe = 0, soffset = 0 in {
2539 def _si : MUBUF_Real_si <op, opName, (outs), (ins), opName>;
2542 def _vi : MUBUF_Real_vi <op, opName, (outs), (ins), opName>;
2544 } // End hasSideEffects = 1, mayStore = 1, AsmMatchConverter = ""
2547 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
2548 FLAT <op, (outs regClass:$vdst),
2549 (ins VReg_64:$addr, glc_flat:$glc, slc_flat:$slc, tfe_flat:$tfe),
2550 asm#" $vdst, $addr"#"$glc"#"$slc"#"$tfe", []> {
2555 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
2556 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr,
2557 glc_flat:$glc, slc_flat:$slc, tfe_flat:$tfe),
2558 name#" $data, $addr"#"$glc"#"$slc"#"$tfe",
2568 multiclass FLAT_ATOMIC <bits<7> op, string name, RegisterClass vdst_rc,
2569 RegisterClass data_rc = vdst_rc> {
2571 let mayLoad = 1, mayStore = 1 in {
2572 def "" : FLAT <op, (outs),
2573 (ins VReg_64:$addr, data_rc:$data, slc_flat_atomic:$slc,
2574 tfe_flat_atomic:$tfe),
2575 name#" $addr, $data"#"$slc"#"$tfe", []>,
2576 AtomicNoRet <NAME, 0> {
2581 def _RTN : FLAT <op, (outs vdst_rc:$vdst),
2582 (ins VReg_64:$addr, data_rc:$data, slc_flat_atomic:$slc,
2583 tfe_flat_atomic:$tfe),
2584 name#" $vdst, $addr, $data glc"#"$slc"#"$tfe", []>,
2585 AtomicNoRet <NAME, 1> {
2587 let hasPostISelHook = 1;
2592 class MIMG_Mask <string op, int channels> {
2594 int Channels = channels;
2597 class MIMG_NoSampler_Helper <bits<7> op, string asm,
2598 RegisterClass dst_rc,
2599 RegisterClass src_rc> : MIMG <
2601 (outs dst_rc:$vdata),
2602 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2603 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2605 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2606 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
2611 let hasPostISelHook = 1;
2614 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
2615 RegisterClass dst_rc,
2617 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
2618 MIMG_Mask<asm#"_V1", channels>;
2619 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
2620 MIMG_Mask<asm#"_V2", channels>;
2621 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
2622 MIMG_Mask<asm#"_V4", channels>;
2625 multiclass MIMG_NoSampler <bits<7> op, string asm> {
2626 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
2627 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
2628 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
2629 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
2632 class MIMG_Sampler_Helper <bits<7> op, string asm,
2633 RegisterClass dst_rc,
2634 RegisterClass src_rc, int wqm> : MIMG <
2636 (outs dst_rc:$vdata),
2637 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2638 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2639 SReg_256:$srsrc, SReg_128:$ssamp),
2640 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2641 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2645 let hasPostISelHook = 1;
2649 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2650 RegisterClass dst_rc,
2651 int channels, int wqm> {
2652 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2653 MIMG_Mask<asm#"_V1", channels>;
2654 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2655 MIMG_Mask<asm#"_V2", channels>;
2656 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2657 MIMG_Mask<asm#"_V4", channels>;
2658 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2659 MIMG_Mask<asm#"_V8", channels>;
2660 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2661 MIMG_Mask<asm#"_V16", channels>;
2664 multiclass MIMG_Sampler <bits<7> op, string asm> {
2665 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2666 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2667 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2668 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2671 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2672 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2673 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2674 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2675 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2678 class MIMG_Gather_Helper <bits<7> op, string asm,
2679 RegisterClass dst_rc,
2680 RegisterClass src_rc, int wqm> : MIMG <
2682 (outs dst_rc:$vdata),
2683 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2684 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2685 SReg_256:$srsrc, SReg_128:$ssamp),
2686 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2687 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2692 // DMASK was repurposed for GATHER4. 4 components are always
2693 // returned and DMASK works like a swizzle - it selects
2694 // the component to fetch. The only useful DMASK values are
2695 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2696 // (red,red,red,red) etc.) The ISA document doesn't mention
2698 // Therefore, disable all code which updates DMASK by setting these two:
2700 let hasPostISelHook = 0;
2704 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2705 RegisterClass dst_rc,
2706 int channels, int wqm> {
2707 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2708 MIMG_Mask<asm#"_V1", channels>;
2709 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2710 MIMG_Mask<asm#"_V2", channels>;
2711 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2712 MIMG_Mask<asm#"_V4", channels>;
2713 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2714 MIMG_Mask<asm#"_V8", channels>;
2715 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2716 MIMG_Mask<asm#"_V16", channels>;
2719 multiclass MIMG_Gather <bits<7> op, string asm> {
2720 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2721 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2722 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2723 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2726 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2727 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2728 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2729 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2730 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2733 //===----------------------------------------------------------------------===//
2734 // Vector instruction mappings
2735 //===----------------------------------------------------------------------===//
2737 // Maps an opcode in e32 form to its e64 equivalent
2738 def getVOPe64 : InstrMapping {
2739 let FilterClass = "VOP";
2740 let RowFields = ["OpName"];
2741 let ColFields = ["Size"];
2743 let ValueCols = [["8"]];
2746 // Maps an opcode in e64 form to its e32 equivalent
2747 def getVOPe32 : InstrMapping {
2748 let FilterClass = "VOP";
2749 let RowFields = ["OpName"];
2750 let ColFields = ["Size"];
2752 let ValueCols = [["4"]];
2755 def getMaskedMIMGOp : InstrMapping {
2756 let FilterClass = "MIMG_Mask";
2757 let RowFields = ["Op"];
2758 let ColFields = ["Channels"];
2760 let ValueCols = [["1"], ["2"], ["3"] ];
2763 // Maps an commuted opcode to its original version
2764 def getCommuteOrig : InstrMapping {
2765 let FilterClass = "VOP2_REV";
2766 let RowFields = ["RevOp"];
2767 let ColFields = ["IsOrig"];
2769 let ValueCols = [["1"]];
2772 // Maps an original opcode to its commuted version
2773 def getCommuteRev : InstrMapping {
2774 let FilterClass = "VOP2_REV";
2775 let RowFields = ["RevOp"];
2776 let ColFields = ["IsOrig"];
2778 let ValueCols = [["0"]];
2781 def getCommuteCmpOrig : InstrMapping {
2782 let FilterClass = "VOP2_REV";
2783 let RowFields = ["RevOp"];
2784 let ColFields = ["IsOrig"];
2786 let ValueCols = [["1"]];
2789 // Maps an original opcode to its commuted version
2790 def getCommuteCmpRev : InstrMapping {
2791 let FilterClass = "VOP2_REV";
2792 let RowFields = ["RevOp"];
2793 let ColFields = ["IsOrig"];
2795 let ValueCols = [["0"]];
2799 def getMCOpcodeGen : InstrMapping {
2800 let FilterClass = "SIMCInstr";
2801 let RowFields = ["PseudoInstr"];
2802 let ColFields = ["Subtarget"];
2803 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2804 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2807 def getAddr64Inst : InstrMapping {
2808 let FilterClass = "MUBUFAddr64Table";
2809 let RowFields = ["OpName"];
2810 let ColFields = ["IsAddr64"];
2812 let ValueCols = [["1"]];
2815 // Maps an atomic opcode to its version with a return value.
2816 def getAtomicRetOp : InstrMapping {
2817 let FilterClass = "AtomicNoRet";
2818 let RowFields = ["NoRetOp"];
2819 let ColFields = ["IsRet"];
2821 let ValueCols = [["1"]];
2824 // Maps an atomic opcode to its returnless version.
2825 def getAtomicNoRetOp : InstrMapping {
2826 let FilterClass = "AtomicNoRet";
2827 let RowFields = ["NoRetOp"];
2828 let ColFields = ["IsRet"];
2830 let ValueCols = [["0"]];
2833 include "SIInstructions.td"
2834 include "CIInstructions.td"
2835 include "VIInstructions.td"