1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 def isCI : Predicate<"Subtarget->getGeneration() "
10 ">= AMDGPUSubtarget::SEA_ISLANDS">;
11 def isVI : Predicate <
12 "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
13 AssemblerPredicate<"FeatureGCN3Encoding">;
15 def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">;
22 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
23 field bits<8> SI = si;
24 field bits<8> VI = vi;
26 field bits<9> SI3 = {0, si{7-0}};
27 field bits<10> VI3 = {0, 0, vi{7-0}};
30 class vop1 <bits<8> si, bits<8> vi = si> : vop {
31 field bits<8> SI = si;
32 field bits<8> VI = vi;
34 field bits<9> SI3 = {1, 1, si{6-0}};
35 field bits<10> VI3 = !add(0x140, vi);
38 class vop2 <bits<6> si, bits<6> vi = si> : vop {
39 field bits<6> SI = si;
40 field bits<6> VI = vi;
42 field bits<9> SI3 = {1, 0, 0, si{5-0}};
43 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
46 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
47 // that doesn't have VOP2 encoding on VI
48 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
52 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
57 class sop1 <bits<8> si, bits<8> vi = si> {
58 field bits<8> SI = si;
59 field bits<8> VI = vi;
62 class sop2 <bits<7> si, bits<7> vi = si> {
63 field bits<7> SI = si;
64 field bits<7> VI = vi;
67 class sopk <bits<5> si, bits<5> vi = si> {
68 field bits<5> SI = si;
69 field bits<5> VI = vi;
72 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
73 // in AMDGPUInstrInfo.cpp
80 //===----------------------------------------------------------------------===//
82 //===----------------------------------------------------------------------===//
84 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
85 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
86 [SDNPMayLoad, SDNPMemOperand]
89 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
91 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
92 SDTCisVT<1, iAny>, // vdata(VGPR)
93 SDTCisVT<2, i32>, // num_channels(imm)
94 SDTCisVT<3, i32>, // vaddr(VGPR)
95 SDTCisVT<4, i32>, // soffset(SGPR)
96 SDTCisVT<5, i32>, // inst_offset(imm)
97 SDTCisVT<6, i32>, // dfmt(imm)
98 SDTCisVT<7, i32>, // nfmt(imm)
99 SDTCisVT<8, i32>, // offen(imm)
100 SDTCisVT<9, i32>, // idxen(imm)
101 SDTCisVT<10, i32>, // glc(imm)
102 SDTCisVT<11, i32>, // slc(imm)
103 SDTCisVT<12, i32> // tfe(imm)
105 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
108 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
109 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
113 class SDSample<string opcode> : SDNode <opcode,
114 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
115 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
118 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
119 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
120 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
121 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
123 def SIconstdata_ptr : SDNode<
124 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
127 //===----------------------------------------------------------------------===//
128 // SDNodes and PatFrag for local loads and stores to enable s_mov_b32 m0, -1
129 // to be glued to the memory instructions.
130 //===----------------------------------------------------------------------===//
132 def SIld_local : SDNode <"ISD::LOAD", SDTLoad,
133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
136 def si_ld_local : PatFrag <(ops node:$ptr), (SIld_local node:$ptr), [{
137 return isLocalLoad(cast<LoadSDNode>(N));
140 def si_load_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{
141 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
142 cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
145 def si_load_local_align8 : Aligned8Bytes <
146 (ops node:$ptr), (si_load_local node:$ptr)
149 def si_sextload_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{
150 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
152 def si_az_extload_local : AZExtLoadBase <si_ld_local>;
154 multiclass SIExtLoadLocal <PatFrag ld_node> {
156 def _i8 : PatFrag <(ops node:$ptr), (ld_node node:$ptr),
157 [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;}]
160 def _i16 : PatFrag <(ops node:$ptr), (ld_node node:$ptr),
161 [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;}]
165 defm si_sextload_local : SIExtLoadLocal <si_sextload_local>;
166 defm si_az_extload_local : SIExtLoadLocal <si_az_extload_local>;
168 def SIst_local : SDNode <"ISD::STORE", SDTStore,
169 [SDNPHasChain, SDNPMayStore, SDNPMemOperand, SDNPInGlue]
172 def si_st_local : PatFrag <
173 (ops node:$val, node:$ptr), (SIst_local node:$val, node:$ptr), [{
174 return isLocalStore(cast<StoreSDNode>(N));
177 def si_store_local : PatFrag <
178 (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{
179 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
180 !cast<StoreSDNode>(N)->isTruncatingStore();
183 def si_store_local_align8 : Aligned8Bytes <
184 (ops node:$val, node:$ptr), (si_store_local node:$val, node:$ptr)
187 def si_truncstore_local : PatFrag <
188 (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{
189 return cast<StoreSDNode>(N)->isTruncatingStore();
192 def si_truncstore_local_i8 : PatFrag <
193 (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{
194 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
197 def si_truncstore_local_i16 : PatFrag <
198 (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{
199 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
202 multiclass SIAtomicM0Glue2 <string op_name> {
204 def _glue : SDNode <"ISD::ATOMIC_"#op_name, SDTAtomic2,
205 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
208 def _local : local_binary_atomic_op <!cast<SDNode>(NAME#"_glue")>;
211 defm si_atomic_load_add : SIAtomicM0Glue2 <"LOAD_ADD">;
212 defm si_atomic_load_and : SIAtomicM0Glue2 <"LOAD_AND">;
213 defm si_atomic_load_min : SIAtomicM0Glue2 <"LOAD_MIN">;
214 defm si_atomic_load_max : SIAtomicM0Glue2 <"LOAD_MAX">;
215 defm si_atomic_load_or : SIAtomicM0Glue2 <"LOAD_OR">;
216 defm si_atomic_load_sub : SIAtomicM0Glue2 <"LOAD_SUB">;
217 defm si_atomic_load_xor : SIAtomicM0Glue2 <"LOAD_XOR">;
218 defm si_atomic_load_umin : SIAtomicM0Glue2 <"LOAD_UMIN">;
219 defm si_atomic_load_umax : SIAtomicM0Glue2 <"LOAD_UMAX">;
220 defm si_atomic_swap : SIAtomicM0Glue2 <"SWAP">;
222 def si_atomic_cmp_swap_glue : SDNode <"ISD::ATOMIC_CMP_SWAP", SDTAtomic3,
223 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
226 defm si_atomic_cmp_swap : AtomicCmpSwapLocal <si_atomic_cmp_swap_glue>;
228 // Transformation function, extract the lower 32bit of a 64bit immediate
229 def LO32 : SDNodeXForm<imm, [{
230 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, SDLoc(N),
234 def LO32f : SDNodeXForm<fpimm, [{
235 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
236 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
239 // Transformation function, extract the upper 32bit of a 64bit immediate
240 def HI32 : SDNodeXForm<imm, [{
241 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, SDLoc(N), MVT::i32);
244 def HI32f : SDNodeXForm<fpimm, [{
245 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
246 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), SDLoc(N),
250 def IMM8bitDWORD : PatLeaf <(imm),
251 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
254 def as_dword_i32imm : SDNodeXForm<imm, [{
255 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, SDLoc(N), MVT::i32);
258 def as_i1imm : SDNodeXForm<imm, [{
259 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i1);
262 def as_i8imm : SDNodeXForm<imm, [{
263 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i8);
266 def as_i16imm : SDNodeXForm<imm, [{
267 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
270 def as_i32imm: SDNodeXForm<imm, [{
271 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
274 def as_i64imm: SDNodeXForm<imm, [{
275 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
278 // Copied from the AArch64 backend:
279 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
280 return CurDAG->getTargetConstant(
281 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
284 // Copied from the AArch64 backend:
285 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
286 return CurDAG->getTargetConstant(
287 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
290 def IMM8bit : PatLeaf <(imm),
291 [{return isUInt<8>(N->getZExtValue());}]
294 def IMM12bit : PatLeaf <(imm),
295 [{return isUInt<12>(N->getZExtValue());}]
298 def IMM16bit : PatLeaf <(imm),
299 [{return isUInt<16>(N->getZExtValue());}]
302 def IMM20bit : PatLeaf <(imm),
303 [{return isUInt<20>(N->getZExtValue());}]
306 def IMM32bit : PatLeaf <(imm),
307 [{return isUInt<32>(N->getZExtValue());}]
310 def mubuf_vaddr_offset : PatFrag<
311 (ops node:$ptr, node:$offset, node:$imm_offset),
312 (add (add node:$ptr, node:$offset), node:$imm_offset)
315 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
316 return isInlineImmediate(N);
319 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
320 return isInlineImmediate(N);
323 class SGPRImm <dag frag> : PatLeaf<frag, [{
324 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
327 const SIRegisterInfo *SIRI =
328 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
329 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
331 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
338 //===----------------------------------------------------------------------===//
340 //===----------------------------------------------------------------------===//
342 def FRAMEri32 : Operand<iPTR> {
343 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
346 def SoppBrTarget : AsmOperandClass {
347 let Name = "SoppBrTarget";
348 let ParserMethod = "parseSOppBrTarget";
351 def sopp_brtarget : Operand<OtherVT> {
352 let EncoderMethod = "getSOPPBrEncoding";
353 let OperandType = "OPERAND_PCREL";
354 let ParserMatchClass = SoppBrTarget;
357 include "SIInstrFormats.td"
358 include "VIInstrFormats.td"
360 def MubufOffsetMatchClass : AsmOperandClass {
361 let Name = "MubufOffset";
362 let ParserMethod = "parseMubufOptionalOps";
363 let RenderMethod = "addImmOperands";
366 class DSOffsetBaseMatchClass <string parser> : AsmOperandClass {
367 let Name = "DSOffset"#parser;
368 let ParserMethod = parser;
369 let RenderMethod = "addImmOperands";
370 let PredicateMethod = "isDSOffset";
373 def DSOffsetMatchClass : DSOffsetBaseMatchClass <"parseDSOptionalOps">;
374 def DSOffsetGDSMatchClass : DSOffsetBaseMatchClass <"parseDSOffsetOptional">;
376 def DSOffset01MatchClass : AsmOperandClass {
377 let Name = "DSOffset1";
378 let ParserMethod = "parseDSOff01OptionalOps";
379 let RenderMethod = "addImmOperands";
380 let PredicateMethod = "isDSOffset01";
383 class GDSBaseMatchClass <string parser> : AsmOperandClass {
384 let Name = "GDS"#parser;
385 let PredicateMethod = "isImm";
386 let ParserMethod = parser;
387 let RenderMethod = "addImmOperands";
390 def GDSMatchClass : GDSBaseMatchClass <"parseDSOptionalOps">;
391 def GDS01MatchClass : GDSBaseMatchClass <"parseDSOff01OptionalOps">;
393 class GLCBaseMatchClass <string parser> : AsmOperandClass {
394 let Name = "GLC"#parser;
395 let PredicateMethod = "isImm";
396 let ParserMethod = parser;
397 let RenderMethod = "addImmOperands";
400 def GLCMubufMatchClass : GLCBaseMatchClass <"parseMubufOptionalOps">;
401 def GLCFlatMatchClass : GLCBaseMatchClass <"parseFlatOptionalOps">;
403 class SLCBaseMatchClass <string parser> : AsmOperandClass {
404 let Name = "SLC"#parser;
405 let PredicateMethod = "isImm";
406 let ParserMethod = parser;
407 let RenderMethod = "addImmOperands";
410 def SLCMubufMatchClass : SLCBaseMatchClass <"parseMubufOptionalOps">;
411 def SLCFlatMatchClass : SLCBaseMatchClass <"parseFlatOptionalOps">;
412 def SLCFlatAtomicMatchClass : SLCBaseMatchClass <"parseFlatAtomicOptionalOps">;
414 class TFEBaseMatchClass <string parser> : AsmOperandClass {
415 let Name = "TFE"#parser;
416 let PredicateMethod = "isImm";
417 let ParserMethod = parser;
418 let RenderMethod = "addImmOperands";
421 def TFEMubufMatchClass : TFEBaseMatchClass <"parseMubufOptionalOps">;
422 def TFEFlatMatchClass : TFEBaseMatchClass <"parseFlatOptionalOps">;
423 def TFEFlatAtomicMatchClass : TFEBaseMatchClass <"parseFlatAtomicOptionalOps">;
425 def OModMatchClass : AsmOperandClass {
427 let PredicateMethod = "isImm";
428 let ParserMethod = "parseVOP3OptionalOps";
429 let RenderMethod = "addImmOperands";
432 def ClampMatchClass : AsmOperandClass {
434 let PredicateMethod = "isImm";
435 let ParserMethod = "parseVOP3OptionalOps";
436 let RenderMethod = "addImmOperands";
439 let OperandType = "OPERAND_IMMEDIATE" in {
441 def offen : Operand<i1> {
442 let PrintMethod = "printOffen";
444 def idxen : Operand<i1> {
445 let PrintMethod = "printIdxen";
447 def addr64 : Operand<i1> {
448 let PrintMethod = "printAddr64";
450 def mbuf_offset : Operand<i16> {
451 let PrintMethod = "printMBUFOffset";
452 let ParserMatchClass = MubufOffsetMatchClass;
454 class ds_offset_base <AsmOperandClass mc> : Operand<i16> {
455 let PrintMethod = "printDSOffset";
456 let ParserMatchClass = mc;
458 def ds_offset : ds_offset_base <DSOffsetMatchClass>;
459 def ds_offset_gds : ds_offset_base <DSOffsetGDSMatchClass>;
461 def ds_offset0 : Operand<i8> {
462 let PrintMethod = "printDSOffset0";
463 let ParserMatchClass = DSOffset01MatchClass;
465 def ds_offset1 : Operand<i8> {
466 let PrintMethod = "printDSOffset1";
467 let ParserMatchClass = DSOffset01MatchClass;
469 class gds_base <AsmOperandClass mc> : Operand <i1> {
470 let PrintMethod = "printGDS";
471 let ParserMatchClass = mc;
473 def gds : gds_base <GDSMatchClass>;
475 def gds01 : gds_base <GDS01MatchClass>;
477 class glc_base <AsmOperandClass mc> : Operand <i1> {
478 let PrintMethod = "printGLC";
479 let ParserMatchClass = mc;
482 def glc : glc_base <GLCMubufMatchClass>;
483 def glc_flat : glc_base <GLCFlatMatchClass>;
485 class slc_base <AsmOperandClass mc> : Operand <i1> {
486 let PrintMethod = "printSLC";
487 let ParserMatchClass = mc;
490 def slc : slc_base <SLCMubufMatchClass>;
491 def slc_flat : slc_base <SLCFlatMatchClass>;
492 def slc_flat_atomic : slc_base <SLCFlatAtomicMatchClass>;
494 class tfe_base <AsmOperandClass mc> : Operand <i1> {
495 let PrintMethod = "printTFE";
496 let ParserMatchClass = mc;
499 def tfe : tfe_base <TFEMubufMatchClass>;
500 def tfe_flat : tfe_base <TFEFlatMatchClass>;
501 def tfe_flat_atomic : tfe_base <TFEFlatAtomicMatchClass>;
503 def omod : Operand <i32> {
504 let PrintMethod = "printOModSI";
505 let ParserMatchClass = OModMatchClass;
508 def ClampMod : Operand <i1> {
509 let PrintMethod = "printClampSI";
510 let ParserMatchClass = ClampMatchClass;
513 } // End OperandType = "OPERAND_IMMEDIATE"
515 def VOPDstS64 : VOPDstOperand <SReg_64>;
517 //===----------------------------------------------------------------------===//
519 //===----------------------------------------------------------------------===//
521 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
522 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
524 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
525 def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">;
526 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
527 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
528 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
529 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
531 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
532 def VOP3NoMods0 : ComplexPattern<untyped, 4, "SelectVOP3NoMods0">;
533 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
534 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
535 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
536 def VOP3NoMods : ComplexPattern<untyped, 2, "SelectVOP3NoMods">;
538 //===----------------------------------------------------------------------===//
539 // SI assembler operands
540 //===----------------------------------------------------------------------===//
561 //===----------------------------------------------------------------------===//
563 // SI Instruction multiclass helpers.
565 // Instructions with _32 take 32-bit operands.
566 // Instructions with _64 take 64-bit operands.
568 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
569 // encoding is the standard encoding, but instruction that make use of
570 // any of the instruction modifiers must use the 64-bit encoding.
572 // Instructions with _e32 use the 32-bit encoding.
573 // Instructions with _e64 use the 64-bit encoding.
575 //===----------------------------------------------------------------------===//
577 class SIMCInstr <string pseudo, int subtarget> {
578 string PseudoInstr = pseudo;
579 int Subtarget = subtarget;
582 //===----------------------------------------------------------------------===//
584 //===----------------------------------------------------------------------===//
586 class EXPCommon : InstSI<
588 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
589 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
590 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
599 let isPseudo = 1, isCodeGenOnly = 1 in {
600 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
603 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
605 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
608 //===----------------------------------------------------------------------===//
610 //===----------------------------------------------------------------------===//
612 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
613 SOP1 <outs, ins, "", pattern>,
614 SIMCInstr<opName, SISubtarget.NONE> {
616 let isCodeGenOnly = 1;
619 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
620 SOP1 <outs, ins, asm, []>,
622 SIMCInstr<opName, SISubtarget.SI> {
623 let isCodeGenOnly = 0;
624 let AssemblerPredicates = [isSICI];
627 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
628 SOP1 <outs, ins, asm, []>,
630 SIMCInstr<opName, SISubtarget.VI> {
631 let isCodeGenOnly = 0;
632 let AssemblerPredicates = [isVI];
635 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
638 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
640 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
642 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
646 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
647 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
648 opName#" $dst, $src0", pattern
651 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
652 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
653 opName#" $dst, $src0", pattern
656 // no input, 64-bit output.
657 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
658 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
660 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
665 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
671 // 64-bit input, no output
672 multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
673 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
675 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
680 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
686 // 64-bit input, 32-bit output.
687 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
688 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
689 opName#" $dst, $src0", pattern
692 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
693 SOP2<outs, ins, "", pattern>,
694 SIMCInstr<opName, SISubtarget.NONE> {
696 let isCodeGenOnly = 1;
699 // Pseudo instructions have no encodings, but adding this field here allows
701 // let sdst = xxx in {
702 // for multiclasses that include both real and pseudo instructions.
703 field bits<7> sdst = 0;
706 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
707 SOP2<outs, ins, asm, []>,
709 SIMCInstr<opName, SISubtarget.SI> {
710 let AssemblerPredicates = [isSICI];
713 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
714 SOP2<outs, ins, asm, []>,
716 SIMCInstr<opName, SISubtarget.VI> {
717 let AssemblerPredicates = [isVI];
720 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
723 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
725 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
727 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
731 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
732 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
733 opName#" $dst, $src0, $src1", pattern
736 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
737 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
738 opName#" $dst, $src0, $src1", pattern
741 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
742 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
743 opName#" $dst, $src0, $src1", pattern
746 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
747 string opName, PatLeaf cond> : SOPC <
748 op, (outs), (ins rc:$src0, rc:$src1),
749 opName#" $src0, $src1", []> {
753 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
754 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
756 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
757 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
759 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
760 SOPK <outs, ins, "", pattern>,
761 SIMCInstr<opName, SISubtarget.NONE> {
763 let isCodeGenOnly = 1;
766 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
767 SOPK <outs, ins, asm, []>,
769 SIMCInstr<opName, SISubtarget.SI> {
770 let AssemblerPredicates = [isSICI];
771 let isCodeGenOnly = 0;
774 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
775 SOPK <outs, ins, asm, []>,
777 SIMCInstr<opName, SISubtarget.VI> {
778 let AssemblerPredicates = [isVI];
779 let isCodeGenOnly = 0;
782 multiclass SOPK_m <sopk op, string opName, dag outs, dag ins, string opAsm,
783 string asm = opName#opAsm> {
784 def "" : SOPK_Pseudo <opName, outs, ins, []>;
786 def _si : SOPK_Real_si <op, opName, outs, ins, asm>;
788 def _vi : SOPK_Real_vi <op, opName, outs, ins, asm>;
792 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
793 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
796 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
797 opName#" $dst, $src0">;
799 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
800 opName#" $dst, $src0">;
803 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
804 def "" : SOPK_Pseudo <opName, (outs),
805 (ins SReg_32:$src0, u16imm:$src1), pattern> {
810 def _si : SOPK_Real_si <op, opName, (outs),
811 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16"> {
815 def _vi : SOPK_Real_vi <op, opName, (outs),
816 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16"> {
821 multiclass SOPK_32TIE <sopk op, string opName, list<dag> pattern> : SOPK_m <
822 op, opName, (outs SReg_32:$sdst), (ins SReg_32:$src0, u16imm:$simm16),
826 multiclass SOPK_IMM32 <sopk op, string opName, dag outs, dag ins,
827 string argAsm, string asm = opName#argAsm> {
829 def "" : SOPK_Pseudo <opName, outs, ins, []>;
831 def _si : SOPK <outs, ins, asm, []>,
833 SIMCInstr<opName, SISubtarget.SI> {
834 let AssemblerPredicates = [isSICI];
835 let isCodeGenOnly = 0;
838 def _vi : SOPK <outs, ins, asm, []>,
840 SIMCInstr<opName, SISubtarget.VI> {
841 let AssemblerPredicates = [isVI];
842 let isCodeGenOnly = 0;
845 //===----------------------------------------------------------------------===//
847 //===----------------------------------------------------------------------===//
849 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
850 SMRD <outs, ins, "", pattern>,
851 SIMCInstr<opName, SISubtarget.NONE> {
853 let isCodeGenOnly = 1;
856 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
858 SMRD <outs, ins, asm, []>,
860 SIMCInstr<opName, SISubtarget.SI> {
861 let AssemblerPredicates = [isSICI];
864 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
866 SMRD <outs, ins, asm, []>,
868 SIMCInstr<opName, SISubtarget.VI> {
869 let AssemblerPredicates = [isVI];
872 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
873 string asm, list<dag> pattern> {
875 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
877 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
879 // glc is only applicable to scalar stores, which are not yet
882 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
886 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
887 RegisterClass dstClass> {
889 op, opName#"_IMM", 1, (outs dstClass:$dst),
890 (ins baseClass:$sbase, u32imm:$offset),
891 opName#" $dst, $sbase, $offset", []
894 defm _SGPR : SMRD_m <
895 op, opName#"_SGPR", 0, (outs dstClass:$dst),
896 (ins baseClass:$sbase, SReg_32:$soff),
897 opName#" $dst, $sbase, $soff", []
901 //===----------------------------------------------------------------------===//
902 // Vector ALU classes
903 //===----------------------------------------------------------------------===//
905 // This must always be right before the operand being input modified.
906 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
907 let PrintMethod = "printOperandAndMods";
910 def InputModsMatchClass : AsmOperandClass {
911 let Name = "RegWithInputMods";
914 def InputModsNoDefault : Operand <i32> {
915 let PrintMethod = "printOperandAndMods";
916 let ParserMatchClass = InputModsMatchClass;
919 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
921 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
922 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
926 // Returns the register class to use for the destination of VOP[123C]
927 // instructions for the given VT.
928 class getVALUDstForVT<ValueType VT> {
929 RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
930 !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
931 VOPDstOperand<SReg_64>)); // else VT == i1
934 // Returns the register class to use for source 0 of VOP[12C]
935 // instructions for the given VT.
936 class getVOPSrc0ForVT<ValueType VT> {
937 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
940 // Returns the register class to use for source 1 of VOP[12C] for the
942 class getVOPSrc1ForVT<ValueType VT> {
943 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
946 // Returns the register class to use for sources of VOP3 instructions for the
948 class getVOP3SrcForVT<ValueType VT> {
949 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
952 // Returns 1 if the source arguments have modifiers, 0 if they do not.
953 class hasModifiers<ValueType SrcVT> {
954 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
955 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
958 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
959 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
960 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
961 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
965 // Returns the input arguments for VOP3 instructions for the given SrcVT.
966 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
967 RegisterOperand Src2RC, int NumSrcArgs,
971 !if (!eq(NumSrcArgs, 1),
972 !if (!eq(HasModifiers, 1),
973 // VOP1 with modifiers
974 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
975 ClampMod:$clamp, omod:$omod)
977 // VOP1 without modifiers
980 !if (!eq(NumSrcArgs, 2),
981 !if (!eq(HasModifiers, 1),
982 // VOP 2 with modifiers
983 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
984 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
985 ClampMod:$clamp, omod:$omod)
987 // VOP2 without modifiers
988 (ins Src0RC:$src0, Src1RC:$src1)
990 /* NumSrcArgs == 3 */,
991 !if (!eq(HasModifiers, 1),
992 // VOP3 with modifiers
993 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
994 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
995 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
996 ClampMod:$clamp, omod:$omod)
998 // VOP3 without modifiers
999 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
1003 // Returns the assembly string for the inputs and outputs of a VOP[12C]
1004 // instruction. This does not add the _e32 suffix, so it can be reused
1006 class getAsm32 <int NumSrcArgs> {
1007 string src1 = ", $src1";
1008 string src2 = ", $src2";
1009 string ret = "$dst, $src0"#
1010 !if(!eq(NumSrcArgs, 1), "", src1)#
1011 !if(!eq(NumSrcArgs, 3), src2, "");
1014 // Returns the assembly string for the inputs and outputs of a VOP3
1016 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
1017 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
1018 string src1 = !if(!eq(NumSrcArgs, 1), "",
1019 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
1020 " $src1_modifiers,"));
1021 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
1023 !if(!eq(HasModifiers, 0),
1024 getAsm32<NumSrcArgs>.ret,
1025 "$dst, "#src0#src1#src2#"$clamp"#"$omod");
1029 class VOPProfile <list<ValueType> _ArgVT> {
1031 field list<ValueType> ArgVT = _ArgVT;
1033 field ValueType DstVT = ArgVT[0];
1034 field ValueType Src0VT = ArgVT[1];
1035 field ValueType Src1VT = ArgVT[2];
1036 field ValueType Src2VT = ArgVT[3];
1037 field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
1038 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
1039 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
1040 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
1041 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
1042 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
1044 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
1045 field bit HasModifiers = hasModifiers<Src0VT>.ret;
1047 field dag Outs = (outs DstRC:$dst);
1049 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
1050 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
1053 field string Asm32 = getAsm32<NumSrcArgs>.ret;
1054 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
1057 // FIXME: I think these F16/I16 profiles will need to use f16/i16 types in order
1058 // for the instruction patterns to work.
1059 def VOP_F16_F16 : VOPProfile <[f32, f32, untyped, untyped]>;
1060 def VOP_F16_I16 : VOPProfile <[f32, i32, untyped, untyped]>;
1061 def VOP_I16_F16 : VOPProfile <[i32, f32, untyped, untyped]>;
1063 def VOP_F16_F16_F16 : VOPProfile <[f32, f32, f32, untyped]>;
1064 def VOP_F16_F16_I16 : VOPProfile <[f32, f32, i32, untyped]>;
1065 def VOP_I16_I16_I16 : VOPProfile <[i32, i32, i32, untyped]>;
1067 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
1068 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
1069 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
1070 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
1071 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
1072 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
1073 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
1074 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
1075 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
1077 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
1078 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
1079 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
1080 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
1081 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
1082 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
1083 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
1084 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
1085 let Src0RC32 = VCSrc_32;
1088 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
1089 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
1090 let Asm64 = "$dst, $src0_modifiers, $src1";
1093 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
1094 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
1095 let Asm64 = "$dst, $src0_modifiers, $src1";
1098 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
1099 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
1100 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
1101 def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> {
1102 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VCCReg:$src2);
1103 let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
1104 let Asm64 = "$dst, $src0, $src1, $src2";
1107 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
1108 def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {
1109 field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
1110 field string Asm = "$dst, $src0, $vsrc1, $src2";
1112 def VOP_MAC : VOPProfile <[f32, f32, f32, f32]> {
1113 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);
1114 let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3,
1116 let Asm32 = getAsm32<2>.ret;
1117 let Asm64 = getAsm64<2, HasModifiers>.ret;
1119 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
1120 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
1121 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
1124 class VOP <string opName> {
1125 string OpName = opName;
1128 class VOP2_REV <string revOp, bit isOrig> {
1129 string RevOp = revOp;
1130 bit IsOrig = isOrig;
1133 class AtomicNoRet <string noRetOp, bit isRet> {
1134 string NoRetOp = noRetOp;
1138 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1139 VOP1Common <outs, ins, "", pattern>,
1141 SIMCInstr <opName#"_e32", SISubtarget.NONE>,
1142 MnemonicAlias<opName#"_e32", opName> {
1144 let isCodeGenOnly = 1;
1150 class VOP1_Real_si <string opName, vop1 op, dag outs, dag ins, string asm> :
1151 VOP1<op.SI, outs, ins, asm, []>,
1152 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1153 let AssemblerPredicate = SIAssemblerPredicate;
1156 class VOP1_Real_vi <string opName, vop1 op, dag outs, dag ins, string asm> :
1157 VOP1<op.VI, outs, ins, asm, []>,
1158 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1159 let AssemblerPredicates = [isVI];
1162 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
1164 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
1166 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
1168 def _vi : VOP1_Real_vi <opName, op, outs, ins, asm>;
1171 multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
1173 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
1175 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
1178 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1179 VOP2Common <outs, ins, "", pattern>,
1181 SIMCInstr<opName#"_e32", SISubtarget.NONE>,
1182 MnemonicAlias<opName#"_e32", opName> {
1184 let isCodeGenOnly = 1;
1187 class VOP2_Real_si <string opName, vop2 op, dag outs, dag ins, string asm> :
1188 VOP2 <op.SI, outs, ins, opName#asm, []>,
1189 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1190 let AssemblerPredicates = [isSICI];
1193 class VOP2_Real_vi <string opName, vop2 op, dag outs, dag ins, string asm> :
1194 VOP2 <op.VI, outs, ins, opName#asm, []>,
1195 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1196 let AssemblerPredicates = [isVI];
1199 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
1200 string opName, string revOp> {
1201 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
1202 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
1204 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
1207 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
1208 string opName, string revOp> {
1209 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
1210 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
1212 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
1214 def _vi : VOP2_Real_vi <opName, op, outs, ins, asm>;
1218 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
1220 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
1221 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
1222 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0);
1223 bits<2> omod = !if(HasModifiers, ?, 0);
1224 bits<1> clamp = !if(HasModifiers, ?, 0);
1225 bits<9> src1 = !if(HasSrc1, ?, 0);
1226 bits<9> src2 = !if(HasSrc2, ?, 0);
1229 class VOP3DisableModFields <bit HasSrc0Mods,
1230 bit HasSrc1Mods = 0,
1231 bit HasSrc2Mods = 0,
1232 bit HasOutputMods = 0> {
1233 bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0);
1234 bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0);
1235 bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0);
1236 bits<2> omod = !if(HasOutputMods, ?, 0);
1237 bits<1> clamp = !if(HasOutputMods, ?, 0);
1240 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1241 VOP3Common <outs, ins, "", pattern>,
1243 SIMCInstr<opName#"_e64", SISubtarget.NONE>,
1244 MnemonicAlias<opName#"_e64", opName> {
1246 let isCodeGenOnly = 1;
1249 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1250 VOP3Common <outs, ins, asm, []>,
1252 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1253 let AssemblerPredicates = [isSICI];
1256 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1257 VOP3Common <outs, ins, asm, []>,
1259 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1260 let AssemblerPredicates = [isVI];
1263 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1264 VOP3Common <outs, ins, asm, []>,
1266 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1267 let AssemblerPredicates = [isSICI];
1270 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1271 VOP3Common <outs, ins, asm, []>,
1273 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1274 let AssemblerPredicates = [isVI];
1277 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
1278 string opName, int NumSrcArgs, bit HasMods = 1> {
1280 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1282 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1283 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1284 !if(!eq(NumSrcArgs, 2), 0, 1),
1286 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1287 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1288 !if(!eq(NumSrcArgs, 2), 0, 1),
1292 // VOP3_m without source modifiers
1293 multiclass VOP3_m_nomods <vop op, dag outs, dag ins, string asm, list<dag> pattern,
1294 string opName, int NumSrcArgs, bit HasMods = 1> {
1296 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1298 let src0_modifiers = 0,
1303 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
1304 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
1308 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
1309 list<dag> pattern, string opName, bit HasMods = 1> {
1311 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1313 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1314 VOP3DisableFields<0, 0, HasMods>;
1316 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1317 VOP3DisableFields<0, 0, HasMods>;
1320 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
1321 list<dag> pattern, string opName, bit HasMods = 1> {
1323 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1325 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1326 VOP3DisableFields<0, 0, HasMods>;
1327 // No VI instruction. This class is for SI only.
1330 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
1331 list<dag> pattern, string opName, string revOp,
1332 bit HasMods = 1, bit UseFullOp = 0> {
1334 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1335 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1337 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1338 VOP3DisableFields<1, 0, HasMods>;
1340 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1341 VOP3DisableFields<1, 0, HasMods>;
1344 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
1345 list<dag> pattern, string opName, string revOp,
1346 bit HasMods = 1, bit UseFullOp = 0> {
1348 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1349 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1351 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1352 VOP3DisableFields<1, 0, HasMods>;
1354 // No VI instruction. This class is for SI only.
1357 // XXX - Is v_div_scale_{f32|f64} only available in vop3b without
1358 // option of implicit vcc use?
1359 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
1360 list<dag> pattern, string opName, string revOp,
1361 bit HasMods = 1, bit UseFullOp = 0> {
1362 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1363 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1365 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
1366 // can write it into any SGPR. We currently don't use the carry out,
1367 // so for now hardcode it to VCC as well.
1368 let sdst = SIOperand.VCC, Defs = [VCC] in {
1369 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1370 VOP3DisableFields<1, 0, HasMods>;
1372 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1373 VOP3DisableFields<1, 0, HasMods>;
1374 } // End sdst = SIOperand.VCC, Defs = [VCC]
1377 multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
1378 list<dag> pattern, string opName, string revOp,
1379 bit HasMods = 1, bit UseFullOp = 0> {
1380 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1383 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1384 VOP3DisableFields<1, 1, HasMods>;
1386 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1387 VOP3DisableFields<1, 1, HasMods>;
1390 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1391 list<dag> pattern, string opName,
1392 bit HasMods, bit defExec, string revOp> {
1394 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1395 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1397 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1398 VOP3DisableFields<1, 0, HasMods> {
1399 let Defs = !if(defExec, [EXEC], []);
1402 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1403 VOP3DisableFields<1, 0, HasMods> {
1404 let Defs = !if(defExec, [EXEC], []);
1408 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1409 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1410 string asm, list<dag> pattern = []> {
1411 let isPseudo = 1, isCodeGenOnly = 1 in {
1412 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1413 SIMCInstr<opName, SISubtarget.NONE>;
1416 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1417 SIMCInstr <opName, SISubtarget.SI> {
1418 let AssemblerPredicates = [isSICI];
1421 def _vi : VOP3Common <outs, ins, asm, []>,
1423 VOP3DisableFields <1, 0, 0>,
1424 SIMCInstr <opName, SISubtarget.VI> {
1425 let AssemblerPredicates = [isVI];
1429 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1430 dag ins32, string asm32, list<dag> pat32,
1431 dag ins64, string asm64, list<dag> pat64,
1434 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1436 defm _e64 : VOP3_1_m <op, outs, ins64, opName#asm64, pat64, opName, HasMods>;
1439 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1440 SDPatternOperator node = null_frag> : VOP1_Helper <
1442 P.Ins32, P.Asm32, [],
1445 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1446 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1447 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1451 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1452 SDPatternOperator node = null_frag> {
1454 defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>;
1456 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1458 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1459 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1460 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1461 opName, P.HasModifiers>;
1464 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1465 dag ins32, string asm32, list<dag> pat32,
1466 dag ins64, string asm64, list<dag> pat64,
1467 string revOp, bit HasMods> {
1468 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1470 defm _e64 : VOP3_2_m <op,
1471 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1475 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1476 SDPatternOperator node = null_frag,
1477 string revOp = opName> : VOP2_Helper <
1479 P.Ins32, P.Asm32, [],
1483 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1484 i1:$clamp, i32:$omod)),
1485 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1486 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1487 revOp, P.HasModifiers
1490 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1491 SDPatternOperator node = null_frag,
1492 string revOp = opName> {
1493 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1495 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1498 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1499 i1:$clamp, i32:$omod)),
1500 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1501 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1502 opName, revOp, P.HasModifiers>;
1505 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1506 dag ins32, string asm32, list<dag> pat32,
1507 dag ins64, string asm64, list<dag> pat64,
1508 string revOp, bit HasMods> {
1510 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1512 defm _e64 : VOP3b_2_m <op,
1513 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1517 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1518 SDPatternOperator node = null_frag,
1519 string revOp = opName> : VOP2b_Helper <
1521 P.Ins32, P.Asm32, [],
1525 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1526 i1:$clamp, i32:$omod)),
1527 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1528 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1529 revOp, P.HasModifiers
1532 // A VOP2 instruction that is VOP3-only on VI.
1533 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1534 dag ins32, string asm32, list<dag> pat32,
1535 dag ins64, string asm64, list<dag> pat64,
1536 string revOp, bit HasMods> {
1537 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1539 defm _e64 : VOP3_2_m <op, outs, ins64, opName#asm64, pat64, opName,
1543 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1544 SDPatternOperator node = null_frag,
1545 string revOp = opName>
1548 P.Ins32, P.Asm32, [],
1552 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1553 i1:$clamp, i32:$omod)),
1554 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1555 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1556 revOp, P.HasModifiers
1559 multiclass VOP2MADK <vop2 op, string opName, list<dag> pattern = []> {
1561 def "" : VOP2_Pseudo <VOP_MADK.Outs, VOP_MADK.Ins, pattern, opName>;
1563 let isCodeGenOnly = 0 in {
1564 def _si : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1565 !strconcat(opName, VOP_MADK.Asm), []>,
1566 SIMCInstr <opName#"_e32", SISubtarget.SI>,
1567 VOP2_MADKe <op.SI> {
1568 let AssemblerPredicates = [isSICI];
1571 def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1572 !strconcat(opName, VOP_MADK.Asm), []>,
1573 SIMCInstr <opName#"_e32", SISubtarget.VI>,
1574 VOP2_MADKe <op.VI> {
1575 let AssemblerPredicates = [isVI];
1577 } // End isCodeGenOnly = 0
1580 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1581 VOPCCommon <ins, "", pattern>,
1583 SIMCInstr<opName#"_e32", SISubtarget.NONE>,
1584 MnemonicAlias<opName#"_e32", opName> {
1586 let isCodeGenOnly = 1;
1589 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1590 string opName, bit DefExec, string revOpName = ""> {
1591 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1593 def _si : VOPC<op.SI, ins, asm, []>,
1594 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1595 let Defs = !if(DefExec, [EXEC], []);
1596 let hasSideEffects = DefExec;
1599 def _vi : VOPC<op.VI, ins, asm, []>,
1600 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1601 let Defs = !if(DefExec, [EXEC], []);
1602 let hasSideEffects = DefExec;
1606 multiclass VOPC_Helper <vopc op, string opName,
1607 dag ins32, string asm32, list<dag> pat32,
1608 dag out64, dag ins64, string asm64, list<dag> pat64,
1609 bit HasMods, bit DefExec, string revOp> {
1610 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1612 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1613 opName, HasMods, DefExec, revOp>;
1616 // Special case for class instructions which only have modifiers on
1617 // the 1st source operand.
1618 multiclass VOPC_Class_Helper <vopc op, string opName,
1619 dag ins32, string asm32, list<dag> pat32,
1620 dag out64, dag ins64, string asm64, list<dag> pat64,
1621 bit HasMods, bit DefExec, string revOp> {
1622 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1624 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1625 opName, HasMods, DefExec, revOp>,
1626 VOP3DisableModFields<1, 0, 0>;
1629 multiclass VOPCInst <vopc op, string opName,
1630 VOPProfile P, PatLeaf cond = COND_NULL,
1631 string revOp = opName,
1632 bit DefExec = 0> : VOPC_Helper <
1634 P.Ins32, P.Asm32, [],
1635 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1638 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1639 i1:$clamp, i32:$omod)),
1640 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1642 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1643 P.HasModifiers, DefExec, revOp
1646 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1647 bit DefExec = 0> : VOPC_Class_Helper <
1649 P.Ins32, P.Asm32, [],
1650 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1653 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1654 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1655 P.HasModifiers, DefExec, opName
1659 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1660 VOPCInst <op, opName, VOP_F32_F32_F32, cond, revOp>;
1662 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1663 VOPCInst <op, opName, VOP_F64_F64_F64, cond, revOp>;
1665 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1666 VOPCInst <op, opName, VOP_I32_I32_I32, cond, revOp>;
1668 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1669 VOPCInst <op, opName, VOP_I64_I64_I64, cond, revOp>;
1672 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1673 PatLeaf cond = COND_NULL,
1675 : VOPCInst <op, opName, P, cond, revOp, 1>;
1677 multiclass VOPCX_F32 <vopc op, string opName, string revOp = opName> :
1678 VOPCX <op, opName, VOP_F32_F32_F32, COND_NULL, revOp>;
1680 multiclass VOPCX_F64 <vopc op, string opName, string revOp = opName> :
1681 VOPCX <op, opName, VOP_F64_F64_F64, COND_NULL, revOp>;
1683 multiclass VOPCX_I32 <vopc op, string opName, string revOp = opName> :
1684 VOPCX <op, opName, VOP_I32_I32_I32, COND_NULL, revOp>;
1686 multiclass VOPCX_I64 <vopc op, string opName, string revOp = opName> :
1687 VOPCX <op, opName, VOP_I64_I64_I64, COND_NULL, revOp>;
1689 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1690 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1691 op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods
1694 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1695 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1697 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1698 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1700 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1701 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1703 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1704 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1706 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1707 SDPatternOperator node = null_frag> : VOP3_Helper <
1708 op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64,
1709 !if(!eq(P.NumSrcArgs, 3),
1712 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1713 i1:$clamp, i32:$omod)),
1714 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1715 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1716 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1718 !if(!eq(P.NumSrcArgs, 2),
1721 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1722 i1:$clamp, i32:$omod)),
1723 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1724 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1725 /* P.NumSrcArgs == 1 */,
1728 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1729 i1:$clamp, i32:$omod))))],
1730 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1731 P.NumSrcArgs, P.HasModifiers
1734 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1735 // only VOP instruction that implicitly reads VCC.
1736 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1738 SDPatternOperator node = null_frag> : VOP3_Helper <
1740 (outs P.DstRC.RegClass:$dst),
1741 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1742 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1743 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1746 "$dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1748 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1749 i1:$clamp, i32:$omod)),
1750 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1751 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1756 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1757 string opName, list<dag> pattern> :
1759 op, (outs vrc:$vdst, SReg_64:$sdst),
1760 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1761 InputModsNoDefault:$src1_modifiers, arc:$src1,
1762 InputModsNoDefault:$src2_modifiers, arc:$src2,
1763 ClampMod:$clamp, omod:$omod),
1764 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1765 opName, opName, 1, 1
1768 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1769 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1771 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1772 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1775 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1776 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1777 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1778 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1779 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1780 i32:$src1_modifiers, P.Src1VT:$src1,
1781 i32:$src2_modifiers, P.Src2VT:$src2,
1785 //===----------------------------------------------------------------------===//
1786 // Interpolation opcodes
1787 //===----------------------------------------------------------------------===//
1789 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1790 VINTRPCommon <outs, ins, "", pattern>,
1791 SIMCInstr<opName, SISubtarget.NONE> {
1793 let isCodeGenOnly = 1;
1796 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1798 VINTRPCommon <outs, ins, asm, []>,
1800 SIMCInstr<opName, SISubtarget.SI>;
1802 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1804 VINTRPCommon <outs, ins, asm, []>,
1806 SIMCInstr<opName, SISubtarget.VI>;
1808 multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
1809 list<dag> pattern = []> {
1810 def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
1812 def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>;
1814 def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
1817 //===----------------------------------------------------------------------===//
1818 // Vector I/O classes
1819 //===----------------------------------------------------------------------===//
1821 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1822 DS <outs, ins, "", pattern>,
1823 SIMCInstr <opName, SISubtarget.NONE> {
1825 let isCodeGenOnly = 1;
1828 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1829 DS <outs, ins, asm, []>,
1831 SIMCInstr <opName, SISubtarget.SI> {
1832 let isCodeGenOnly = 0;
1835 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1836 DS <outs, ins, asm, []>,
1838 SIMCInstr <opName, SISubtarget.VI>;
1840 class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1841 DS_Real_si <op,opName, outs, ins, asm> {
1843 // Single load interpret the 2 i8imm operands as a single i16 offset.
1845 let offset0 = offset{7-0};
1846 let offset1 = offset{15-8};
1847 let isCodeGenOnly = 0;
1850 class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1851 DS_Real_vi <op, opName, outs, ins, asm> {
1853 // Single load interpret the 2 i8imm operands as a single i16 offset.
1855 let offset0 = offset{7-0};
1856 let offset1 = offset{15-8};
1859 multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc,
1860 dag outs = (outs rc:$vdst),
1861 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds),
1862 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
1864 def "" : DS_Pseudo <opName, outs, ins, []>;
1866 let data0 = 0, data1 = 0 in {
1867 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1868 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1872 multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc,
1873 dag outs = (outs rc:$vdst),
1874 dag ins = (ins VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1876 string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> {
1878 def "" : DS_Pseudo <opName, outs, ins, []>;
1880 let data0 = 0, data1 = 0, AsmMatchConverter = "cvtDSOffset01" in {
1881 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1882 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1886 multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc,
1888 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds),
1889 string asm = opName#" $addr, $data0"#"$offset$gds"> {
1891 def "" : DS_Pseudo <opName, outs, ins, []>,
1892 AtomicNoRet<opName, 0>;
1894 let data1 = 0, vdst = 0 in {
1895 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1896 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1900 multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc,
1902 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1903 ds_offset0:$offset0, ds_offset1:$offset1, gds01:$gds),
1904 string asm = opName#" $addr, $data0, $data1"#"$offset0"#"$offset1"#"$gds"> {
1906 def "" : DS_Pseudo <opName, outs, ins, []>;
1908 let vdst = 0, AsmMatchConverter = "cvtDSOffset01" in {
1909 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1910 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1914 multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc,
1915 string noRetOp = "",
1916 dag outs = (outs rc:$vdst),
1917 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds),
1918 string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> {
1920 def "" : DS_Pseudo <opName, outs, ins, []>,
1921 AtomicNoRet<noRetOp, 1>;
1924 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1925 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1929 multiclass DS_1A2D_RET_m <bits<8> op, string opName, RegisterClass rc,
1930 string noRetOp = "", dag ins,
1931 dag outs = (outs rc:$vdst),
1932 string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"#"$gds"> {
1934 def "" : DS_Pseudo <opName, outs, ins, []>,
1935 AtomicNoRet<noRetOp, 1>;
1937 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1938 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1941 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1942 string noRetOp = "", RegisterClass src = rc> :
1943 DS_1A2D_RET_m <op, asm, rc, noRetOp,
1944 (ins VGPR_32:$addr, src:$data0, src:$data1,
1945 ds_offset:$offset, gds:$gds)
1948 multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc,
1949 string noRetOp = opName,
1951 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1952 ds_offset:$offset, gds:$gds),
1953 string asm = opName#" $addr, $data0, $data1"#"$offset"#"$gds"> {
1955 def "" : DS_Pseudo <opName, outs, ins, []>,
1956 AtomicNoRet<noRetOp, 0>;
1959 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1960 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1964 multiclass DS_0A_RET <bits<8> op, string opName,
1965 dag outs = (outs VGPR_32:$vdst),
1966 dag ins = (ins ds_offset:$offset, gds:$gds),
1967 string asm = opName#" $vdst"#"$offset"#"$gds"> {
1969 let mayLoad = 1, mayStore = 1 in {
1970 def "" : DS_Pseudo <opName, outs, ins, []>;
1972 let addr = 0, data0 = 0, data1 = 0 in {
1973 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1974 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1975 } // end addr = 0, data0 = 0, data1 = 0
1976 } // end mayLoad = 1, mayStore = 1
1979 multiclass DS_1A_RET_GDS <bits<8> op, string opName,
1980 dag outs = (outs VGPR_32:$vdst),
1981 dag ins = (ins VGPR_32:$addr, ds_offset_gds:$offset),
1982 string asm = opName#" $vdst, $addr"#"$offset gds"> {
1984 def "" : DS_Pseudo <opName, outs, ins, []>;
1986 let data0 = 0, data1 = 0, gds = 1 in {
1987 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1988 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1989 } // end data0 = 0, data1 = 0, gds = 1
1992 multiclass DS_1A_GDS <bits<8> op, string opName,
1994 dag ins = (ins VGPR_32:$addr),
1995 string asm = opName#" $addr gds"> {
1997 def "" : DS_Pseudo <opName, outs, ins, []>;
1999 let vdst = 0, data0 = 0, data1 = 0, offset0 = 0, offset1 = 0, gds = 1 in {
2000 def _si : DS_Real_si <op, opName, outs, ins, asm>;
2001 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
2002 } // end vdst = 0, data = 0, data1 = 0, gds = 1
2005 multiclass DS_1A <bits<8> op, string opName,
2007 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds),
2008 string asm = opName#" $addr"#"$offset"#"$gds"> {
2010 let mayLoad = 1, mayStore = 1 in {
2011 def "" : DS_Pseudo <opName, outs, ins, []>;
2013 let vdst = 0, data0 = 0, data1 = 0 in {
2014 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2015 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2016 } // let vdst = 0, data0 = 0, data1 = 0
2017 } // end mayLoad = 1, mayStore = 1
2020 //===----------------------------------------------------------------------===//
2022 //===----------------------------------------------------------------------===//
2024 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2025 MTBUF <outs, ins, "", pattern>,
2026 SIMCInstr<opName, SISubtarget.NONE> {
2028 let isCodeGenOnly = 1;
2031 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
2033 MTBUF <outs, ins, asm, []>,
2035 SIMCInstr<opName, SISubtarget.SI>;
2037 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
2038 MTBUF <outs, ins, asm, []>,
2040 SIMCInstr <opName, SISubtarget.VI>;
2042 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
2043 list<dag> pattern> {
2045 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
2047 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
2049 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
2053 let mayStore = 1, mayLoad = 0 in {
2055 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
2056 RegisterClass regClass> : MTBUF_m <
2058 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
2059 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
2060 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2061 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
2062 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2065 } // mayStore = 1, mayLoad = 0
2067 let mayLoad = 1, mayStore = 0 in {
2069 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
2070 RegisterClass regClass> : MTBUF_m <
2071 op, opName, (outs regClass:$dst),
2072 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
2073 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
2074 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2075 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
2076 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2079 } // mayLoad = 1, mayStore = 0
2081 //===----------------------------------------------------------------------===//
2083 //===----------------------------------------------------------------------===//
2085 class mubuf <bits<7> si, bits<7> vi = si> {
2086 field bits<7> SI = si;
2087 field bits<7> VI = vi;
2090 let isCodeGenOnly = 0 in {
2092 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
2093 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
2097 } // End let isCodeGenOnly = 0
2099 class MUBUF_vi <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
2100 MUBUF <outs, ins, asm, pattern>, MUBUFe_vi <op> {
2104 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
2105 bit IsAddr64 = is_addr64;
2106 string OpName = NAME # suffix;
2109 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2110 MUBUF <outs, ins, "", pattern>,
2111 SIMCInstr<opName, SISubtarget.NONE> {
2113 let isCodeGenOnly = 1;
2115 // dummy fields, so that we can use let statements around multiclasses
2125 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
2127 MUBUF <outs, ins, asm, []>,
2129 SIMCInstr<opName, SISubtarget.SI> {
2133 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
2135 MUBUF <outs, ins, asm, []>,
2137 SIMCInstr<opName, SISubtarget.VI> {
2141 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
2142 list<dag> pattern> {
2144 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2145 MUBUFAddr64Table <0>;
2147 let addr64 = 0, isCodeGenOnly = 0 in {
2148 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2151 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2154 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
2155 dag ins, string asm, list<dag> pattern> {
2157 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2158 MUBUFAddr64Table <1>;
2160 let addr64 = 1, isCodeGenOnly = 0 in {
2161 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2164 // There is no VI version. If the pseudo is selected, it should be lowered
2165 // for VI appropriately.
2168 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
2169 string asm, list<dag> pattern, bit is_return> {
2171 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2172 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
2173 AtomicNoRet<NAME#"_OFFSET", is_return>;
2175 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
2177 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2180 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2184 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
2185 string asm, list<dag> pattern, bit is_return> {
2187 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2188 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
2189 AtomicNoRet<NAME#"_ADDR64", is_return>;
2191 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
2192 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2195 // There is no VI version. If the pseudo is selected, it should be lowered
2196 // for VI appropriately.
2199 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
2200 ValueType vt, SDPatternOperator atomic> {
2202 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
2204 // No return variants
2207 defm _ADDR64 : MUBUFAtomicAddr64_m <
2208 op, name#"_addr64", (outs),
2209 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
2210 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2211 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
2214 defm _OFFSET : MUBUFAtomicOffset_m <
2215 op, name#"_offset", (outs),
2216 (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset,
2218 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
2222 // Variant that return values
2223 let glc = 1, Constraints = "$vdata = $vdata_in",
2224 DisableEncoding = "$vdata_in" in {
2226 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
2227 op, name#"_rtn_addr64", (outs rc:$vdata),
2228 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
2229 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2230 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
2232 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
2233 i16:$offset, i1:$slc), vt:$vdata_in))], 1
2236 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
2237 op, name#"_rtn_offset", (outs rc:$vdata),
2238 (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset,
2239 mbuf_offset:$offset, slc:$slc),
2240 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
2242 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
2243 i1:$slc), vt:$vdata_in))], 1
2248 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
2251 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
2252 ValueType load_vt = i32,
2253 SDPatternOperator ld = null_frag> {
2255 let mayLoad = 1, mayStore = 0 in {
2256 let offen = 0, idxen = 0, vaddr = 0 in {
2257 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
2258 (ins SReg_128:$srsrc, SCSrc_32:$soffset,
2259 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2260 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2261 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
2262 i32:$soffset, i16:$offset,
2263 i1:$glc, i1:$slc, i1:$tfe)))]>;
2266 let offen = 1, idxen = 0 in {
2267 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
2268 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2269 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
2271 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2274 let offen = 0, idxen = 1 in {
2275 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
2276 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2277 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2278 slc:$slc, tfe:$tfe),
2279 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2282 let offen = 1, idxen = 1 in {
2283 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
2284 (ins VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2285 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2286 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2289 let offen = 0, idxen = 0 in {
2290 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
2291 (ins VReg_64:$vaddr, SReg_128:$srsrc,
2292 SCSrc_32:$soffset, mbuf_offset:$offset,
2293 glc:$glc, slc:$slc, tfe:$tfe),
2294 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#
2295 "$glc"#"$slc"#"$tfe",
2296 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
2297 i64:$vaddr, i32:$soffset,
2298 i16:$offset, i1:$glc, i1:$slc,
2304 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
2305 ValueType store_vt = i32, SDPatternOperator st = null_frag> {
2306 let mayLoad = 0, mayStore = 1 in {
2307 defm : MUBUF_m <op, name, (outs),
2308 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2309 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
2311 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
2312 "$glc"#"$slc"#"$tfe", []>;
2314 let offen = 0, idxen = 0, vaddr = 0 in {
2315 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
2316 (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset,
2317 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2318 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2319 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
2320 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
2321 } // offen = 0, idxen = 0, vaddr = 0
2323 let offen = 1, idxen = 0 in {
2324 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
2325 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2326 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2327 slc:$slc, tfe:$tfe),
2328 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
2329 "$glc"#"$slc"#"$tfe", []>;
2330 } // end offen = 1, idxen = 0
2332 let offen = 0, idxen = 1 in {
2333 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs),
2334 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2335 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2336 slc:$slc, tfe:$tfe),
2337 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2340 let offen = 1, idxen = 1 in {
2341 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs),
2342 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2343 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2344 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2347 let offen = 0, idxen = 0 in {
2348 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
2349 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc,
2351 mbuf_offset:$offset, glc:$glc, slc:$slc,
2353 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#
2354 "$offset"#"$glc"#"$slc"#"$tfe",
2355 [(st store_vt:$vdata,
2356 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
2357 i32:$soffset, i16:$offset,
2358 i1:$glc, i1:$slc, i1:$tfe))]>;
2360 } // End mayLoad = 0, mayStore = 1
2363 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
2364 FLAT <op, (outs regClass:$vdst),
2365 (ins VReg_64:$addr, glc_flat:$glc, slc_flat:$slc, tfe_flat:$tfe),
2366 asm#" $vdst, $addr"#"$glc"#"$slc"#"$tfe", []> {
2371 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
2372 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr,
2373 glc_flat:$glc, slc_flat:$slc, tfe_flat:$tfe),
2374 name#" $data, $addr"#"$glc"#"$slc"#"$tfe",
2384 multiclass FLAT_ATOMIC <bits<7> op, string name, RegisterClass vdst_rc,
2385 RegisterClass data_rc = vdst_rc> {
2387 let mayLoad = 1, mayStore = 1 in {
2388 def "" : FLAT <op, (outs),
2389 (ins VReg_64:$addr, data_rc:$data, slc_flat_atomic:$slc,
2390 tfe_flat_atomic:$tfe),
2391 name#" $addr, $data"#"$slc"#"$tfe", []>,
2392 AtomicNoRet <NAME, 0> {
2397 def _RTN : FLAT <op, (outs vdst_rc:$vdst),
2398 (ins VReg_64:$addr, data_rc:$data, slc_flat_atomic:$slc,
2399 tfe_flat_atomic:$tfe),
2400 name#" $vdst, $addr, $data glc"#"$slc"#"$tfe", []>,
2401 AtomicNoRet <NAME, 1> {
2407 class MIMG_Mask <string op, int channels> {
2409 int Channels = channels;
2412 class MIMG_NoSampler_Helper <bits<7> op, string asm,
2413 RegisterClass dst_rc,
2414 RegisterClass src_rc> : MIMG <
2416 (outs dst_rc:$vdata),
2417 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2418 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2420 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2421 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
2426 let hasPostISelHook = 1;
2429 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
2430 RegisterClass dst_rc,
2432 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
2433 MIMG_Mask<asm#"_V1", channels>;
2434 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
2435 MIMG_Mask<asm#"_V2", channels>;
2436 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
2437 MIMG_Mask<asm#"_V4", channels>;
2440 multiclass MIMG_NoSampler <bits<7> op, string asm> {
2441 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
2442 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
2443 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
2444 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
2447 class MIMG_Sampler_Helper <bits<7> op, string asm,
2448 RegisterClass dst_rc,
2449 RegisterClass src_rc, int wqm> : MIMG <
2451 (outs dst_rc:$vdata),
2452 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2453 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2454 SReg_256:$srsrc, SReg_128:$ssamp),
2455 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2456 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2460 let hasPostISelHook = 1;
2464 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2465 RegisterClass dst_rc,
2466 int channels, int wqm> {
2467 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2468 MIMG_Mask<asm#"_V1", channels>;
2469 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2470 MIMG_Mask<asm#"_V2", channels>;
2471 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2472 MIMG_Mask<asm#"_V4", channels>;
2473 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2474 MIMG_Mask<asm#"_V8", channels>;
2475 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2476 MIMG_Mask<asm#"_V16", channels>;
2479 multiclass MIMG_Sampler <bits<7> op, string asm> {
2480 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2481 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2482 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2483 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2486 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2487 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2488 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2489 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2490 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2493 class MIMG_Gather_Helper <bits<7> op, string asm,
2494 RegisterClass dst_rc,
2495 RegisterClass src_rc, int wqm> : MIMG <
2497 (outs dst_rc:$vdata),
2498 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2499 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2500 SReg_256:$srsrc, SReg_128:$ssamp),
2501 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2502 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2507 // DMASK was repurposed for GATHER4. 4 components are always
2508 // returned and DMASK works like a swizzle - it selects
2509 // the component to fetch. The only useful DMASK values are
2510 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2511 // (red,red,red,red) etc.) The ISA document doesn't mention
2513 // Therefore, disable all code which updates DMASK by setting these two:
2515 let hasPostISelHook = 0;
2519 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2520 RegisterClass dst_rc,
2521 int channels, int wqm> {
2522 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2523 MIMG_Mask<asm#"_V1", channels>;
2524 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2525 MIMG_Mask<asm#"_V2", channels>;
2526 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2527 MIMG_Mask<asm#"_V4", channels>;
2528 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2529 MIMG_Mask<asm#"_V8", channels>;
2530 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2531 MIMG_Mask<asm#"_V16", channels>;
2534 multiclass MIMG_Gather <bits<7> op, string asm> {
2535 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2536 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2537 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2538 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2541 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2542 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2543 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2544 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2545 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2548 //===----------------------------------------------------------------------===//
2549 // Vector instruction mappings
2550 //===----------------------------------------------------------------------===//
2552 // Maps an opcode in e32 form to its e64 equivalent
2553 def getVOPe64 : InstrMapping {
2554 let FilterClass = "VOP";
2555 let RowFields = ["OpName"];
2556 let ColFields = ["Size"];
2558 let ValueCols = [["8"]];
2561 // Maps an opcode in e64 form to its e32 equivalent
2562 def getVOPe32 : InstrMapping {
2563 let FilterClass = "VOP";
2564 let RowFields = ["OpName"];
2565 let ColFields = ["Size"];
2567 let ValueCols = [["4"]];
2570 def getMaskedMIMGOp : InstrMapping {
2571 let FilterClass = "MIMG_Mask";
2572 let RowFields = ["Op"];
2573 let ColFields = ["Channels"];
2575 let ValueCols = [["1"], ["2"], ["3"] ];
2578 // Maps an commuted opcode to its original version
2579 def getCommuteOrig : InstrMapping {
2580 let FilterClass = "VOP2_REV";
2581 let RowFields = ["RevOp"];
2582 let ColFields = ["IsOrig"];
2584 let ValueCols = [["1"]];
2587 // Maps an original opcode to its commuted version
2588 def getCommuteRev : InstrMapping {
2589 let FilterClass = "VOP2_REV";
2590 let RowFields = ["RevOp"];
2591 let ColFields = ["IsOrig"];
2593 let ValueCols = [["0"]];
2596 def getCommuteCmpOrig : InstrMapping {
2597 let FilterClass = "VOP2_REV";
2598 let RowFields = ["RevOp"];
2599 let ColFields = ["IsOrig"];
2601 let ValueCols = [["1"]];
2604 // Maps an original opcode to its commuted version
2605 def getCommuteCmpRev : InstrMapping {
2606 let FilterClass = "VOP2_REV";
2607 let RowFields = ["RevOp"];
2608 let ColFields = ["IsOrig"];
2610 let ValueCols = [["0"]];
2614 def getMCOpcodeGen : InstrMapping {
2615 let FilterClass = "SIMCInstr";
2616 let RowFields = ["PseudoInstr"];
2617 let ColFields = ["Subtarget"];
2618 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2619 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2622 def getAddr64Inst : InstrMapping {
2623 let FilterClass = "MUBUFAddr64Table";
2624 let RowFields = ["OpName"];
2625 let ColFields = ["IsAddr64"];
2627 let ValueCols = [["1"]];
2630 // Maps an atomic opcode to its version with a return value.
2631 def getAtomicRetOp : InstrMapping {
2632 let FilterClass = "AtomicNoRet";
2633 let RowFields = ["NoRetOp"];
2634 let ColFields = ["IsRet"];
2636 let ValueCols = [["1"]];
2639 // Maps an atomic opcode to its returnless version.
2640 def getAtomicNoRetOp : InstrMapping {
2641 let FilterClass = "AtomicNoRet";
2642 let RowFields = ["NoRetOp"];
2643 let ColFields = ["IsRet"];
2645 let ValueCols = [["0"]];
2648 include "SIInstructions.td"
2649 include "CIInstructions.td"
2650 include "VIInstructions.td"