1 //===-- SIInstructions.td - SI Instruction Defintions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This file was originally auto-generated from a GPU register header file and
10 // all the instruction definitions were originally commented out. Instructions
11 // that are not yet supported remain commented out.
12 //===----------------------------------------------------------------------===//
19 def INTERP : InterpSlots;
21 def InterpSlot : Operand<i32> {
22 let PrintMethod = "printInterpSlot";
25 def SendMsgImm : Operand<i32> {
26 let PrintMethod = "printSendMsg";
29 def isGCN : Predicate<"Subtarget->getGeneration() "
30 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">,
31 AssemblerPredicate<"FeatureGCN">;
32 def isSI : Predicate<"Subtarget->getGeneration() "
33 "== AMDGPUSubtarget::SOUTHERN_ISLANDS">,
34 AssemblerPredicate<"FeatureSouthernIslands">;
37 def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
38 def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
40 def SWaitMatchClass : AsmOperandClass {
41 let Name = "SWaitCnt";
42 let RenderMethod = "addImmOperands";
43 let ParserMethod = "parseSWaitCntOps";
46 def WAIT_FLAG : InstFlag<"printWaitFlag"> {
47 let ParserMatchClass = SWaitMatchClass;
50 let SubtargetPredicate = isGCN in {
52 //===----------------------------------------------------------------------===//
54 //===----------------------------------------------------------------------===//
58 //===----------------------------------------------------------------------===//
60 //===----------------------------------------------------------------------===//
64 // We are using the SGPR_32 and not the SReg_32 register class for 32-bit
65 // SMRD instructions, because the SGPR_32 register class does not include M0
66 // and writing to M0 from an SMRD instruction will hang the GPU.
67 defm S_LOAD_DWORD : SMRD_Helper <smrd<0x00>, "s_load_dword", SReg_64, SGPR_32>;
68 defm S_LOAD_DWORDX2 : SMRD_Helper <smrd<0x01>, "s_load_dwordx2", SReg_64, SReg_64>;
69 defm S_LOAD_DWORDX4 : SMRD_Helper <smrd<0x02>, "s_load_dwordx4", SReg_64, SReg_128>;
70 defm S_LOAD_DWORDX8 : SMRD_Helper <smrd<0x03>, "s_load_dwordx8", SReg_64, SReg_256>;
71 defm S_LOAD_DWORDX16 : SMRD_Helper <smrd<0x04>, "s_load_dwordx16", SReg_64, SReg_512>;
73 defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
74 smrd<0x08>, "s_buffer_load_dword", SReg_128, SGPR_32
77 defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <
78 smrd<0x09>, "s_buffer_load_dwordx2", SReg_128, SReg_64
81 defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper <
82 smrd<0x0a>, "s_buffer_load_dwordx4", SReg_128, SReg_128
85 defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper <
86 smrd<0x0b>, "s_buffer_load_dwordx8", SReg_128, SReg_256
89 defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
90 smrd<0x0c>, "s_buffer_load_dwordx16", SReg_128, SReg_512
95 //def S_MEMTIME : SMRD_ <0x0000001e, "s_memtime", []>;
97 defm S_DCACHE_INV : SMRD_Inval <smrd<0x1f, 0x20>, "s_dcache_inv",
98 int_amdgcn_s_dcache_inv>;
100 //===----------------------------------------------------------------------===//
102 //===----------------------------------------------------------------------===//
104 let isMoveImm = 1 in {
105 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
106 defm S_MOV_B32 : SOP1_32 <sop1<0x03, 0x00>, "s_mov_b32", []>;
107 defm S_MOV_B64 : SOP1_64 <sop1<0x04, 0x01>, "s_mov_b64", []>;
108 } // let isRematerializeable = 1
110 let Uses = [SCC] in {
111 defm S_CMOV_B32 : SOP1_32 <sop1<0x05, 0x02>, "s_cmov_b32", []>;
112 defm S_CMOV_B64 : SOP1_64 <sop1<0x06, 0x03>, "s_cmov_b64", []>;
113 } // End Uses = [SCC]
114 } // End isMoveImm = 1
116 let Defs = [SCC] in {
117 defm S_NOT_B32 : SOP1_32 <sop1<0x07, 0x04>, "s_not_b32",
118 [(set i32:$dst, (not i32:$src0))]
121 defm S_NOT_B64 : SOP1_64 <sop1<0x08, 0x05>, "s_not_b64",
122 [(set i64:$dst, (not i64:$src0))]
124 defm S_WQM_B32 : SOP1_32 <sop1<0x09, 0x06>, "s_wqm_b32", []>;
125 defm S_WQM_B64 : SOP1_64 <sop1<0x0a, 0x07>, "s_wqm_b64", []>;
126 } // End Defs = [SCC]
129 defm S_BREV_B32 : SOP1_32 <sop1<0x0b, 0x08>, "s_brev_b32",
130 [(set i32:$dst, (AMDGPUbrev i32:$src0))]
132 defm S_BREV_B64 : SOP1_64 <sop1<0x0c, 0x09>, "s_brev_b64", []>;
134 let Defs = [SCC] in {
135 defm S_BCNT0_I32_B32 : SOP1_32 <sop1<0x0d, 0x0a>, "s_bcnt0_i32_b32", []>;
136 defm S_BCNT0_I32_B64 : SOP1_32_64 <sop1<0x0e, 0x0b>, "s_bcnt0_i32_b64", []>;
137 defm S_BCNT1_I32_B32 : SOP1_32 <sop1<0x0f, 0x0c>, "s_bcnt1_i32_b32",
138 [(set i32:$dst, (ctpop i32:$src0))]
140 defm S_BCNT1_I32_B64 : SOP1_32_64 <sop1<0x10, 0x0d>, "s_bcnt1_i32_b64", []>;
141 } // End Defs = [SCC]
143 defm S_FF0_I32_B32 : SOP1_32 <sop1<0x11, 0x0e>, "s_ff0_i32_b32", []>;
144 defm S_FF0_I32_B64 : SOP1_32_64 <sop1<0x12, 0x0f>, "s_ff0_i32_b64", []>;
145 defm S_FF1_I32_B32 : SOP1_32 <sop1<0x13, 0x10>, "s_ff1_i32_b32",
146 [(set i32:$dst, (cttz_zero_undef i32:$src0))]
148 defm S_FF1_I32_B64 : SOP1_32_64 <sop1<0x14, 0x11>, "s_ff1_i32_b64", []>;
150 defm S_FLBIT_I32_B32 : SOP1_32 <sop1<0x15, 0x12>, "s_flbit_i32_b32",
151 [(set i32:$dst, (ctlz_zero_undef i32:$src0))]
154 defm S_FLBIT_I32_B64 : SOP1_32_64 <sop1<0x16, 0x13>, "s_flbit_i32_b64", []>;
155 defm S_FLBIT_I32 : SOP1_32 <sop1<0x17, 0x14>, "s_flbit_i32",
156 [(set i32:$dst, (int_AMDGPU_flbit_i32 i32:$src0))]
158 defm S_FLBIT_I32_I64 : SOP1_32_64 <sop1<0x18, 0x15>, "s_flbit_i32_i64", []>;
159 defm S_SEXT_I32_I8 : SOP1_32 <sop1<0x19, 0x16>, "s_sext_i32_i8",
160 [(set i32:$dst, (sext_inreg i32:$src0, i8))]
162 defm S_SEXT_I32_I16 : SOP1_32 <sop1<0x1a, 0x17>, "s_sext_i32_i16",
163 [(set i32:$dst, (sext_inreg i32:$src0, i16))]
166 defm S_BITSET0_B32 : SOP1_32 <sop1<0x1b, 0x18>, "s_bitset0_b32", []>;
167 defm S_BITSET0_B64 : SOP1_64 <sop1<0x1c, 0x19>, "s_bitset0_b64", []>;
168 defm S_BITSET1_B32 : SOP1_32 <sop1<0x1d, 0x1a>, "s_bitset1_b32", []>;
169 defm S_BITSET1_B64 : SOP1_64 <sop1<0x1e, 0x1b>, "s_bitset1_b64", []>;
170 defm S_GETPC_B64 : SOP1_64_0 <sop1<0x1f, 0x1c>, "s_getpc_b64", []>;
171 defm S_SETPC_B64 : SOP1_64 <sop1<0x20, 0x1d>, "s_setpc_b64", []>;
172 defm S_SWAPPC_B64 : SOP1_64 <sop1<0x21, 0x1e>, "s_swappc_b64", []>;
173 defm S_RFE_B64 : SOP1_64 <sop1<0x22, 0x1f>, "s_rfe_b64", []>;
175 let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC] in {
177 defm S_AND_SAVEEXEC_B64 : SOP1_64 <sop1<0x24, 0x20>, "s_and_saveexec_b64", []>;
178 defm S_OR_SAVEEXEC_B64 : SOP1_64 <sop1<0x25, 0x21>, "s_or_saveexec_b64", []>;
179 defm S_XOR_SAVEEXEC_B64 : SOP1_64 <sop1<0x26, 0x22>, "s_xor_saveexec_b64", []>;
180 defm S_ANDN2_SAVEEXEC_B64 : SOP1_64 <sop1<0x27, 0x23>, "s_andn2_saveexec_b64", []>;
181 defm S_ORN2_SAVEEXEC_B64 : SOP1_64 <sop1<0x28, 0x24>, "s_orn2_saveexec_b64", []>;
182 defm S_NAND_SAVEEXEC_B64 : SOP1_64 <sop1<0x29, 0x25>, "s_nand_saveexec_b64", []>;
183 defm S_NOR_SAVEEXEC_B64 : SOP1_64 <sop1<0x2a, 0x26>, "s_nor_saveexec_b64", []>;
184 defm S_XNOR_SAVEEXEC_B64 : SOP1_64 <sop1<0x2b, 0x27>, "s_xnor_saveexec_b64", []>;
186 } // End hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC]
188 defm S_QUADMASK_B32 : SOP1_32 <sop1<0x2c, 0x28>, "s_quadmask_b32", []>;
189 defm S_QUADMASK_B64 : SOP1_64 <sop1<0x2d, 0x29>, "s_quadmask_b64", []>;
190 defm S_MOVRELS_B32 : SOP1_32 <sop1<0x2e, 0x2a>, "s_movrels_b32", []>;
191 defm S_MOVRELS_B64 : SOP1_64 <sop1<0x2f, 0x2b>, "s_movrels_b64", []>;
192 defm S_MOVRELD_B32 : SOP1_32 <sop1<0x30, 0x2c>, "s_movreld_b32", []>;
193 defm S_MOVRELD_B64 : SOP1_64 <sop1<0x31, 0x2d>, "s_movreld_b64", []>;
194 defm S_CBRANCH_JOIN : SOP1_1 <sop1<0x32, 0x2e>, "s_cbranch_join", []>;
195 defm S_MOV_REGRD_B32 : SOP1_32 <sop1<0x33, 0x2f>, "s_mov_regrd_b32", []>;
196 let Defs = [SCC] in {
197 defm S_ABS_I32 : SOP1_32 <sop1<0x34, 0x30>, "s_abs_i32", []>;
198 } // End Defs = [SCC]
199 defm S_MOV_FED_B32 : SOP1_32 <sop1<0x35, 0x31>, "s_mov_fed_b32", []>;
201 //===----------------------------------------------------------------------===//
203 //===----------------------------------------------------------------------===//
205 let Defs = [SCC] in { // Carry out goes to SCC
206 let isCommutable = 1 in {
207 defm S_ADD_U32 : SOP2_32 <sop2<0x00>, "s_add_u32", []>;
208 defm S_ADD_I32 : SOP2_32 <sop2<0x02>, "s_add_i32",
209 [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))]
211 } // End isCommutable = 1
213 defm S_SUB_U32 : SOP2_32 <sop2<0x01>, "s_sub_u32", []>;
214 defm S_SUB_I32 : SOP2_32 <sop2<0x03>, "s_sub_i32",
215 [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))]
218 let Uses = [SCC] in { // Carry in comes from SCC
219 let isCommutable = 1 in {
220 defm S_ADDC_U32 : SOP2_32 <sop2<0x04>, "s_addc_u32",
221 [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
222 } // End isCommutable = 1
224 defm S_SUBB_U32 : SOP2_32 <sop2<0x05>, "s_subb_u32",
225 [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
226 } // End Uses = [SCC]
228 defm S_MIN_I32 : SOP2_32 <sop2<0x06>, "s_min_i32",
229 [(set i32:$dst, (smin i32:$src0, i32:$src1))]
231 defm S_MIN_U32 : SOP2_32 <sop2<0x07>, "s_min_u32",
232 [(set i32:$dst, (umin i32:$src0, i32:$src1))]
234 defm S_MAX_I32 : SOP2_32 <sop2<0x08>, "s_max_i32",
235 [(set i32:$dst, (smax i32:$src0, i32:$src1))]
237 defm S_MAX_U32 : SOP2_32 <sop2<0x09>, "s_max_u32",
238 [(set i32:$dst, (umax i32:$src0, i32:$src1))]
240 } // End Defs = [SCC]
243 let Uses = [SCC] in {
244 defm S_CSELECT_B32 : SOP2_32 <sop2<0x0a>, "s_cselect_b32", []>;
245 defm S_CSELECT_B64 : SOP2_64 <sop2<0x0b>, "s_cselect_b64", []>;
246 } // End Uses = [SCC]
248 let Defs = [SCC] in {
249 defm S_AND_B32 : SOP2_32 <sop2<0x0e, 0x0c>, "s_and_b32",
250 [(set i32:$dst, (and i32:$src0, i32:$src1))]
253 defm S_AND_B64 : SOP2_64 <sop2<0x0f, 0x0d>, "s_and_b64",
254 [(set i64:$dst, (and i64:$src0, i64:$src1))]
257 defm S_OR_B32 : SOP2_32 <sop2<0x10, 0x0e>, "s_or_b32",
258 [(set i32:$dst, (or i32:$src0, i32:$src1))]
261 defm S_OR_B64 : SOP2_64 <sop2<0x11, 0x0f>, "s_or_b64",
262 [(set i64:$dst, (or i64:$src0, i64:$src1))]
265 defm S_XOR_B32 : SOP2_32 <sop2<0x12, 0x10>, "s_xor_b32",
266 [(set i32:$dst, (xor i32:$src0, i32:$src1))]
269 defm S_XOR_B64 : SOP2_64 <sop2<0x13, 0x11>, "s_xor_b64",
270 [(set i64:$dst, (xor i64:$src0, i64:$src1))]
272 defm S_ANDN2_B32 : SOP2_32 <sop2<0x14, 0x12>, "s_andn2_b32", []>;
273 defm S_ANDN2_B64 : SOP2_64 <sop2<0x15, 0x13>, "s_andn2_b64", []>;
274 defm S_ORN2_B32 : SOP2_32 <sop2<0x16, 0x14>, "s_orn2_b32", []>;
275 defm S_ORN2_B64 : SOP2_64 <sop2<0x17, 0x15>, "s_orn2_b64", []>;
276 defm S_NAND_B32 : SOP2_32 <sop2<0x18, 0x16>, "s_nand_b32", []>;
277 defm S_NAND_B64 : SOP2_64 <sop2<0x19, 0x17>, "s_nand_b64", []>;
278 defm S_NOR_B32 : SOP2_32 <sop2<0x1a, 0x18>, "s_nor_b32", []>;
279 defm S_NOR_B64 : SOP2_64 <sop2<0x1b, 0x19>, "s_nor_b64", []>;
280 defm S_XNOR_B32 : SOP2_32 <sop2<0x1c, 0x1a>, "s_xnor_b32", []>;
281 defm S_XNOR_B64 : SOP2_64 <sop2<0x1d, 0x1b>, "s_xnor_b64", []>;
282 } // End Defs = [SCC]
284 // Use added complexity so these patterns are preferred to the VALU patterns.
285 let AddedComplexity = 1 in {
286 let Defs = [SCC] in {
288 defm S_LSHL_B32 : SOP2_32 <sop2<0x1e, 0x1c>, "s_lshl_b32",
289 [(set i32:$dst, (shl i32:$src0, i32:$src1))]
291 defm S_LSHL_B64 : SOP2_64_32 <sop2<0x1f, 0x1d>, "s_lshl_b64",
292 [(set i64:$dst, (shl i64:$src0, i32:$src1))]
294 defm S_LSHR_B32 : SOP2_32 <sop2<0x20, 0x1e>, "s_lshr_b32",
295 [(set i32:$dst, (srl i32:$src0, i32:$src1))]
297 defm S_LSHR_B64 : SOP2_64_32 <sop2<0x21, 0x1f>, "s_lshr_b64",
298 [(set i64:$dst, (srl i64:$src0, i32:$src1))]
300 defm S_ASHR_I32 : SOP2_32 <sop2<0x22, 0x20>, "s_ashr_i32",
301 [(set i32:$dst, (sra i32:$src0, i32:$src1))]
303 defm S_ASHR_I64 : SOP2_64_32 <sop2<0x23, 0x21>, "s_ashr_i64",
304 [(set i64:$dst, (sra i64:$src0, i32:$src1))]
306 } // End Defs = [SCC]
308 defm S_BFM_B32 : SOP2_32 <sop2<0x24, 0x22>, "s_bfm_b32",
309 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))]>;
310 defm S_BFM_B64 : SOP2_64 <sop2<0x25, 0x23>, "s_bfm_b64", []>;
311 defm S_MUL_I32 : SOP2_32 <sop2<0x26, 0x24>, "s_mul_i32",
312 [(set i32:$dst, (mul i32:$src0, i32:$src1))]
315 } // End AddedComplexity = 1
317 let Defs = [SCC] in {
318 defm S_BFE_U32 : SOP2_32 <sop2<0x27, 0x25>, "s_bfe_u32", []>;
319 defm S_BFE_I32 : SOP2_32 <sop2<0x28, 0x26>, "s_bfe_i32", []>;
320 defm S_BFE_U64 : SOP2_64 <sop2<0x29, 0x27>, "s_bfe_u64", []>;
321 defm S_BFE_I64 : SOP2_64_32 <sop2<0x2a, 0x28>, "s_bfe_i64", []>;
322 } // End Defs = [SCC]
325 defm S_CBRANCH_G_FORK : SOP2_m <
326 sop2<0x2b, 0x29>, "s_cbranch_g_fork", (outs),
327 (ins SReg_64:$src0, SReg_64:$src1), "s_cbranch_g_fork $src0, $src1", []
331 let Defs = [SCC] in {
332 defm S_ABSDIFF_I32 : SOP2_32 <sop2<0x2c, 0x2a>, "s_absdiff_i32", []>;
333 } // End Defs = [SCC]
335 //===----------------------------------------------------------------------===//
337 //===----------------------------------------------------------------------===//
339 def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "s_cmp_eq_i32">;
340 def S_CMP_LG_I32 : SOPC_32 <0x00000001, "s_cmp_lg_i32">;
341 def S_CMP_GT_I32 : SOPC_32 <0x00000002, "s_cmp_gt_i32">;
342 def S_CMP_GE_I32 : SOPC_32 <0x00000003, "s_cmp_ge_i32">;
343 def S_CMP_LT_I32 : SOPC_32 <0x00000004, "s_cmp_lt_i32">;
344 def S_CMP_LE_I32 : SOPC_32 <0x00000005, "s_cmp_le_i32">;
345 def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "s_cmp_eq_u32">;
346 def S_CMP_LG_U32 : SOPC_32 <0x00000007, "s_cmp_lg_u32">;
347 def S_CMP_GT_U32 : SOPC_32 <0x00000008, "s_cmp_gt_u32">;
348 def S_CMP_GE_U32 : SOPC_32 <0x00000009, "s_cmp_ge_u32">;
349 def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "s_cmp_lt_u32">;
350 def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "s_cmp_le_u32">;
351 ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "s_bitcmp0_b32", []>;
352 ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "s_bitcmp1_b32", []>;
353 ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "s_bitcmp0_b64", []>;
354 ////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "s_bitcmp1_b64", []>;
355 //def S_SETVSKIP : SOPC_ <0x00000010, "s_setvskip", []>;
357 //===----------------------------------------------------------------------===//
359 //===----------------------------------------------------------------------===//
361 let isReMaterializable = 1, isMoveImm = 1 in {
362 defm S_MOVK_I32 : SOPK_32 <sopk<0x00>, "s_movk_i32", []>;
363 } // End isReMaterializable = 1
364 let Uses = [SCC] in {
365 defm S_CMOVK_I32 : SOPK_32 <sopk<0x02, 0x01>, "s_cmovk_i32", []>;
368 let isCompare = 1 in {
371 This instruction is disabled for now until we can figure out how to teach
372 the instruction selector to correctly use the S_CMP* vs V_CMP*
375 When this instruction is enabled the code generator sometimes produces this
378 SCC = S_CMPK_EQ_I32 SGPR0, imm
380 VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
382 defm S_CMPK_EQ_I32 : SOPK_SCC <sopk<0x03, 0x02>, "s_cmpk_eq_i32",
383 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))]
387 defm S_CMPK_EQ_I32 : SOPK_SCC <sopk<0x03, 0x02>, "s_cmpk_eq_i32", []>;
388 defm S_CMPK_LG_I32 : SOPK_SCC <sopk<0x04, 0x03>, "s_cmpk_lg_i32", []>;
389 defm S_CMPK_GT_I32 : SOPK_SCC <sopk<0x05, 0x04>, "s_cmpk_gt_i32", []>;
390 defm S_CMPK_GE_I32 : SOPK_SCC <sopk<0x06, 0x05>, "s_cmpk_ge_i32", []>;
391 defm S_CMPK_LT_I32 : SOPK_SCC <sopk<0x07, 0x06>, "s_cmpk_lt_i32", []>;
392 defm S_CMPK_LE_I32 : SOPK_SCC <sopk<0x08, 0x07>, "s_cmpk_le_i32", []>;
393 defm S_CMPK_EQ_U32 : SOPK_SCC <sopk<0x09, 0x08>, "s_cmpk_eq_u32", []>;
394 defm S_CMPK_LG_U32 : SOPK_SCC <sopk<0x0a, 0x09>, "s_cmpk_lg_u32", []>;
395 defm S_CMPK_GT_U32 : SOPK_SCC <sopk<0x0b, 0x0a>, "s_cmpk_gt_u32", []>;
396 defm S_CMPK_GE_U32 : SOPK_SCC <sopk<0x0c, 0x0b>, "s_cmpk_ge_u32", []>;
397 defm S_CMPK_LT_U32 : SOPK_SCC <sopk<0x0d, 0x0c>, "s_cmpk_lt_u32", []>;
398 defm S_CMPK_LE_U32 : SOPK_SCC <sopk<0x0e, 0x0d>, "s_cmpk_le_u32", []>;
399 } // End isCompare = 1
401 let Defs = [SCC], isCommutable = 1, DisableEncoding = "$src0",
402 Constraints = "$sdst = $src0" in {
403 defm S_ADDK_I32 : SOPK_32TIE <sopk<0x0f, 0x0e>, "s_addk_i32", []>;
404 defm S_MULK_I32 : SOPK_32TIE <sopk<0x10, 0x0f>, "s_mulk_i32", []>;
407 defm S_CBRANCH_I_FORK : SOPK_m <
408 sopk<0x11, 0x10>, "s_cbranch_i_fork", (outs),
409 (ins SReg_64:$sdst, u16imm:$simm16), " $sdst, $simm16"
411 defm S_GETREG_B32 : SOPK_32 <sopk<0x12, 0x11>, "s_getreg_b32", []>;
412 defm S_SETREG_B32 : SOPK_m <
413 sopk<0x13, 0x12>, "s_setreg_b32", (outs),
414 (ins SReg_32:$sdst, u16imm:$simm16), " $sdst, $simm16"
417 //defm S_GETREG_REGRD_B32 : SOPK_32 <sopk<0x14, 0x13>, "s_getreg_regrd_b32", []>;
418 defm S_SETREG_IMM32_B32 : SOPK_IMM32 <
419 sopk<0x15, 0x14>, "s_setreg_imm32_b32", (outs),
420 (ins i32imm:$imm, u16imm:$simm16), " $imm, $simm16"
423 //===----------------------------------------------------------------------===//
425 //===----------------------------------------------------------------------===//
427 def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">;
429 let isTerminator = 1 in {
431 def S_ENDPGM : SOPP <0x00000001, (ins), "s_endpgm",
438 let isBranch = 1 in {
439 def S_BRANCH : SOPP <
440 0x00000002, (ins sopp_brtarget:$simm16), "s_branch $simm16",
445 let Uses = [SCC] in {
446 def S_CBRANCH_SCC0 : SOPP <
447 0x00000004, (ins sopp_brtarget:$simm16),
448 "s_cbranch_scc0 $simm16"
450 def S_CBRANCH_SCC1 : SOPP <
451 0x00000005, (ins sopp_brtarget:$simm16),
452 "s_cbranch_scc1 $simm16"
454 } // End Uses = [SCC]
456 let Uses = [VCC] in {
457 def S_CBRANCH_VCCZ : SOPP <
458 0x00000006, (ins sopp_brtarget:$simm16),
459 "s_cbranch_vccz $simm16"
461 def S_CBRANCH_VCCNZ : SOPP <
462 0x00000007, (ins sopp_brtarget:$simm16),
463 "s_cbranch_vccnz $simm16"
465 } // End Uses = [VCC]
467 let Uses = [EXEC] in {
468 def S_CBRANCH_EXECZ : SOPP <
469 0x00000008, (ins sopp_brtarget:$simm16),
470 "s_cbranch_execz $simm16"
472 def S_CBRANCH_EXECNZ : SOPP <
473 0x00000009, (ins sopp_brtarget:$simm16),
474 "s_cbranch_execnz $simm16"
476 } // End Uses = [EXEC]
479 } // End isBranch = 1
480 } // End isTerminator = 1
482 let hasSideEffects = 1 in {
483 def S_BARRIER : SOPP <0x0000000a, (ins), "s_barrier",
484 [(int_AMDGPU_barrier_local)]
486 let SchedRW = [WriteBarrier];
490 let isConvergent = 1;
493 def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "s_waitcnt $simm16">;
494 def S_SETHALT : SOPP <0x0000000d, (ins i16imm:$simm16), "s_sethalt $simm16">;
495 def S_SLEEP : SOPP <0x0000000e, (ins i16imm:$simm16), "s_sleep $simm16">;
496 def S_SETPRIO : SOPP <0x0000000f, (ins i16imm:$sim16), "s_setprio $sim16">;
498 let Uses = [EXEC, M0] in {
499 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16), "s_sendmsg $simm16",
500 [(AMDGPUsendmsg (i32 imm:$simm16))]
502 } // End Uses = [EXEC, M0]
504 def S_SENDMSGHALT : SOPP <0x00000011, (ins i16imm:$simm16), "s_sendmsghalt $simm16">;
505 def S_TRAP : SOPP <0x00000012, (ins i16imm:$simm16), "s_trap $simm16">;
506 def S_ICACHE_INV : SOPP <0x00000013, (ins), "s_icache_inv"> {
509 def S_INCPERFLEVEL : SOPP <0x00000014, (ins i16imm:$simm16), "s_incperflevel $simm16">;
510 def S_DECPERFLEVEL : SOPP <0x00000015, (ins i16imm:$simm16), "s_decperflevel $simm16">;
511 def S_TTRACEDATA : SOPP <0x00000016, (ins), "s_ttracedata"> {
514 } // End hasSideEffects
516 //===----------------------------------------------------------------------===//
518 //===----------------------------------------------------------------------===//
520 let isCompare = 1, isCommutable = 1 in {
522 defm V_CMP_F_F32 : VOPC_F32 <vopc<0x0, 0x40>, "v_cmp_f_f32">;
523 defm V_CMP_LT_F32 : VOPC_F32 <vopc<0x1, 0x41>, "v_cmp_lt_f32", COND_OLT, "v_cmp_gt_f32">;
524 defm V_CMP_EQ_F32 : VOPC_F32 <vopc<0x2, 0x42>, "v_cmp_eq_f32", COND_OEQ>;
525 defm V_CMP_LE_F32 : VOPC_F32 <vopc<0x3, 0x43>, "v_cmp_le_f32", COND_OLE, "v_cmp_ge_f32">;
526 defm V_CMP_GT_F32 : VOPC_F32 <vopc<0x4, 0x44>, "v_cmp_gt_f32", COND_OGT>;
527 defm V_CMP_LG_F32 : VOPC_F32 <vopc<0x5, 0x45>, "v_cmp_lg_f32", COND_ONE>;
528 defm V_CMP_GE_F32 : VOPC_F32 <vopc<0x6, 0x46>, "v_cmp_ge_f32", COND_OGE>;
529 defm V_CMP_O_F32 : VOPC_F32 <vopc<0x7, 0x47>, "v_cmp_o_f32", COND_O>;
530 defm V_CMP_U_F32 : VOPC_F32 <vopc<0x8, 0x48>, "v_cmp_u_f32", COND_UO>;
531 defm V_CMP_NGE_F32 : VOPC_F32 <vopc<0x9, 0x49>, "v_cmp_nge_f32", COND_ULT, "v_cmp_nle_f32">;
532 defm V_CMP_NLG_F32 : VOPC_F32 <vopc<0xa, 0x4a>, "v_cmp_nlg_f32", COND_UEQ>;
533 defm V_CMP_NGT_F32 : VOPC_F32 <vopc<0xb, 0x4b>, "v_cmp_ngt_f32", COND_ULE, "v_cmp_nlt_f32">;
534 defm V_CMP_NLE_F32 : VOPC_F32 <vopc<0xc, 0x4c>, "v_cmp_nle_f32", COND_UGT>;
535 defm V_CMP_NEQ_F32 : VOPC_F32 <vopc<0xd, 0x4d>, "v_cmp_neq_f32", COND_UNE>;
536 defm V_CMP_NLT_F32 : VOPC_F32 <vopc<0xe, 0x4e>, "v_cmp_nlt_f32", COND_UGE>;
537 defm V_CMP_TRU_F32 : VOPC_F32 <vopc<0xf, 0x4f>, "v_cmp_tru_f32">;
540 defm V_CMPX_F_F32 : VOPCX_F32 <vopc<0x10, 0x50>, "v_cmpx_f_f32">;
541 defm V_CMPX_LT_F32 : VOPCX_F32 <vopc<0x11, 0x51>, "v_cmpx_lt_f32", "v_cmpx_gt_f32">;
542 defm V_CMPX_EQ_F32 : VOPCX_F32 <vopc<0x12, 0x52>, "v_cmpx_eq_f32">;
543 defm V_CMPX_LE_F32 : VOPCX_F32 <vopc<0x13, 0x53>, "v_cmpx_le_f32", "v_cmpx_ge_f32">;
544 defm V_CMPX_GT_F32 : VOPCX_F32 <vopc<0x14, 0x54>, "v_cmpx_gt_f32">;
545 defm V_CMPX_LG_F32 : VOPCX_F32 <vopc<0x15, 0x55>, "v_cmpx_lg_f32">;
546 defm V_CMPX_GE_F32 : VOPCX_F32 <vopc<0x16, 0x56>, "v_cmpx_ge_f32">;
547 defm V_CMPX_O_F32 : VOPCX_F32 <vopc<0x17, 0x57>, "v_cmpx_o_f32">;
548 defm V_CMPX_U_F32 : VOPCX_F32 <vopc<0x18, 0x58>, "v_cmpx_u_f32">;
549 defm V_CMPX_NGE_F32 : VOPCX_F32 <vopc<0x19, 0x59>, "v_cmpx_nge_f32">;
550 defm V_CMPX_NLG_F32 : VOPCX_F32 <vopc<0x1a, 0x5a>, "v_cmpx_nlg_f32">;
551 defm V_CMPX_NGT_F32 : VOPCX_F32 <vopc<0x1b, 0x5b>, "v_cmpx_ngt_f32">;
552 defm V_CMPX_NLE_F32 : VOPCX_F32 <vopc<0x1c, 0x5c>, "v_cmpx_nle_f32">;
553 defm V_CMPX_NEQ_F32 : VOPCX_F32 <vopc<0x1d, 0x5d>, "v_cmpx_neq_f32">;
554 defm V_CMPX_NLT_F32 : VOPCX_F32 <vopc<0x1e, 0x5e>, "v_cmpx_nlt_f32">;
555 defm V_CMPX_TRU_F32 : VOPCX_F32 <vopc<0x1f, 0x5f>, "v_cmpx_tru_f32">;
558 defm V_CMP_F_F64 : VOPC_F64 <vopc<0x20, 0x60>, "v_cmp_f_f64">;
559 defm V_CMP_LT_F64 : VOPC_F64 <vopc<0x21, 0x61>, "v_cmp_lt_f64", COND_OLT, "v_cmp_gt_f64">;
560 defm V_CMP_EQ_F64 : VOPC_F64 <vopc<0x22, 0x62>, "v_cmp_eq_f64", COND_OEQ>;
561 defm V_CMP_LE_F64 : VOPC_F64 <vopc<0x23, 0x63>, "v_cmp_le_f64", COND_OLE, "v_cmp_ge_f64">;
562 defm V_CMP_GT_F64 : VOPC_F64 <vopc<0x24, 0x64>, "v_cmp_gt_f64", COND_OGT>;
563 defm V_CMP_LG_F64 : VOPC_F64 <vopc<0x25, 0x65>, "v_cmp_lg_f64", COND_ONE>;
564 defm V_CMP_GE_F64 : VOPC_F64 <vopc<0x26, 0x66>, "v_cmp_ge_f64", COND_OGE>;
565 defm V_CMP_O_F64 : VOPC_F64 <vopc<0x27, 0x67>, "v_cmp_o_f64", COND_O>;
566 defm V_CMP_U_F64 : VOPC_F64 <vopc<0x28, 0x68>, "v_cmp_u_f64", COND_UO>;
567 defm V_CMP_NGE_F64 : VOPC_F64 <vopc<0x29, 0x69>, "v_cmp_nge_f64", COND_ULT, "v_cmp_nle_f64">;
568 defm V_CMP_NLG_F64 : VOPC_F64 <vopc<0x2a, 0x6a>, "v_cmp_nlg_f64", COND_UEQ>;
569 defm V_CMP_NGT_F64 : VOPC_F64 <vopc<0x2b, 0x6b>, "v_cmp_ngt_f64", COND_ULE, "v_cmp_nlt_f64">;
570 defm V_CMP_NLE_F64 : VOPC_F64 <vopc<0x2c, 0x6c>, "v_cmp_nle_f64", COND_UGT>;
571 defm V_CMP_NEQ_F64 : VOPC_F64 <vopc<0x2d, 0x6d>, "v_cmp_neq_f64", COND_UNE>;
572 defm V_CMP_NLT_F64 : VOPC_F64 <vopc<0x2e, 0x6e>, "v_cmp_nlt_f64", COND_UGE>;
573 defm V_CMP_TRU_F64 : VOPC_F64 <vopc<0x2f, 0x6f>, "v_cmp_tru_f64">;
576 defm V_CMPX_F_F64 : VOPCX_F64 <vopc<0x30, 0x70>, "v_cmpx_f_f64">;
577 defm V_CMPX_LT_F64 : VOPCX_F64 <vopc<0x31, 0x71>, "v_cmpx_lt_f64", "v_cmpx_gt_f64">;
578 defm V_CMPX_EQ_F64 : VOPCX_F64 <vopc<0x32, 0x72>, "v_cmpx_eq_f64">;
579 defm V_CMPX_LE_F64 : VOPCX_F64 <vopc<0x33, 0x73>, "v_cmpx_le_f64", "v_cmpx_ge_f64">;
580 defm V_CMPX_GT_F64 : VOPCX_F64 <vopc<0x34, 0x74>, "v_cmpx_gt_f64">;
581 defm V_CMPX_LG_F64 : VOPCX_F64 <vopc<0x35, 0x75>, "v_cmpx_lg_f64">;
582 defm V_CMPX_GE_F64 : VOPCX_F64 <vopc<0x36, 0x76>, "v_cmpx_ge_f64">;
583 defm V_CMPX_O_F64 : VOPCX_F64 <vopc<0x37, 0x77>, "v_cmpx_o_f64">;
584 defm V_CMPX_U_F64 : VOPCX_F64 <vopc<0x38, 0x78>, "v_cmpx_u_f64">;
585 defm V_CMPX_NGE_F64 : VOPCX_F64 <vopc<0x39, 0x79>, "v_cmpx_nge_f64", "v_cmpx_nle_f64">;
586 defm V_CMPX_NLG_F64 : VOPCX_F64 <vopc<0x3a, 0x7a>, "v_cmpx_nlg_f64">;
587 defm V_CMPX_NGT_F64 : VOPCX_F64 <vopc<0x3b, 0x7b>, "v_cmpx_ngt_f64", "v_cmpx_nlt_f64">;
588 defm V_CMPX_NLE_F64 : VOPCX_F64 <vopc<0x3c, 0x7c>, "v_cmpx_nle_f64">;
589 defm V_CMPX_NEQ_F64 : VOPCX_F64 <vopc<0x3d, 0x7d>, "v_cmpx_neq_f64">;
590 defm V_CMPX_NLT_F64 : VOPCX_F64 <vopc<0x3e, 0x7e>, "v_cmpx_nlt_f64">;
591 defm V_CMPX_TRU_F64 : VOPCX_F64 <vopc<0x3f, 0x7f>, "v_cmpx_tru_f64">;
594 let SubtargetPredicate = isSICI in {
596 defm V_CMPS_F_F32 : VOPC_F32 <vopc<0x40>, "v_cmps_f_f32">;
597 defm V_CMPS_LT_F32 : VOPC_F32 <vopc<0x41>, "v_cmps_lt_f32", COND_NULL, "v_cmps_gt_f32">;
598 defm V_CMPS_EQ_F32 : VOPC_F32 <vopc<0x42>, "v_cmps_eq_f32">;
599 defm V_CMPS_LE_F32 : VOPC_F32 <vopc<0x43>, "v_cmps_le_f32", COND_NULL, "v_cmps_ge_f32">;
600 defm V_CMPS_GT_F32 : VOPC_F32 <vopc<0x44>, "v_cmps_gt_f32">;
601 defm V_CMPS_LG_F32 : VOPC_F32 <vopc<0x45>, "v_cmps_lg_f32">;
602 defm V_CMPS_GE_F32 : VOPC_F32 <vopc<0x46>, "v_cmps_ge_f32">;
603 defm V_CMPS_O_F32 : VOPC_F32 <vopc<0x47>, "v_cmps_o_f32">;
604 defm V_CMPS_U_F32 : VOPC_F32 <vopc<0x48>, "v_cmps_u_f32">;
605 defm V_CMPS_NGE_F32 : VOPC_F32 <vopc<0x49>, "v_cmps_nge_f32", COND_NULL, "v_cmps_nle_f32">;
606 defm V_CMPS_NLG_F32 : VOPC_F32 <vopc<0x4a>, "v_cmps_nlg_f32">;
607 defm V_CMPS_NGT_F32 : VOPC_F32 <vopc<0x4b>, "v_cmps_ngt_f32", COND_NULL, "v_cmps_nlt_f32">;
608 defm V_CMPS_NLE_F32 : VOPC_F32 <vopc<0x4c>, "v_cmps_nle_f32">;
609 defm V_CMPS_NEQ_F32 : VOPC_F32 <vopc<0x4d>, "v_cmps_neq_f32">;
610 defm V_CMPS_NLT_F32 : VOPC_F32 <vopc<0x4e>, "v_cmps_nlt_f32">;
611 defm V_CMPS_TRU_F32 : VOPC_F32 <vopc<0x4f>, "v_cmps_tru_f32">;
614 defm V_CMPSX_F_F32 : VOPCX_F32 <vopc<0x50>, "v_cmpsx_f_f32">;
615 defm V_CMPSX_LT_F32 : VOPCX_F32 <vopc<0x51>, "v_cmpsx_lt_f32", "v_cmpsx_gt_f32">;
616 defm V_CMPSX_EQ_F32 : VOPCX_F32 <vopc<0x52>, "v_cmpsx_eq_f32">;
617 defm V_CMPSX_LE_F32 : VOPCX_F32 <vopc<0x53>, "v_cmpsx_le_f32", "v_cmpsx_ge_f32">;
618 defm V_CMPSX_GT_F32 : VOPCX_F32 <vopc<0x54>, "v_cmpsx_gt_f32">;
619 defm V_CMPSX_LG_F32 : VOPCX_F32 <vopc<0x55>, "v_cmpsx_lg_f32">;
620 defm V_CMPSX_GE_F32 : VOPCX_F32 <vopc<0x56>, "v_cmpsx_ge_f32">;
621 defm V_CMPSX_O_F32 : VOPCX_F32 <vopc<0x57>, "v_cmpsx_o_f32">;
622 defm V_CMPSX_U_F32 : VOPCX_F32 <vopc<0x58>, "v_cmpsx_u_f32">;
623 defm V_CMPSX_NGE_F32 : VOPCX_F32 <vopc<0x59>, "v_cmpsx_nge_f32", "v_cmpsx_nle_f32">;
624 defm V_CMPSX_NLG_F32 : VOPCX_F32 <vopc<0x5a>, "v_cmpsx_nlg_f32">;
625 defm V_CMPSX_NGT_F32 : VOPCX_F32 <vopc<0x5b>, "v_cmpsx_ngt_f32", "v_cmpsx_nlt_f32">;
626 defm V_CMPSX_NLE_F32 : VOPCX_F32 <vopc<0x5c>, "v_cmpsx_nle_f32">;
627 defm V_CMPSX_NEQ_F32 : VOPCX_F32 <vopc<0x5d>, "v_cmpsx_neq_f32">;
628 defm V_CMPSX_NLT_F32 : VOPCX_F32 <vopc<0x5e>, "v_cmpsx_nlt_f32">;
629 defm V_CMPSX_TRU_F32 : VOPCX_F32 <vopc<0x5f>, "v_cmpsx_tru_f32">;
632 defm V_CMPS_F_F64 : VOPC_F64 <vopc<0x60>, "v_cmps_f_f64">;
633 defm V_CMPS_LT_F64 : VOPC_F64 <vopc<0x61>, "v_cmps_lt_f64", COND_NULL, "v_cmps_gt_f64">;
634 defm V_CMPS_EQ_F64 : VOPC_F64 <vopc<0x62>, "v_cmps_eq_f64">;
635 defm V_CMPS_LE_F64 : VOPC_F64 <vopc<0x63>, "v_cmps_le_f64", COND_NULL, "v_cmps_ge_f64">;
636 defm V_CMPS_GT_F64 : VOPC_F64 <vopc<0x64>, "v_cmps_gt_f64">;
637 defm V_CMPS_LG_F64 : VOPC_F64 <vopc<0x65>, "v_cmps_lg_f64">;
638 defm V_CMPS_GE_F64 : VOPC_F64 <vopc<0x66>, "v_cmps_ge_f64">;
639 defm V_CMPS_O_F64 : VOPC_F64 <vopc<0x67>, "v_cmps_o_f64">;
640 defm V_CMPS_U_F64 : VOPC_F64 <vopc<0x68>, "v_cmps_u_f64">;
641 defm V_CMPS_NGE_F64 : VOPC_F64 <vopc<0x69>, "v_cmps_nge_f64", COND_NULL, "v_cmps_nle_f64">;
642 defm V_CMPS_NLG_F64 : VOPC_F64 <vopc<0x6a>, "v_cmps_nlg_f64">;
643 defm V_CMPS_NGT_F64 : VOPC_F64 <vopc<0x6b>, "v_cmps_ngt_f64", COND_NULL, "v_cmps_nlt_f64">;
644 defm V_CMPS_NLE_F64 : VOPC_F64 <vopc<0x6c>, "v_cmps_nle_f64">;
645 defm V_CMPS_NEQ_F64 : VOPC_F64 <vopc<0x6d>, "v_cmps_neq_f64">;
646 defm V_CMPS_NLT_F64 : VOPC_F64 <vopc<0x6e>, "v_cmps_nlt_f64">;
647 defm V_CMPS_TRU_F64 : VOPC_F64 <vopc<0x6f>, "v_cmps_tru_f64">;
650 defm V_CMPSX_F_F64 : VOPCX_F64 <vopc<0x70>, "v_cmpsx_f_f64">;
651 defm V_CMPSX_LT_F64 : VOPCX_F64 <vopc<0x71>, "v_cmpsx_lt_f64", "v_cmpsx_gt_f64">;
652 defm V_CMPSX_EQ_F64 : VOPCX_F64 <vopc<0x72>, "v_cmpsx_eq_f64">;
653 defm V_CMPSX_LE_F64 : VOPCX_F64 <vopc<0x73>, "v_cmpsx_le_f64", "v_cmpsx_ge_f64">;
654 defm V_CMPSX_GT_F64 : VOPCX_F64 <vopc<0x74>, "v_cmpsx_gt_f64">;
655 defm V_CMPSX_LG_F64 : VOPCX_F64 <vopc<0x75>, "v_cmpsx_lg_f64">;
656 defm V_CMPSX_GE_F64 : VOPCX_F64 <vopc<0x76>, "v_cmpsx_ge_f64">;
657 defm V_CMPSX_O_F64 : VOPCX_F64 <vopc<0x77>, "v_cmpsx_o_f64">;
658 defm V_CMPSX_U_F64 : VOPCX_F64 <vopc<0x78>, "v_cmpsx_u_f64">;
659 defm V_CMPSX_NGE_F64 : VOPCX_F64 <vopc<0x79>, "v_cmpsx_nge_f64", "v_cmpsx_nle_f64">;
660 defm V_CMPSX_NLG_F64 : VOPCX_F64 <vopc<0x7a>, "v_cmpsx_nlg_f64">;
661 defm V_CMPSX_NGT_F64 : VOPCX_F64 <vopc<0x7b>, "v_cmpsx_ngt_f64", "v_cmpsx_nlt_f64">;
662 defm V_CMPSX_NLE_F64 : VOPCX_F64 <vopc<0x7c>, "v_cmpsx_nle_f64">;
663 defm V_CMPSX_NEQ_F64 : VOPCX_F64 <vopc<0x7d>, "v_cmpsx_neq_f64">;
664 defm V_CMPSX_NLT_F64 : VOPCX_F64 <vopc<0x7e>, "v_cmpsx_nlt_f64">;
665 defm V_CMPSX_TRU_F64 : VOPCX_F64 <vopc<0x7f>, "v_cmpsx_tru_f64">;
667 } // End SubtargetPredicate = isSICI
669 defm V_CMP_F_I32 : VOPC_I32 <vopc<0x80, 0xc0>, "v_cmp_f_i32">;
670 defm V_CMP_LT_I32 : VOPC_I32 <vopc<0x81, 0xc1>, "v_cmp_lt_i32", COND_SLT, "v_cmp_gt_i32">;
671 defm V_CMP_EQ_I32 : VOPC_I32 <vopc<0x82, 0xc2>, "v_cmp_eq_i32", COND_EQ>;
672 defm V_CMP_LE_I32 : VOPC_I32 <vopc<0x83, 0xc3>, "v_cmp_le_i32", COND_SLE, "v_cmp_ge_i32">;
673 defm V_CMP_GT_I32 : VOPC_I32 <vopc<0x84, 0xc4>, "v_cmp_gt_i32", COND_SGT>;
674 defm V_CMP_NE_I32 : VOPC_I32 <vopc<0x85, 0xc5>, "v_cmp_ne_i32", COND_NE>;
675 defm V_CMP_GE_I32 : VOPC_I32 <vopc<0x86, 0xc6>, "v_cmp_ge_i32", COND_SGE>;
676 defm V_CMP_T_I32 : VOPC_I32 <vopc<0x87, 0xc7>, "v_cmp_t_i32">;
679 defm V_CMPX_F_I32 : VOPCX_I32 <vopc<0x90, 0xd0>, "v_cmpx_f_i32">;
680 defm V_CMPX_LT_I32 : VOPCX_I32 <vopc<0x91, 0xd1>, "v_cmpx_lt_i32", "v_cmpx_gt_i32">;
681 defm V_CMPX_EQ_I32 : VOPCX_I32 <vopc<0x92, 0xd2>, "v_cmpx_eq_i32">;
682 defm V_CMPX_LE_I32 : VOPCX_I32 <vopc<0x93, 0xd3>, "v_cmpx_le_i32", "v_cmpx_ge_i32">;
683 defm V_CMPX_GT_I32 : VOPCX_I32 <vopc<0x94, 0xd4>, "v_cmpx_gt_i32">;
684 defm V_CMPX_NE_I32 : VOPCX_I32 <vopc<0x95, 0xd5>, "v_cmpx_ne_i32">;
685 defm V_CMPX_GE_I32 : VOPCX_I32 <vopc<0x96, 0xd6>, "v_cmpx_ge_i32">;
686 defm V_CMPX_T_I32 : VOPCX_I32 <vopc<0x97, 0xd7>, "v_cmpx_t_i32">;
689 defm V_CMP_F_I64 : VOPC_I64 <vopc<0xa0, 0xe0>, "v_cmp_f_i64">;
690 defm V_CMP_LT_I64 : VOPC_I64 <vopc<0xa1, 0xe1>, "v_cmp_lt_i64", COND_SLT, "v_cmp_gt_i64">;
691 defm V_CMP_EQ_I64 : VOPC_I64 <vopc<0xa2, 0xe2>, "v_cmp_eq_i64", COND_EQ>;
692 defm V_CMP_LE_I64 : VOPC_I64 <vopc<0xa3, 0xe3>, "v_cmp_le_i64", COND_SLE, "v_cmp_ge_i64">;
693 defm V_CMP_GT_I64 : VOPC_I64 <vopc<0xa4, 0xe4>, "v_cmp_gt_i64", COND_SGT>;
694 defm V_CMP_NE_I64 : VOPC_I64 <vopc<0xa5, 0xe5>, "v_cmp_ne_i64", COND_NE>;
695 defm V_CMP_GE_I64 : VOPC_I64 <vopc<0xa6, 0xe6>, "v_cmp_ge_i64", COND_SGE>;
696 defm V_CMP_T_I64 : VOPC_I64 <vopc<0xa7, 0xe7>, "v_cmp_t_i64">;
699 defm V_CMPX_F_I64 : VOPCX_I64 <vopc<0xb0, 0xf0>, "v_cmpx_f_i64">;
700 defm V_CMPX_LT_I64 : VOPCX_I64 <vopc<0xb1, 0xf1>, "v_cmpx_lt_i64", "v_cmpx_gt_i64">;
701 defm V_CMPX_EQ_I64 : VOPCX_I64 <vopc<0xb2, 0xf2>, "v_cmpx_eq_i64">;
702 defm V_CMPX_LE_I64 : VOPCX_I64 <vopc<0xb3, 0xf3>, "v_cmpx_le_i64", "v_cmpx_ge_i64">;
703 defm V_CMPX_GT_I64 : VOPCX_I64 <vopc<0xb4, 0xf4>, "v_cmpx_gt_i64">;
704 defm V_CMPX_NE_I64 : VOPCX_I64 <vopc<0xb5, 0xf5>, "v_cmpx_ne_i64">;
705 defm V_CMPX_GE_I64 : VOPCX_I64 <vopc<0xb6, 0xf6>, "v_cmpx_ge_i64">;
706 defm V_CMPX_T_I64 : VOPCX_I64 <vopc<0xb7, 0xf7>, "v_cmpx_t_i64">;
709 defm V_CMP_F_U32 : VOPC_I32 <vopc<0xc0, 0xc8>, "v_cmp_f_u32">;
710 defm V_CMP_LT_U32 : VOPC_I32 <vopc<0xc1, 0xc9>, "v_cmp_lt_u32", COND_ULT, "v_cmp_gt_u32">;
711 defm V_CMP_EQ_U32 : VOPC_I32 <vopc<0xc2, 0xca>, "v_cmp_eq_u32", COND_EQ>;
712 defm V_CMP_LE_U32 : VOPC_I32 <vopc<0xc3, 0xcb>, "v_cmp_le_u32", COND_ULE, "v_cmp_ge_u32">;
713 defm V_CMP_GT_U32 : VOPC_I32 <vopc<0xc4, 0xcc>, "v_cmp_gt_u32", COND_UGT>;
714 defm V_CMP_NE_U32 : VOPC_I32 <vopc<0xc5, 0xcd>, "v_cmp_ne_u32", COND_NE>;
715 defm V_CMP_GE_U32 : VOPC_I32 <vopc<0xc6, 0xce>, "v_cmp_ge_u32", COND_UGE>;
716 defm V_CMP_T_U32 : VOPC_I32 <vopc<0xc7, 0xcf>, "v_cmp_t_u32">;
719 defm V_CMPX_F_U32 : VOPCX_I32 <vopc<0xd0, 0xd8>, "v_cmpx_f_u32">;
720 defm V_CMPX_LT_U32 : VOPCX_I32 <vopc<0xd1, 0xd9>, "v_cmpx_lt_u32", "v_cmpx_gt_u32">;
721 defm V_CMPX_EQ_U32 : VOPCX_I32 <vopc<0xd2, 0xda>, "v_cmpx_eq_u32">;
722 defm V_CMPX_LE_U32 : VOPCX_I32 <vopc<0xd3, 0xdb>, "v_cmpx_le_u32", "v_cmpx_le_u32">;
723 defm V_CMPX_GT_U32 : VOPCX_I32 <vopc<0xd4, 0xdc>, "v_cmpx_gt_u32">;
724 defm V_CMPX_NE_U32 : VOPCX_I32 <vopc<0xd5, 0xdd>, "v_cmpx_ne_u32">;
725 defm V_CMPX_GE_U32 : VOPCX_I32 <vopc<0xd6, 0xde>, "v_cmpx_ge_u32">;
726 defm V_CMPX_T_U32 : VOPCX_I32 <vopc<0xd7, 0xdf>, "v_cmpx_t_u32">;
729 defm V_CMP_F_U64 : VOPC_I64 <vopc<0xe0, 0xe8>, "v_cmp_f_u64">;
730 defm V_CMP_LT_U64 : VOPC_I64 <vopc<0xe1, 0xe9>, "v_cmp_lt_u64", COND_ULT, "v_cmp_gt_u64">;
731 defm V_CMP_EQ_U64 : VOPC_I64 <vopc<0xe2, 0xea>, "v_cmp_eq_u64", COND_EQ>;
732 defm V_CMP_LE_U64 : VOPC_I64 <vopc<0xe3, 0xeb>, "v_cmp_le_u64", COND_ULE, "v_cmp_ge_u64">;
733 defm V_CMP_GT_U64 : VOPC_I64 <vopc<0xe4, 0xec>, "v_cmp_gt_u64", COND_UGT>;
734 defm V_CMP_NE_U64 : VOPC_I64 <vopc<0xe5, 0xed>, "v_cmp_ne_u64", COND_NE>;
735 defm V_CMP_GE_U64 : VOPC_I64 <vopc<0xe6, 0xee>, "v_cmp_ge_u64", COND_UGE>;
736 defm V_CMP_T_U64 : VOPC_I64 <vopc<0xe7, 0xef>, "v_cmp_t_u64">;
738 defm V_CMPX_F_U64 : VOPCX_I64 <vopc<0xf0, 0xf8>, "v_cmpx_f_u64">;
739 defm V_CMPX_LT_U64 : VOPCX_I64 <vopc<0xf1, 0xf9>, "v_cmpx_lt_u64", "v_cmpx_gt_u64">;
740 defm V_CMPX_EQ_U64 : VOPCX_I64 <vopc<0xf2, 0xfa>, "v_cmpx_eq_u64">;
741 defm V_CMPX_LE_U64 : VOPCX_I64 <vopc<0xf3, 0xfb>, "v_cmpx_le_u64", "v_cmpx_ge_u64">;
742 defm V_CMPX_GT_U64 : VOPCX_I64 <vopc<0xf4, 0xfc>, "v_cmpx_gt_u64">;
743 defm V_CMPX_NE_U64 : VOPCX_I64 <vopc<0xf5, 0xfd>, "v_cmpx_ne_u64">;
744 defm V_CMPX_GE_U64 : VOPCX_I64 <vopc<0xf6, 0xfe>, "v_cmpx_ge_u64">;
745 defm V_CMPX_T_U64 : VOPCX_I64 <vopc<0xf7, 0xff>, "v_cmpx_t_u64">;
747 } // End isCompare = 1, isCommutable = 1
749 defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 <vopc<0x88, 0x10>, "v_cmp_class_f32">;
750 defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 <vopc<0x98, 0x11>, "v_cmpx_class_f32">;
751 defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 <vopc<0xa8, 0x12>, "v_cmp_class_f64">;
752 defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 <vopc<0xb8, 0x13>, "v_cmpx_class_f64">;
754 //===----------------------------------------------------------------------===//
756 //===----------------------------------------------------------------------===//
758 defm DS_ADD_U32 : DS_1A1D_NORET <0x0, "ds_add_u32", VGPR_32>;
759 defm DS_SUB_U32 : DS_1A1D_NORET <0x1, "ds_sub_u32", VGPR_32>;
760 defm DS_RSUB_U32 : DS_1A1D_NORET <0x2, "ds_rsub_u32", VGPR_32>;
761 defm DS_INC_U32 : DS_1A1D_NORET <0x3, "ds_inc_u32", VGPR_32>;
762 defm DS_DEC_U32 : DS_1A1D_NORET <0x4, "ds_dec_u32", VGPR_32>;
763 defm DS_MIN_I32 : DS_1A1D_NORET <0x5, "ds_min_i32", VGPR_32>;
764 defm DS_MAX_I32 : DS_1A1D_NORET <0x6, "ds_max_i32", VGPR_32>;
765 defm DS_MIN_U32 : DS_1A1D_NORET <0x7, "ds_min_u32", VGPR_32>;
766 defm DS_MAX_U32 : DS_1A1D_NORET <0x8, "ds_max_u32", VGPR_32>;
767 defm DS_AND_B32 : DS_1A1D_NORET <0x9, "ds_and_b32", VGPR_32>;
768 defm DS_OR_B32 : DS_1A1D_NORET <0xa, "ds_or_b32", VGPR_32>;
769 defm DS_XOR_B32 : DS_1A1D_NORET <0xb, "ds_xor_b32", VGPR_32>;
770 defm DS_MSKOR_B32 : DS_1A2D_NORET <0xc, "ds_mskor_b32", VGPR_32>;
772 defm DS_WRITE_B32 : DS_1A1D_NORET <0xd, "ds_write_b32", VGPR_32>;
773 defm DS_WRITE2_B32 : DS_1A1D_Off8_NORET <0xe, "ds_write2_b32", VGPR_32>;
774 defm DS_WRITE2ST64_B32 : DS_1A1D_Off8_NORET <0xf, "ds_write2st64_b32", VGPR_32>;
776 defm DS_CMPST_B32 : DS_1A2D_NORET <0x10, "ds_cmpst_b32", VGPR_32>;
777 defm DS_CMPST_F32 : DS_1A2D_NORET <0x11, "ds_cmpst_f32", VGPR_32>;
778 defm DS_MIN_F32 : DS_1A2D_NORET <0x12, "ds_min_f32", VGPR_32>;
779 defm DS_MAX_F32 : DS_1A2D_NORET <0x13, "ds_max_f32", VGPR_32>;
781 defm DS_GWS_INIT : DS_1A_GDS <0x19, "ds_gws_init">;
782 defm DS_GWS_SEMA_V : DS_1A_GDS <0x1a, "ds_gws_sema_v">;
783 defm DS_GWS_SEMA_BR : DS_1A_GDS <0x1b, "ds_gws_sema_br">;
784 defm DS_GWS_SEMA_P : DS_1A_GDS <0x1c, "ds_gws_sema_p">;
785 defm DS_GWS_BARRIER : DS_1A_GDS <0x1d, "ds_gws_barrier">;
787 defm DS_WRITE_B8 : DS_1A1D_NORET <0x1e, "ds_write_b8", VGPR_32>;
788 defm DS_WRITE_B16 : DS_1A1D_NORET <0x1f, "ds_write_b16", VGPR_32>;
790 defm DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "ds_add_rtn_u32", VGPR_32, "ds_add_u32">;
791 defm DS_SUB_RTN_U32 : DS_1A1D_RET <0x21, "ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">;
792 defm DS_RSUB_RTN_U32 : DS_1A1D_RET <0x22, "ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">;
793 defm DS_INC_RTN_U32 : DS_1A1D_RET <0x23, "ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">;
794 defm DS_DEC_RTN_U32 : DS_1A1D_RET <0x24, "ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">;
795 defm DS_MIN_RTN_I32 : DS_1A1D_RET <0x25, "ds_min_rtn_i32", VGPR_32, "ds_min_i32">;
796 defm DS_MAX_RTN_I32 : DS_1A1D_RET <0x26, "ds_max_rtn_i32", VGPR_32, "ds_max_i32">;
797 defm DS_MIN_RTN_U32 : DS_1A1D_RET <0x27, "ds_min_rtn_u32", VGPR_32, "ds_min_u32">;
798 defm DS_MAX_RTN_U32 : DS_1A1D_RET <0x28, "ds_max_rtn_u32", VGPR_32, "ds_max_u32">;
799 defm DS_AND_RTN_B32 : DS_1A1D_RET <0x29, "ds_and_rtn_b32", VGPR_32, "ds_and_b32">;
800 defm DS_OR_RTN_B32 : DS_1A1D_RET <0x2a, "ds_or_rtn_b32", VGPR_32, "ds_or_b32">;
801 defm DS_XOR_RTN_B32 : DS_1A1D_RET <0x2b, "ds_xor_rtn_b32", VGPR_32, "ds_xor_b32">;
802 defm DS_MSKOR_RTN_B32 : DS_1A2D_RET <0x2c, "ds_mskor_rtn_b32", VGPR_32, "ds_mskor_b32">;
803 defm DS_WRXCHG_RTN_B32 : DS_1A1D_RET <0x2d, "ds_wrxchg_rtn_b32", VGPR_32>;
804 defm DS_WRXCHG2_RTN_B32 : DS_1A2D_RET <
805 0x2e, "ds_wrxchg2_rtn_b32", VReg_64, "", VGPR_32
807 defm DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_RET <
808 0x2f, "ds_wrxchg2st64_rtn_b32", VReg_64, "", VGPR_32
810 defm DS_CMPST_RTN_B32 : DS_1A2D_RET <0x30, "ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">;
811 defm DS_CMPST_RTN_F32 : DS_1A2D_RET <0x31, "ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">;
812 defm DS_MIN_RTN_F32 : DS_1A2D_RET <0x32, "ds_min_rtn_f32", VGPR_32, "ds_min_f32">;
813 defm DS_MAX_RTN_F32 : DS_1A2D_RET <0x33, "ds_max_rtn_f32", VGPR_32, "ds_max_f32">;
814 defm DS_SWIZZLE_B32 : DS_1A_RET <0x35, "ds_swizzle_b32", VGPR_32>;
815 let mayStore = 0 in {
816 defm DS_READ_B32 : DS_1A_RET <0x36, "ds_read_b32", VGPR_32>;
817 defm DS_READ2_B32 : DS_1A_Off8_RET <0x37, "ds_read2_b32", VReg_64>;
818 defm DS_READ2ST64_B32 : DS_1A_Off8_RET <0x38, "ds_read2st64_b32", VReg_64>;
819 defm DS_READ_I8 : DS_1A_RET <0x39, "ds_read_i8", VGPR_32>;
820 defm DS_READ_U8 : DS_1A_RET <0x3a, "ds_read_u8", VGPR_32>;
821 defm DS_READ_I16 : DS_1A_RET <0x3b, "ds_read_i16", VGPR_32>;
822 defm DS_READ_U16 : DS_1A_RET <0x3c, "ds_read_u16", VGPR_32>;
824 defm DS_CONSUME : DS_0A_RET <0x3d, "ds_consume">;
825 defm DS_APPEND : DS_0A_RET <0x3e, "ds_append">;
826 defm DS_ORDERED_COUNT : DS_1A_RET_GDS <0x3f, "ds_ordered_count">;
827 defm DS_ADD_U64 : DS_1A1D_NORET <0x40, "ds_add_u64", VReg_64>;
828 defm DS_SUB_U64 : DS_1A1D_NORET <0x41, "ds_sub_u64", VReg_64>;
829 defm DS_RSUB_U64 : DS_1A1D_NORET <0x42, "ds_rsub_u64", VReg_64>;
830 defm DS_INC_U64 : DS_1A1D_NORET <0x43, "ds_inc_u64", VReg_64>;
831 defm DS_DEC_U64 : DS_1A1D_NORET <0x44, "ds_dec_u64", VReg_64>;
832 defm DS_MIN_I64 : DS_1A1D_NORET <0x45, "ds_min_i64", VReg_64>;
833 defm DS_MAX_I64 : DS_1A1D_NORET <0x46, "ds_max_i64", VReg_64>;
834 defm DS_MIN_U64 : DS_1A1D_NORET <0x47, "ds_min_u64", VReg_64>;
835 defm DS_MAX_U64 : DS_1A1D_NORET <0x48, "ds_max_u64", VReg_64>;
836 defm DS_AND_B64 : DS_1A1D_NORET <0x49, "ds_and_b64", VReg_64>;
837 defm DS_OR_B64 : DS_1A1D_NORET <0x4a, "ds_or_b64", VReg_64>;
838 defm DS_XOR_B64 : DS_1A1D_NORET <0x4b, "ds_xor_b64", VReg_64>;
839 defm DS_MSKOR_B64 : DS_1A2D_NORET <0x4c, "ds_mskor_b64", VReg_64>;
841 defm DS_WRITE_B64 : DS_1A1D_NORET <0x4d, "ds_write_b64", VReg_64>;
842 defm DS_WRITE2_B64 : DS_1A1D_Off8_NORET <0x4E, "ds_write2_b64", VReg_64>;
843 defm DS_WRITE2ST64_B64 : DS_1A1D_Off8_NORET <0x4f, "ds_write2st64_b64", VReg_64>;
845 defm DS_CMPST_B64 : DS_1A2D_NORET <0x50, "ds_cmpst_b64", VReg_64>;
846 defm DS_CMPST_F64 : DS_1A2D_NORET <0x51, "ds_cmpst_f64", VReg_64>;
847 defm DS_MIN_F64 : DS_1A1D_NORET <0x52, "ds_min_f64", VReg_64>;
848 defm DS_MAX_F64 : DS_1A1D_NORET <0x53, "ds_max_f64", VReg_64>;
850 defm DS_ADD_RTN_U64 : DS_1A1D_RET <0x60, "ds_add_rtn_u64", VReg_64, "ds_add_u64">;
851 defm DS_SUB_RTN_U64 : DS_1A1D_RET <0x61, "ds_sub_rtn_u64", VReg_64, "ds_sub_u64">;
852 defm DS_RSUB_RTN_U64 : DS_1A1D_RET <0x62, "ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">;
853 defm DS_INC_RTN_U64 : DS_1A1D_RET <0x63, "ds_inc_rtn_u64", VReg_64, "ds_inc_u64">;
854 defm DS_DEC_RTN_U64 : DS_1A1D_RET <0x64, "ds_dec_rtn_u64", VReg_64, "ds_dec_u64">;
855 defm DS_MIN_RTN_I64 : DS_1A1D_RET <0x65, "ds_min_rtn_i64", VReg_64, "ds_min_i64">;
856 defm DS_MAX_RTN_I64 : DS_1A1D_RET <0x66, "ds_max_rtn_i64", VReg_64, "ds_max_i64">;
857 defm DS_MIN_RTN_U64 : DS_1A1D_RET <0x67, "ds_min_rtn_u64", VReg_64, "ds_min_u64">;
858 defm DS_MAX_RTN_U64 : DS_1A1D_RET <0x68, "ds_max_rtn_u64", VReg_64, "ds_max_u64">;
859 defm DS_AND_RTN_B64 : DS_1A1D_RET <0x69, "ds_and_rtn_b64", VReg_64, "ds_and_b64">;
860 defm DS_OR_RTN_B64 : DS_1A1D_RET <0x6a, "ds_or_rtn_b64", VReg_64, "ds_or_b64">;
861 defm DS_XOR_RTN_B64 : DS_1A1D_RET <0x6b, "ds_xor_rtn_b64", VReg_64, "ds_xor_b64">;
862 defm DS_MSKOR_RTN_B64 : DS_1A2D_RET <0x6c, "ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">;
863 defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET <0x6d, "ds_wrxchg_rtn_b64", VReg_64, "ds_wrxchg_b64">;
864 defm DS_WRXCHG2_RTN_B64 : DS_1A2D_RET <0x6e, "ds_wrxchg2_rtn_b64", VReg_128, "ds_wrxchg2_b64", VReg_64>;
865 defm DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_RET <0x6f, "ds_wrxchg2st64_rtn_b64", VReg_128, "ds_wrxchg2st64_b64", VReg_64>;
866 defm DS_CMPST_RTN_B64 : DS_1A2D_RET <0x70, "ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">;
867 defm DS_CMPST_RTN_F64 : DS_1A2D_RET <0x71, "ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">;
868 defm DS_MIN_RTN_F64 : DS_1A1D_RET <0x72, "ds_min_rtn_f64", VReg_64, "ds_min_f64">;
869 defm DS_MAX_RTN_F64 : DS_1A1D_RET <0x73, "ds_max_rtn_f64", VReg_64, "ds_max_f64">;
871 let mayStore = 0 in {
872 defm DS_READ_B64 : DS_1A_RET <0x76, "ds_read_b64", VReg_64>;
873 defm DS_READ2_B64 : DS_1A_Off8_RET <0x77, "ds_read2_b64", VReg_128>;
874 defm DS_READ2ST64_B64 : DS_1A_Off8_RET <0x78, "ds_read2st64_b64", VReg_128>;
877 defm DS_ADD_SRC2_U32 : DS_1A <0x80, "ds_add_src2_u32">;
878 defm DS_SUB_SRC2_U32 : DS_1A <0x81, "ds_sub_src2_u32">;
879 defm DS_RSUB_SRC2_U32 : DS_1A <0x82, "ds_rsub_src2_u32">;
880 defm DS_INC_SRC2_U32 : DS_1A <0x83, "ds_inc_src2_u32">;
881 defm DS_DEC_SRC2_U32 : DS_1A <0x84, "ds_dec_src2_u32">;
882 defm DS_MIN_SRC2_I32 : DS_1A <0x85, "ds_min_src2_i32">;
883 defm DS_MAX_SRC2_I32 : DS_1A <0x86, "ds_max_src2_i32">;
884 defm DS_MIN_SRC2_U32 : DS_1A <0x87, "ds_min_src2_u32">;
885 defm DS_MAX_SRC2_U32 : DS_1A <0x88, "ds_max_src2_u32">;
886 defm DS_AND_SRC2_B32 : DS_1A <0x89, "ds_and_src_b32">;
887 defm DS_OR_SRC2_B32 : DS_1A <0x8a, "ds_or_src2_b32">;
888 defm DS_XOR_SRC2_B32 : DS_1A <0x8b, "ds_xor_src2_b32">;
889 defm DS_WRITE_SRC2_B32 : DS_1A <0x8c, "ds_write_src2_b32">;
891 defm DS_MIN_SRC2_F32 : DS_1A <0x92, "ds_min_src2_f32">;
892 defm DS_MAX_SRC2_F32 : DS_1A <0x93, "ds_max_src2_f32">;
894 defm DS_ADD_SRC2_U64 : DS_1A <0xc0, "ds_add_src2_u64">;
895 defm DS_SUB_SRC2_U64 : DS_1A <0xc1, "ds_sub_src2_u64">;
896 defm DS_RSUB_SRC2_U64 : DS_1A <0xc2, "ds_rsub_src2_u64">;
897 defm DS_INC_SRC2_U64 : DS_1A <0xc3, "ds_inc_src2_u64">;
898 defm DS_DEC_SRC2_U64 : DS_1A <0xc4, "ds_dec_src2_u64">;
899 defm DS_MIN_SRC2_I64 : DS_1A <0xc5, "ds_min_src2_i64">;
900 defm DS_MAX_SRC2_I64 : DS_1A <0xc6, "ds_max_src2_i64">;
901 defm DS_MIN_SRC2_U64 : DS_1A <0xc7, "ds_min_src2_u64">;
902 defm DS_MAX_SRC2_U64 : DS_1A <0xc8, "ds_max_src2_u64">;
903 defm DS_AND_SRC2_B64 : DS_1A <0xc9, "ds_and_src2_b64">;
904 defm DS_OR_SRC2_B64 : DS_1A <0xca, "ds_or_src2_b64">;
905 defm DS_XOR_SRC2_B64 : DS_1A <0xcb, "ds_xor_src2_b64">;
906 defm DS_WRITE_SRC2_B64 : DS_1A <0xcc, "ds_write_src2_b64">;
908 defm DS_MIN_SRC2_F64 : DS_1A <0xd2, "ds_min_src2_f64">;
909 defm DS_MAX_SRC2_F64 : DS_1A <0xd3, "ds_max_src2_f64">;
911 //===----------------------------------------------------------------------===//
912 // MUBUF Instructions
913 //===----------------------------------------------------------------------===//
915 defm BUFFER_LOAD_FORMAT_X : MUBUF_Load_Helper <
916 mubuf<0x00>, "buffer_load_format_x", VGPR_32
918 defm BUFFER_LOAD_FORMAT_XY : MUBUF_Load_Helper <
919 mubuf<0x01>, "buffer_load_format_xy", VReg_64
921 defm BUFFER_LOAD_FORMAT_XYZ : MUBUF_Load_Helper <
922 mubuf<0x02>, "buffer_load_format_xyz", VReg_96
924 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <
925 mubuf<0x03>, "buffer_load_format_xyzw", VReg_128
927 defm BUFFER_STORE_FORMAT_X : MUBUF_Store_Helper <
928 mubuf<0x04>, "buffer_store_format_x", VGPR_32
930 defm BUFFER_STORE_FORMAT_XY : MUBUF_Store_Helper <
931 mubuf<0x05>, "buffer_store_format_xy", VReg_64
933 defm BUFFER_STORE_FORMAT_XYZ : MUBUF_Store_Helper <
934 mubuf<0x06>, "buffer_store_format_xyz", VReg_96
936 defm BUFFER_STORE_FORMAT_XYZW : MUBUF_Store_Helper <
937 mubuf<0x07>, "buffer_store_format_xyzw", VReg_128
939 defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <
940 mubuf<0x08, 0x10>, "buffer_load_ubyte", VGPR_32, i32, az_extloadi8_global
942 defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <
943 mubuf<0x09, 0x11>, "buffer_load_sbyte", VGPR_32, i32, sextloadi8_global
945 defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <
946 mubuf<0x0a, 0x12>, "buffer_load_ushort", VGPR_32, i32, az_extloadi16_global
948 defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <
949 mubuf<0x0b, 0x13>, "buffer_load_sshort", VGPR_32, i32, sextloadi16_global
951 defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <
952 mubuf<0x0c, 0x14>, "buffer_load_dword", VGPR_32, i32, global_load
954 defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <
955 mubuf<0x0d, 0x15>, "buffer_load_dwordx2", VReg_64, v2i32, global_load
957 defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <
958 mubuf<0x0e, 0x17>, "buffer_load_dwordx4", VReg_128, v4i32, global_load
961 defm BUFFER_STORE_BYTE : MUBUF_Store_Helper <
962 mubuf<0x18>, "buffer_store_byte", VGPR_32, i32, truncstorei8_global
965 defm BUFFER_STORE_SHORT : MUBUF_Store_Helper <
966 mubuf<0x1a>, "buffer_store_short", VGPR_32, i32, truncstorei16_global
969 defm BUFFER_STORE_DWORD : MUBUF_Store_Helper <
970 mubuf<0x1c>, "buffer_store_dword", VGPR_32, i32, global_store
973 defm BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper <
974 mubuf<0x1d>, "buffer_store_dwordx2", VReg_64, v2i32, global_store
977 defm BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper <
978 mubuf<0x1e, 0x1f>, "buffer_store_dwordx4", VReg_128, v4i32, global_store
981 defm BUFFER_ATOMIC_SWAP : MUBUF_Atomic <
982 mubuf<0x30, 0x40>, "buffer_atomic_swap", VGPR_32, i32, atomic_swap_global
984 //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <mubuf<0x31, 0x41>, "buffer_atomic_cmpswap", []>;
985 defm BUFFER_ATOMIC_ADD : MUBUF_Atomic <
986 mubuf<0x32, 0x42>, "buffer_atomic_add", VGPR_32, i32, atomic_add_global
988 defm BUFFER_ATOMIC_SUB : MUBUF_Atomic <
989 mubuf<0x33, 0x43>, "buffer_atomic_sub", VGPR_32, i32, atomic_sub_global
991 //def BUFFER_ATOMIC_RSUB : MUBUF_ <mubuf<0x34>, "buffer_atomic_rsub", []>; // isn't on CI & VI
992 defm BUFFER_ATOMIC_SMIN : MUBUF_Atomic <
993 mubuf<0x35, 0x44>, "buffer_atomic_smin", VGPR_32, i32, atomic_min_global
995 defm BUFFER_ATOMIC_UMIN : MUBUF_Atomic <
996 mubuf<0x36, 0x45>, "buffer_atomic_umin", VGPR_32, i32, atomic_umin_global
998 defm BUFFER_ATOMIC_SMAX : MUBUF_Atomic <
999 mubuf<0x37, 0x46>, "buffer_atomic_smax", VGPR_32, i32, atomic_max_global
1001 defm BUFFER_ATOMIC_UMAX : MUBUF_Atomic <
1002 mubuf<0x38, 0x47>, "buffer_atomic_umax", VGPR_32, i32, atomic_umax_global
1004 defm BUFFER_ATOMIC_AND : MUBUF_Atomic <
1005 mubuf<0x39, 0x48>, "buffer_atomic_and", VGPR_32, i32, atomic_and_global
1007 defm BUFFER_ATOMIC_OR : MUBUF_Atomic <
1008 mubuf<0x3a, 0x49>, "buffer_atomic_or", VGPR_32, i32, atomic_or_global
1010 defm BUFFER_ATOMIC_XOR : MUBUF_Atomic <
1011 mubuf<0x3b, 0x4a>, "buffer_atomic_xor", VGPR_32, i32, atomic_xor_global
1013 //def BUFFER_ATOMIC_INC : MUBUF_ <mubuf<0x3c, 0x4b>, "buffer_atomic_inc", []>;
1014 //def BUFFER_ATOMIC_DEC : MUBUF_ <mubuf<0x3d, 0x4c>, "buffer_atomic_dec", []>;
1015 //def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <mubuf<0x3e>, "buffer_atomic_fcmpswap", []>; // isn't on VI
1016 //def BUFFER_ATOMIC_FMIN : MUBUF_ <mubuf<0x3f>, "buffer_atomic_fmin", []>; // isn't on VI
1017 //def BUFFER_ATOMIC_FMAX : MUBUF_ <mubuf<0x40>, "buffer_atomic_fmax", []>; // isn't on VI
1018 //def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <mubuf<0x50, 0x60>, "buffer_atomic_swap_x2", []>;
1019 //def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <mubuf<0x51, 0x61>, "buffer_atomic_cmpswap_x2", []>;
1020 //def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <mubuf<0x52, 0x62>, "buffer_atomic_add_x2", []>;
1021 //def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <mubuf<0x53, 0x63>, "buffer_atomic_sub_x2", []>;
1022 //def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <mubuf<0x54>, "buffer_atomic_rsub_x2", []>; // isn't on CI & VI
1023 //def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <mubuf<0x55, 0x64>, "buffer_atomic_smin_x2", []>;
1024 //def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <mubuf<0x56, 0x65>, "buffer_atomic_umin_x2", []>;
1025 //def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <mubuf<0x57, 0x66>, "buffer_atomic_smax_x2", []>;
1026 //def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <mubuf<0x58, 0x67>, "buffer_atomic_umax_x2", []>;
1027 //def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <mubuf<0x59, 0x68>, "buffer_atomic_and_x2", []>;
1028 //def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <mubuf<0x5a, 0x69>, "buffer_atomic_or_x2", []>;
1029 //def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <mubuf<0x5b, 0x6a>, "buffer_atomic_xor_x2", []>;
1030 //def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <mubuf<0x5c, 0x6b>, "buffer_atomic_inc_x2", []>;
1031 //def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <mubuf<0x5d, 0x6c>, "buffer_atomic_dec_x2", []>;
1032 //def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <mubuf<0x5e>, "buffer_atomic_fcmpswap_x2", []>; // isn't on VI
1033 //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <mubuf<0x5f>, "buffer_atomic_fmin_x2", []>; // isn't on VI
1034 //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <mubuf<0x60>, "buffer_atomic_fmax_x2", []>; // isn't on VI
1036 let SubtargetPredicate = isSI in {
1037 defm BUFFER_WBINVL1_SC : MUBUF_Invalidate <mubuf<0x70>, "buffer_wbinvl1_sc", int_amdgcn_buffer_wbinvl1_sc>; // isn't on CI & VI
1040 defm BUFFER_WBINVL1 : MUBUF_Invalidate <mubuf<0x71, 0x3e>, "buffer_wbinvl1", int_amdgcn_buffer_wbinvl1>;
1042 //===----------------------------------------------------------------------===//
1043 // MTBUF Instructions
1044 //===----------------------------------------------------------------------===//
1046 //def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "tbuffer_load_format_x", []>;
1047 //def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "tbuffer_load_format_xy", []>;
1048 //def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "tbuffer_load_format_xyz", []>;
1049 defm TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "tbuffer_load_format_xyzw", VReg_128>;
1050 defm TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "tbuffer_store_format_x", VGPR_32>;
1051 defm TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "tbuffer_store_format_xy", VReg_64>;
1052 defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "tbuffer_store_format_xyz", VReg_128>;
1053 defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "tbuffer_store_format_xyzw", VReg_128>;
1055 //===----------------------------------------------------------------------===//
1056 // MIMG Instructions
1057 //===----------------------------------------------------------------------===//
1059 defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "image_load">;
1060 defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "image_load_mip">;
1061 //def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"image_load_pck", 0x00000002>;
1062 //def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"image_load_pck_sgn", 0x00000003>;
1063 //def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"image_load_mip_pck", 0x00000004>;
1064 //def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"image_load_mip_pck_sgn", 0x00000005>;
1065 //def IMAGE_STORE : MIMG_NoPattern_ <"image_store", 0x00000008>;
1066 //def IMAGE_STORE_MIP : MIMG_NoPattern_ <"image_store_mip", 0x00000009>;
1067 //def IMAGE_STORE_PCK : MIMG_NoPattern_ <"image_store_pck", 0x0000000a>;
1068 //def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"image_store_mip_pck", 0x0000000b>;
1069 defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "image_get_resinfo">;
1070 //def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"image_atomic_swap", 0x0000000f>;
1071 //def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"image_atomic_cmpswap", 0x00000010>;
1072 //def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"image_atomic_add", 0x00000011>;
1073 //def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"image_atomic_sub", 0x00000012>;
1074 //def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"image_atomic_rsub", 0x00000013>;
1075 //def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"image_atomic_smin", 0x00000014>;
1076 //def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"image_atomic_umin", 0x00000015>;
1077 //def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"image_atomic_smax", 0x00000016>;
1078 //def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"image_atomic_umax", 0x00000017>;
1079 //def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"image_atomic_and", 0x00000018>;
1080 //def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"image_atomic_or", 0x00000019>;
1081 //def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"image_atomic_xor", 0x0000001a>;
1082 //def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"image_atomic_inc", 0x0000001b>;
1083 //def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"image_atomic_dec", 0x0000001c>;
1084 //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"image_atomic_fcmpswap", 0x0000001d>;
1085 //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"image_atomic_fmin", 0x0000001e>;
1086 //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"image_atomic_fmax", 0x0000001f>;
1087 defm IMAGE_SAMPLE : MIMG_Sampler_WQM <0x00000020, "image_sample">;
1088 defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <0x00000021, "image_sample_cl">;
1089 defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "image_sample_d">;
1090 defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, "image_sample_d_cl">;
1091 defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "image_sample_l">;
1092 defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <0x00000025, "image_sample_b">;
1093 defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <0x00000026, "image_sample_b_cl">;
1094 defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, "image_sample_lz">;
1095 defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <0x00000028, "image_sample_c">;
1096 defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <0x00000029, "image_sample_c_cl">;
1097 defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "image_sample_c_d">;
1098 defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, "image_sample_c_d_cl">;
1099 defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "image_sample_c_l">;
1100 defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <0x0000002d, "image_sample_c_b">;
1101 defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <0x0000002e, "image_sample_c_b_cl">;
1102 defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, "image_sample_c_lz">;
1103 defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <0x00000030, "image_sample_o">;
1104 defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <0x00000031, "image_sample_cl_o">;
1105 defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, "image_sample_d_o">;
1106 defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, "image_sample_d_cl_o">;
1107 defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, "image_sample_l_o">;
1108 defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <0x00000035, "image_sample_b_o">;
1109 defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <0x00000036, "image_sample_b_cl_o">;
1110 defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, "image_sample_lz_o">;
1111 defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <0x00000038, "image_sample_c_o">;
1112 defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <0x00000039, "image_sample_c_cl_o">;
1113 defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, "image_sample_c_d_o">;
1114 defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, "image_sample_c_d_cl_o">;
1115 defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, "image_sample_c_l_o">;
1116 defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <0x0000003d, "image_sample_c_b_o">;
1117 defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <0x0000003e, "image_sample_c_b_cl_o">;
1118 defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, "image_sample_c_lz_o">;
1119 defm IMAGE_GATHER4 : MIMG_Gather_WQM <0x00000040, "image_gather4">;
1120 defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <0x00000041, "image_gather4_cl">;
1121 defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, "image_gather4_l">;
1122 defm IMAGE_GATHER4_B : MIMG_Gather_WQM <0x00000045, "image_gather4_b">;
1123 defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <0x00000046, "image_gather4_b_cl">;
1124 defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, "image_gather4_lz">;
1125 defm IMAGE_GATHER4_C : MIMG_Gather_WQM <0x00000048, "image_gather4_c">;
1126 defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <0x00000049, "image_gather4_c_cl">;
1127 defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, "image_gather4_c_l">;
1128 defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <0x0000004d, "image_gather4_c_b">;
1129 defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <0x0000004e, "image_gather4_c_b_cl">;
1130 defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, "image_gather4_c_lz">;
1131 defm IMAGE_GATHER4_O : MIMG_Gather_WQM <0x00000050, "image_gather4_o">;
1132 defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <0x00000051, "image_gather4_cl_o">;
1133 defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, "image_gather4_l_o">;
1134 defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <0x00000055, "image_gather4_b_o">;
1135 defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, "image_gather4_b_cl_o">;
1136 defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, "image_gather4_lz_o">;
1137 defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <0x00000058, "image_gather4_c_o">;
1138 defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <0x00000059, "image_gather4_c_cl_o">;
1139 defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, "image_gather4_c_l_o">;
1140 defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <0x0000005d, "image_gather4_c_b_o">;
1141 defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <0x0000005e, "image_gather4_c_b_cl_o">;
1142 defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, "image_gather4_c_lz_o">;
1143 defm IMAGE_GET_LOD : MIMG_Sampler_WQM <0x00000060, "image_get_lod">;
1144 defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, "image_sample_cd">;
1145 defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, "image_sample_cd_cl">;
1146 defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, "image_sample_c_cd">;
1147 defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, "image_sample_c_cd_cl">;
1148 defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, "image_sample_cd_o">;
1149 defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, "image_sample_cd_cl_o">;
1150 defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, "image_sample_c_cd_o">;
1151 defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, "image_sample_c_cd_cl_o">;
1152 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>;
1153 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>;
1155 //===----------------------------------------------------------------------===//
1156 // VOP1 Instructions
1157 //===----------------------------------------------------------------------===//
1159 let vdst = 0, src0 = 0 in {
1160 defm V_NOP : VOP1_m <vop1<0x0>, (outs), (ins), "v_nop", [], "v_nop">;
1163 let isMoveImm = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1164 defm V_MOV_B32 : VOP1Inst <vop1<0x1>, "v_mov_b32", VOP_I32_I32>;
1165 } // End isMoveImm = 1
1167 let Uses = [EXEC] in {
1169 // FIXME: Specify SchedRW for READFIRSTLANE_B32
1171 def V_READFIRSTLANE_B32 : VOP1 <
1173 (outs SReg_32:$vdst),
1174 (ins VGPR_32:$src0),
1175 "v_readfirstlane_b32 $vdst, $src0",
1181 let SchedRW = [WriteQuarterRate32] in {
1183 defm V_CVT_I32_F64 : VOP1Inst <vop1<0x3>, "v_cvt_i32_f64",
1184 VOP_I32_F64, fp_to_sint
1186 defm V_CVT_F64_I32 : VOP1Inst <vop1<0x4>, "v_cvt_f64_i32",
1187 VOP_F64_I32, sint_to_fp
1189 defm V_CVT_F32_I32 : VOP1Inst <vop1<0x5>, "v_cvt_f32_i32",
1190 VOP_F32_I32, sint_to_fp
1192 defm V_CVT_F32_U32 : VOP1Inst <vop1<0x6>, "v_cvt_f32_u32",
1193 VOP_F32_I32, uint_to_fp
1195 defm V_CVT_U32_F32 : VOP1Inst <vop1<0x7>, "v_cvt_u32_f32",
1196 VOP_I32_F32, fp_to_uint
1198 defm V_CVT_I32_F32 : VOP1Inst <vop1<0x8>, "v_cvt_i32_f32",
1199 VOP_I32_F32, fp_to_sint
1201 defm V_CVT_F16_F32 : VOP1Inst <vop1<0xa>, "v_cvt_f16_f32",
1202 VOP_I32_F32, fp_to_f16
1204 defm V_CVT_F32_F16 : VOP1Inst <vop1<0xb>, "v_cvt_f32_f16",
1205 VOP_F32_I32, f16_to_fp
1207 defm V_CVT_RPI_I32_F32 : VOP1Inst <vop1<0xc>, "v_cvt_rpi_i32_f32",
1208 VOP_I32_F32, cvt_rpi_i32_f32>;
1209 defm V_CVT_FLR_I32_F32 : VOP1Inst <vop1<0xd>, "v_cvt_flr_i32_f32",
1210 VOP_I32_F32, cvt_flr_i32_f32>;
1211 defm V_CVT_OFF_F32_I4 : VOP1Inst <vop1<0x0e>, "v_cvt_off_f32_i4", VOP_F32_I32>;
1212 defm V_CVT_F32_F64 : VOP1Inst <vop1<0xf>, "v_cvt_f32_f64",
1215 defm V_CVT_F64_F32 : VOP1Inst <vop1<0x10>, "v_cvt_f64_f32",
1216 VOP_F64_F32, fextend
1218 defm V_CVT_F32_UBYTE0 : VOP1Inst <vop1<0x11>, "v_cvt_f32_ubyte0",
1219 VOP_F32_I32, AMDGPUcvt_f32_ubyte0
1221 defm V_CVT_F32_UBYTE1 : VOP1Inst <vop1<0x12>, "v_cvt_f32_ubyte1",
1222 VOP_F32_I32, AMDGPUcvt_f32_ubyte1
1224 defm V_CVT_F32_UBYTE2 : VOP1Inst <vop1<0x13>, "v_cvt_f32_ubyte2",
1225 VOP_F32_I32, AMDGPUcvt_f32_ubyte2
1227 defm V_CVT_F32_UBYTE3 : VOP1Inst <vop1<0x14>, "v_cvt_f32_ubyte3",
1228 VOP_F32_I32, AMDGPUcvt_f32_ubyte3
1230 defm V_CVT_U32_F64 : VOP1Inst <vop1<0x15>, "v_cvt_u32_f64",
1231 VOP_I32_F64, fp_to_uint
1233 defm V_CVT_F64_U32 : VOP1Inst <vop1<0x16>, "v_cvt_f64_u32",
1234 VOP_F64_I32, uint_to_fp
1237 } // let SchedRW = [WriteQuarterRate32]
1239 defm V_FRACT_F32 : VOP1Inst <vop1<0x20, 0x1b>, "v_fract_f32",
1240 VOP_F32_F32, AMDGPUfract
1242 defm V_TRUNC_F32 : VOP1Inst <vop1<0x21, 0x1c>, "v_trunc_f32",
1245 defm V_CEIL_F32 : VOP1Inst <vop1<0x22, 0x1d>, "v_ceil_f32",
1248 defm V_RNDNE_F32 : VOP1Inst <vop1<0x23, 0x1e>, "v_rndne_f32",
1251 defm V_FLOOR_F32 : VOP1Inst <vop1<0x24, 0x1f>, "v_floor_f32",
1254 defm V_EXP_F32 : VOP1Inst <vop1<0x25, 0x20>, "v_exp_f32",
1258 let SchedRW = [WriteQuarterRate32] in {
1260 defm V_LOG_F32 : VOP1Inst <vop1<0x27, 0x21>, "v_log_f32",
1263 defm V_RCP_F32 : VOP1Inst <vop1<0x2a, 0x22>, "v_rcp_f32",
1264 VOP_F32_F32, AMDGPUrcp
1266 defm V_RCP_IFLAG_F32 : VOP1Inst <vop1<0x2b, 0x23>, "v_rcp_iflag_f32",
1269 defm V_RSQ_F32 : VOP1Inst <vop1<0x2e, 0x24>, "v_rsq_f32",
1270 VOP_F32_F32, AMDGPUrsq
1273 } //let SchedRW = [WriteQuarterRate32]
1275 let SchedRW = [WriteDouble] in {
1277 defm V_RCP_F64 : VOP1Inst <vop1<0x2f, 0x25>, "v_rcp_f64",
1278 VOP_F64_F64, AMDGPUrcp
1280 defm V_RSQ_F64 : VOP1Inst <vop1<0x31, 0x26>, "v_rsq_f64",
1281 VOP_F64_F64, AMDGPUrsq
1284 } // let SchedRW = [WriteDouble];
1286 defm V_SQRT_F32 : VOP1Inst <vop1<0x33, 0x27>, "v_sqrt_f32",
1290 let SchedRW = [WriteDouble] in {
1292 defm V_SQRT_F64 : VOP1Inst <vop1<0x34, 0x28>, "v_sqrt_f64",
1296 } // End SchedRW = [WriteDouble]
1298 let SchedRW = [WriteQuarterRate32] in {
1300 defm V_SIN_F32 : VOP1Inst <vop1<0x35, 0x29>, "v_sin_f32",
1301 VOP_F32_F32, AMDGPUsin
1303 defm V_COS_F32 : VOP1Inst <vop1<0x36, 0x2a>, "v_cos_f32",
1304 VOP_F32_F32, AMDGPUcos
1307 } // End SchedRW = [WriteQuarterRate32]
1309 defm V_NOT_B32 : VOP1Inst <vop1<0x37, 0x2b>, "v_not_b32", VOP_I32_I32>;
1310 defm V_BFREV_B32 : VOP1Inst <vop1<0x38, 0x2c>, "v_bfrev_b32", VOP_I32_I32>;
1311 defm V_FFBH_U32 : VOP1Inst <vop1<0x39, 0x2d>, "v_ffbh_u32", VOP_I32_I32>;
1312 defm V_FFBL_B32 : VOP1Inst <vop1<0x3a, 0x2e>, "v_ffbl_b32", VOP_I32_I32>;
1313 defm V_FFBH_I32 : VOP1Inst <vop1<0x3b, 0x2f>, "v_ffbh_i32", VOP_I32_I32>;
1314 defm V_FREXP_EXP_I32_F64 : VOP1Inst <vop1<0x3c,0x30>, "v_frexp_exp_i32_f64",
1318 let SchedRW = [WriteDoubleAdd] in {
1319 defm V_FREXP_MANT_F64 : VOP1Inst <vop1<0x3d, 0x31>, "v_frexp_mant_f64",
1323 defm V_FRACT_F64 : VOP1Inst <vop1<0x3e, 0x32>, "v_fract_f64",
1326 } // End SchedRW = [WriteDoubleAdd]
1329 defm V_FREXP_EXP_I32_F32 : VOP1Inst <vop1<0x3f, 0x33>, "v_frexp_exp_i32_f32",
1332 defm V_FREXP_MANT_F32 : VOP1Inst <vop1<0x40, 0x34>, "v_frexp_mant_f32",
1335 let vdst = 0, src0 = 0 in {
1336 defm V_CLREXCP : VOP1_m <vop1<0x41,0x35>, (outs), (ins), "v_clrexcp", [],
1340 defm V_MOVRELD_B32 : VOP1Inst <vop1<0x42, 0x36>, "v_movreld_b32", VOP_I32_I32>;
1341 defm V_MOVRELS_B32 : VOP1Inst <vop1<0x43, 0x37>, "v_movrels_b32", VOP_I32_I32>;
1342 defm V_MOVRELSD_B32 : VOP1Inst <vop1<0x44, 0x38>, "v_movrelsd_b32", VOP_I32_I32>;
1344 // These instruction only exist on SI and CI
1345 let SubtargetPredicate = isSICI in {
1347 let SchedRW = [WriteQuarterRate32] in {
1349 defm V_MOV_FED_B32 : VOP1InstSI <vop1<0x9>, "v_mov_fed_b32", VOP_I32_I32>;
1350 defm V_LOG_CLAMP_F32 : VOP1InstSI <vop1<0x26>, "v_log_clamp_f32", VOP_F32_F32>;
1351 defm V_RCP_CLAMP_F32 : VOP1InstSI <vop1<0x28>, "v_rcp_clamp_f32", VOP_F32_F32>;
1352 defm V_RCP_LEGACY_F32 : VOP1InstSI <vop1<0x29>, "v_rcp_legacy_f32", VOP_F32_F32>;
1353 defm V_RSQ_CLAMP_F32 : VOP1InstSI <vop1<0x2c>, "v_rsq_clamp_f32",
1354 VOP_F32_F32, AMDGPUrsq_clamped
1356 defm V_RSQ_LEGACY_F32 : VOP1InstSI <vop1<0x2d>, "v_rsq_legacy_f32",
1357 VOP_F32_F32, AMDGPUrsq_legacy
1360 } // End SchedRW = [WriteQuarterRate32]
1362 let SchedRW = [WriteDouble] in {
1364 defm V_RCP_CLAMP_F64 : VOP1InstSI <vop1<0x30>, "v_rcp_clamp_f64", VOP_F64_F64>;
1365 defm V_RSQ_CLAMP_F64 : VOP1InstSI <vop1<0x32>, "v_rsq_clamp_f64",
1366 VOP_F64_F64, AMDGPUrsq_clamped
1369 } // End SchedRW = [WriteDouble]
1371 } // End SubtargetPredicate = isSICI
1373 //===----------------------------------------------------------------------===//
1374 // VINTRP Instructions
1375 //===----------------------------------------------------------------------===//
1377 let Uses = [M0, EXEC] in {
1379 // FIXME: Specify SchedRW for VINTRP insturctions.
1381 multiclass V_INTERP_P1_F32_m : VINTRP_m <
1383 (outs VGPR_32:$dst),
1384 (ins VGPR_32:$i, i32imm:$attr_chan, i32imm:$attr),
1385 "v_interp_p1_f32 $dst, $i, $attr_chan, $attr, [m0]",
1386 [(set f32:$dst, (AMDGPUinterp_p1 i32:$i, (i32 imm:$attr_chan),
1390 let OtherPredicates = [has32BankLDS] in {
1392 defm V_INTERP_P1_F32 : V_INTERP_P1_F32_m;
1394 } // End OtherPredicates = [has32BankLDS]
1396 let OtherPredicates = [has16BankLDS], Constraints = "@earlyclobber $dst" in {
1398 defm V_INTERP_P1_F32_16bank : V_INTERP_P1_F32_m;
1400 } // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $dst"
1402 let DisableEncoding = "$src0", Constraints = "$src0 = $dst" in {
1404 defm V_INTERP_P2_F32 : VINTRP_m <
1406 (outs VGPR_32:$dst),
1407 (ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr),
1408 "v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [m0]",
1409 [(set f32:$dst, (AMDGPUinterp_p2 f32:$src0, i32:$j, (i32 imm:$attr_chan),
1410 (i32 imm:$attr)))]>;
1412 } // End DisableEncoding = "$src0", Constraints = "$src0 = $dst"
1414 defm V_INTERP_MOV_F32 : VINTRP_m <
1416 (outs VGPR_32:$dst),
1417 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr),
1418 "v_interp_mov_f32 $dst, $src0, $attr_chan, $attr, [m0]",
1419 [(set f32:$dst, (AMDGPUinterp_mov (i32 imm:$src0), (i32 imm:$attr_chan),
1420 (i32 imm:$attr)))]>;
1422 } // End Uses = [M0, EXEC]
1424 //===----------------------------------------------------------------------===//
1425 // VOP2 Instructions
1426 //===----------------------------------------------------------------------===//
1428 multiclass V_CNDMASK <vop2 op, string name> {
1429 defm _e32 : VOP2_m <
1430 op, VOP_CNDMASK.Outs, VOP_CNDMASK.Ins32, VOP_CNDMASK.Asm32, [],
1433 defm _e64 : VOP3_m <
1434 op, VOP_CNDMASK.Outs, VOP_CNDMASK.Ins64,
1435 name#!cast<string>(VOP_CNDMASK.Asm64), [], name, 3>;
1438 defm V_CNDMASK_B32 : V_CNDMASK<vop2<0x0>, "v_cndmask_b32">;
1440 let isCommutable = 1 in {
1441 defm V_ADD_F32 : VOP2Inst <vop2<0x3, 0x1>, "v_add_f32",
1442 VOP_F32_F32_F32, fadd
1445 defm V_SUB_F32 : VOP2Inst <vop2<0x4, 0x2>, "v_sub_f32", VOP_F32_F32_F32, fsub>;
1446 defm V_SUBREV_F32 : VOP2Inst <vop2<0x5, 0x3>, "v_subrev_f32",
1447 VOP_F32_F32_F32, null_frag, "v_sub_f32"
1449 } // End isCommutable = 1
1451 let isCommutable = 1 in {
1453 defm V_MUL_LEGACY_F32 : VOP2Inst <vop2<0x7, 0x4>, "v_mul_legacy_f32",
1454 VOP_F32_F32_F32, int_AMDGPU_mul
1457 defm V_MUL_F32 : VOP2Inst <vop2<0x8, 0x5>, "v_mul_f32",
1458 VOP_F32_F32_F32, fmul
1461 defm V_MUL_I32_I24 : VOP2Inst <vop2<0x9, 0x6>, "v_mul_i32_i24",
1462 VOP_I32_I32_I32, AMDGPUmul_i24
1465 defm V_MUL_HI_I32_I24 : VOP2Inst <vop2<0xa,0x7>, "v_mul_hi_i32_i24",
1469 defm V_MUL_U32_U24 : VOP2Inst <vop2<0xb, 0x8>, "v_mul_u32_u24",
1470 VOP_I32_I32_I32, AMDGPUmul_u24
1473 defm V_MUL_HI_U32_U24 : VOP2Inst <vop2<0xc,0x9>, "v_mul_hi_u32_u24",
1477 defm V_MIN_F32 : VOP2Inst <vop2<0xf, 0xa>, "v_min_f32", VOP_F32_F32_F32,
1479 defm V_MAX_F32 : VOP2Inst <vop2<0x10, 0xb>, "v_max_f32", VOP_F32_F32_F32,
1481 defm V_MIN_I32 : VOP2Inst <vop2<0x11, 0xc>, "v_min_i32", VOP_I32_I32_I32>;
1482 defm V_MAX_I32 : VOP2Inst <vop2<0x12, 0xd>, "v_max_i32", VOP_I32_I32_I32>;
1483 defm V_MIN_U32 : VOP2Inst <vop2<0x13, 0xe>, "v_min_u32", VOP_I32_I32_I32>;
1484 defm V_MAX_U32 : VOP2Inst <vop2<0x14, 0xf>, "v_max_u32", VOP_I32_I32_I32>;
1486 defm V_LSHRREV_B32 : VOP2Inst <
1487 vop2<0x16, 0x10>, "v_lshrrev_b32", VOP_I32_I32_I32, null_frag,
1491 defm V_ASHRREV_I32 : VOP2Inst <
1492 vop2<0x18, 0x11>, "v_ashrrev_i32", VOP_I32_I32_I32, null_frag,
1496 defm V_LSHLREV_B32 : VOP2Inst <
1497 vop2<0x1a, 0x12>, "v_lshlrev_b32", VOP_I32_I32_I32, null_frag,
1501 defm V_AND_B32 : VOP2Inst <vop2<0x1b, 0x13>, "v_and_b32", VOP_I32_I32_I32>;
1502 defm V_OR_B32 : VOP2Inst <vop2<0x1c, 0x14>, "v_or_b32", VOP_I32_I32_I32>;
1503 defm V_XOR_B32 : VOP2Inst <vop2<0x1d, 0x15>, "v_xor_b32", VOP_I32_I32_I32>;
1505 let Constraints = "$dst = $src2", DisableEncoding="$src2",
1506 isConvertibleToThreeAddress = 1 in {
1507 defm V_MAC_F32 : VOP2Inst <vop2<0x1f, 0x16>, "v_mac_f32", VOP_MAC>;
1509 } // End isCommutable = 1
1511 defm V_MADMK_F32 : VOP2MADK <vop2<0x20, 0x17>, "v_madmk_f32">;
1513 let isCommutable = 1 in {
1514 defm V_MADAK_F32 : VOP2MADK <vop2<0x21, 0x18>, "v_madak_f32">;
1515 } // End isCommutable = 1
1517 let isCommutable = 1 in {
1518 // No patterns so that the scalar instructions are always selected.
1519 // The scalar versions will be replaced with vector when needed later.
1521 // V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in VI,
1522 // but the VI instructions behave the same as the SI versions.
1523 defm V_ADD_I32 : VOP2bInst <vop2<0x25, 0x19>, "v_add_i32",
1524 VOP2b_I32_I1_I32_I32
1526 defm V_SUB_I32 : VOP2bInst <vop2<0x26, 0x1a>, "v_sub_i32", VOP2b_I32_I1_I32_I32>;
1528 defm V_SUBREV_I32 : VOP2bInst <vop2<0x27, 0x1b>, "v_subrev_i32",
1529 VOP2b_I32_I1_I32_I32, null_frag, "v_sub_i32"
1532 defm V_ADDC_U32 : VOP2bInst <vop2<0x28, 0x1c>, "v_addc_u32",
1533 VOP2b_I32_I1_I32_I32_I1
1535 defm V_SUBB_U32 : VOP2bInst <vop2<0x29, 0x1d>, "v_subb_u32",
1536 VOP2b_I32_I1_I32_I32_I1
1538 defm V_SUBBREV_U32 : VOP2bInst <vop2<0x2a, 0x1e>, "v_subbrev_u32",
1539 VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32"
1542 } // End isCommutable = 1
1544 defm V_READLANE_B32 : VOP2SI_3VI_m <
1545 vop3 <0x001, 0x289>,
1547 (outs SReg_32:$vdst),
1548 (ins VGPR_32:$src0, SCSrc_32:$src1),
1549 "v_readlane_b32 $vdst, $src0, $src1"
1552 defm V_WRITELANE_B32 : VOP2SI_3VI_m <
1553 vop3 <0x002, 0x28a>,
1555 (outs VGPR_32:$vdst),
1556 (ins SReg_32:$src0, SCSrc_32:$src1),
1557 "v_writelane_b32 $vdst, $src0, $src1"
1560 // These instructions only exist on SI and CI
1561 let SubtargetPredicate = isSICI in {
1563 let isCommutable = 1 in {
1564 defm V_MAC_LEGACY_F32 : VOP2InstSI <vop2<0x6>, "v_mac_legacy_f32",
1567 } // End isCommutable = 1
1569 defm V_MIN_LEGACY_F32 : VOP2InstSI <vop2<0xd>, "v_min_legacy_f32",
1570 VOP_F32_F32_F32, AMDGPUfmin_legacy
1572 defm V_MAX_LEGACY_F32 : VOP2InstSI <vop2<0xe>, "v_max_legacy_f32",
1573 VOP_F32_F32_F32, AMDGPUfmax_legacy
1576 let isCommutable = 1 in {
1577 defm V_LSHR_B32 : VOP2InstSI <vop2<0x15>, "v_lshr_b32", VOP_I32_I32_I32>;
1578 defm V_ASHR_I32 : VOP2InstSI <vop2<0x17>, "v_ashr_i32", VOP_I32_I32_I32>;
1579 defm V_LSHL_B32 : VOP2InstSI <vop2<0x19>, "v_lshl_b32", VOP_I32_I32_I32>;
1580 } // End isCommutable = 1
1581 } // End let SubtargetPredicate = SICI
1583 defm V_BFM_B32 : VOP2_VI3_Inst <vop23<0x1e, 0x293>, "v_bfm_b32",
1586 defm V_BCNT_U32_B32 : VOP2_VI3_Inst <vop23<0x22, 0x28b>, "v_bcnt_u32_b32",
1589 defm V_MBCNT_LO_U32_B32 : VOP2_VI3_Inst <vop23<0x23, 0x28c>, "v_mbcnt_lo_u32_b32",
1592 defm V_MBCNT_HI_U32_B32 : VOP2_VI3_Inst <vop23<0x24, 0x28d>, "v_mbcnt_hi_u32_b32",
1595 defm V_LDEXP_F32 : VOP2_VI3_Inst <vop23<0x2b, 0x288>, "v_ldexp_f32",
1596 VOP_F32_F32_I32, AMDGPUldexp
1599 defm V_CVT_PKACCUM_U8_F32 : VOP2_VI3_Inst <vop23<0x2c, 0x1f0>, "v_cvt_pkaccum_u8_f32",
1600 VOP_I32_F32_I32>; // TODO: set "Uses = dst"
1602 defm V_CVT_PKNORM_I16_F32 : VOP2_VI3_Inst <vop23<0x2d, 0x294>, "v_cvt_pknorm_i16_f32",
1605 defm V_CVT_PKNORM_U16_F32 : VOP2_VI3_Inst <vop23<0x2e, 0x295>, "v_cvt_pknorm_u16_f32",
1608 defm V_CVT_PKRTZ_F16_F32 : VOP2_VI3_Inst <vop23<0x2f, 0x296>, "v_cvt_pkrtz_f16_f32",
1609 VOP_I32_F32_F32, int_SI_packf16
1611 defm V_CVT_PK_U16_U32 : VOP2_VI3_Inst <vop23<0x30, 0x297>, "v_cvt_pk_u16_u32",
1614 defm V_CVT_PK_I16_I32 : VOP2_VI3_Inst <vop23<0x31, 0x298>, "v_cvt_pk_i16_i32",
1618 //===----------------------------------------------------------------------===//
1619 // VOP3 Instructions
1620 //===----------------------------------------------------------------------===//
1622 let isCommutable = 1 in {
1623 defm V_MAD_LEGACY_F32 : VOP3Inst <vop3<0x140, 0x1c0>, "v_mad_legacy_f32",
1627 defm V_MAD_F32 : VOP3Inst <vop3<0x141, 0x1c1>, "v_mad_f32",
1628 VOP_F32_F32_F32_F32, fmad
1631 defm V_MAD_I32_I24 : VOP3Inst <vop3<0x142, 0x1c2>, "v_mad_i32_i24",
1632 VOP_I32_I32_I32_I32, AMDGPUmad_i24
1634 defm V_MAD_U32_U24 : VOP3Inst <vop3<0x143, 0x1c3>, "v_mad_u32_u24",
1635 VOP_I32_I32_I32_I32, AMDGPUmad_u24
1637 } // End isCommutable = 1
1639 defm V_CUBEID_F32 : VOP3Inst <vop3<0x144, 0x1c4>, "v_cubeid_f32",
1642 defm V_CUBESC_F32 : VOP3Inst <vop3<0x145, 0x1c5>, "v_cubesc_f32",
1645 defm V_CUBETC_F32 : VOP3Inst <vop3<0x146, 0x1c6>, "v_cubetc_f32",
1648 defm V_CUBEMA_F32 : VOP3Inst <vop3<0x147, 0x1c7>, "v_cubema_f32",
1652 defm V_BFE_U32 : VOP3Inst <vop3<0x148, 0x1c8>, "v_bfe_u32",
1653 VOP_I32_I32_I32_I32, AMDGPUbfe_u32
1655 defm V_BFE_I32 : VOP3Inst <vop3<0x149, 0x1c9>, "v_bfe_i32",
1656 VOP_I32_I32_I32_I32, AMDGPUbfe_i32
1659 defm V_BFI_B32 : VOP3Inst <vop3<0x14a, 0x1ca>, "v_bfi_b32",
1660 VOP_I32_I32_I32_I32, AMDGPUbfi
1663 let isCommutable = 1 in {
1664 defm V_FMA_F32 : VOP3Inst <vop3<0x14b, 0x1cb>, "v_fma_f32",
1665 VOP_F32_F32_F32_F32, fma
1667 defm V_FMA_F64 : VOP3Inst <vop3<0x14c, 0x1cc>, "v_fma_f64",
1668 VOP_F64_F64_F64_F64, fma
1670 } // End isCommutable = 1
1672 //def V_LERP_U8 : VOP3_U8 <0x0000014d, "v_lerp_u8", []>;
1673 defm V_ALIGNBIT_B32 : VOP3Inst <vop3<0x14e, 0x1ce>, "v_alignbit_b32",
1676 defm V_ALIGNBYTE_B32 : VOP3Inst <vop3<0x14f, 0x1cf>, "v_alignbyte_b32",
1680 defm V_MIN3_F32 : VOP3Inst <vop3<0x151, 0x1d0>, "v_min3_f32",
1681 VOP_F32_F32_F32_F32, AMDGPUfmin3>;
1683 defm V_MIN3_I32 : VOP3Inst <vop3<0x152, 0x1d1>, "v_min3_i32",
1684 VOP_I32_I32_I32_I32, AMDGPUsmin3
1686 defm V_MIN3_U32 : VOP3Inst <vop3<0x153, 0x1d2>, "v_min3_u32",
1687 VOP_I32_I32_I32_I32, AMDGPUumin3
1689 defm V_MAX3_F32 : VOP3Inst <vop3<0x154, 0x1d3>, "v_max3_f32",
1690 VOP_F32_F32_F32_F32, AMDGPUfmax3
1692 defm V_MAX3_I32 : VOP3Inst <vop3<0x155, 0x1d4>, "v_max3_i32",
1693 VOP_I32_I32_I32_I32, AMDGPUsmax3
1695 defm V_MAX3_U32 : VOP3Inst <vop3<0x156, 0x1d5>, "v_max3_u32",
1696 VOP_I32_I32_I32_I32, AMDGPUumax3
1698 defm V_MED3_F32 : VOP3Inst <vop3<0x157, 0x1d6>, "v_med3_f32",
1701 defm V_MED3_I32 : VOP3Inst <vop3<0x158, 0x1d7>, "v_med3_i32",
1704 defm V_MED3_U32 : VOP3Inst <vop3<0x159, 0x1d8>, "v_med3_u32",
1708 //def V_SAD_U8 : VOP3_U8 <0x0000015a, "v_sad_u8", []>;
1709 //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "v_sad_hi_u8", []>;
1710 //def V_SAD_U16 : VOP3_U16 <0x0000015c, "v_sad_u16", []>;
1711 defm V_SAD_U32 : VOP3Inst <vop3<0x15d, 0x1dc>, "v_sad_u32",
1714 ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "v_cvt_pk_u8_f32", []>;
1715 defm V_DIV_FIXUP_F32 : VOP3Inst <
1716 vop3<0x15f, 0x1de>, "v_div_fixup_f32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup
1719 let SchedRW = [WriteDoubleAdd] in {
1721 defm V_DIV_FIXUP_F64 : VOP3Inst <
1722 vop3<0x160, 0x1df>, "v_div_fixup_f64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup
1725 } // End SchedRW = [WriteDouble]
1727 let SchedRW = [WriteDoubleAdd] in {
1728 let isCommutable = 1 in {
1730 defm V_ADD_F64 : VOP3Inst <vop3<0x164, 0x280>, "v_add_f64",
1731 VOP_F64_F64_F64, fadd
1733 defm V_MUL_F64 : VOP3Inst <vop3<0x165, 0x281>, "v_mul_f64",
1734 VOP_F64_F64_F64, fmul
1737 defm V_MIN_F64 : VOP3Inst <vop3<0x166, 0x282>, "v_min_f64",
1738 VOP_F64_F64_F64, fminnum
1740 defm V_MAX_F64 : VOP3Inst <vop3<0x167, 0x283>, "v_max_f64",
1741 VOP_F64_F64_F64, fmaxnum
1744 } // isCommutable = 1
1746 defm V_LDEXP_F64 : VOP3Inst <vop3<0x168, 0x284>, "v_ldexp_f64",
1747 VOP_F64_F64_I32, AMDGPUldexp
1750 } // let SchedRW = [WriteDoubleAdd]
1752 let isCommutable = 1, SchedRW = [WriteQuarterRate32] in {
1754 defm V_MUL_LO_U32 : VOP3Inst <vop3<0x169, 0x285>, "v_mul_lo_u32",
1757 defm V_MUL_HI_U32 : VOP3Inst <vop3<0x16a, 0x286>, "v_mul_hi_u32",
1761 defm V_MUL_LO_I32 : VOP3Inst <vop3<0x16b, 0x285>, "v_mul_lo_i32",
1764 defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c, 0x287>, "v_mul_hi_i32",
1768 } // isCommutable = 1, SchedRW = [WriteQuarterRate32]
1770 let SchedRW = [WriteFloatFMA, WriteSALU] in {
1771 defm V_DIV_SCALE_F32 : VOP3b_32 <vop3<0x16d, 0x1e0>, "v_div_scale_f32", []>;
1774 let SchedRW = [WriteDouble, WriteSALU] in {
1775 // Double precision division pre-scale.
1776 defm V_DIV_SCALE_F64 : VOP3b_64 <vop3<0x16e, 0x1e1>, "v_div_scale_f64", []>;
1777 } // let SchedRW = [WriteDouble]
1779 let isCommutable = 1, Uses = [VCC, EXEC] in {
1781 let SchedRW = [WriteFloatFMA] in {
1783 // result = src0 * src1 + src2
1787 defm V_DIV_FMAS_F32 : VOP3_VCC_Inst <vop3<0x16f, 0x1e2>, "v_div_fmas_f32",
1788 VOP_F32_F32_F32_F32, AMDGPUdiv_fmas
1792 let SchedRW = [WriteDouble] in {
1794 // result = src0 * src1 + src2
1798 defm V_DIV_FMAS_F64 : VOP3_VCC_Inst <vop3<0x170, 0x1e3>, "v_div_fmas_f64",
1799 VOP_F64_F64_F64_F64, AMDGPUdiv_fmas
1802 } // End SchedRW = [WriteDouble]
1803 } // End isCommutable = 1, Uses = [VCC, EXEC]
1805 //def V_MSAD_U8 : VOP3_U8 <0x00000171, "v_msad_u8", []>;
1806 //def V_QSAD_U8 : VOP3_U8 <0x00000172, "v_qsad_u8", []>;
1807 //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "v_mqsad_u8", []>;
1809 let SchedRW = [WriteDouble] in {
1810 defm V_TRIG_PREOP_F64 : VOP3Inst <
1811 vop3<0x174, 0x292>, "v_trig_preop_f64", VOP_F64_F64_I32, AMDGPUtrig_preop
1814 } // let SchedRW = [WriteDouble]
1816 // These instructions only exist on SI and CI
1817 let SubtargetPredicate = isSICI in {
1819 defm V_LSHL_B64 : VOP3Inst <vop3<0x161>, "v_lshl_b64", VOP_I64_I64_I32>;
1820 defm V_LSHR_B64 : VOP3Inst <vop3<0x162>, "v_lshr_b64", VOP_I64_I64_I32>;
1821 defm V_ASHR_I64 : VOP3Inst <vop3<0x163>, "v_ashr_i64", VOP_I64_I64_I32>;
1823 defm V_MULLIT_F32 : VOP3Inst <vop3<0x150>, "v_mullit_f32",
1824 VOP_F32_F32_F32_F32>;
1826 } // End SubtargetPredicate = isSICI
1828 let SubtargetPredicate = isVI in {
1830 defm V_LSHLREV_B64 : VOP3Inst <vop3<0, 0x28f>, "v_lshlrev_b64",
1833 defm V_LSHRREV_B64 : VOP3Inst <vop3<0, 0x290>, "v_lshrrev_b64",
1836 defm V_ASHRREV_I64 : VOP3Inst <vop3<0, 0x291>, "v_ashrrev_i64",
1840 } // End SubtargetPredicate = isVI
1842 //===----------------------------------------------------------------------===//
1843 // Pseudo Instructions
1844 //===----------------------------------------------------------------------===//
1845 let isCodeGenOnly = 1, isPseudo = 1 in {
1847 // For use in patterns
1848 def V_CNDMASK_B64_PSEUDO : VOP3Common <(outs VReg_64:$dst),
1849 (ins VSrc_64:$src0, VSrc_64:$src1, SSrc_64:$src2), "", []
1852 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC] in {
1853 // 64-bit vector move instruction. This is mainly used by the SIFoldOperands
1854 // pass to enable folding of inline immediates.
1855 def V_MOV_B64_PSEUDO : InstSI <(outs VReg_64:$dst), (ins VSrc_64:$src0), "", []>;
1856 } // end let hasSideEffects = 0, mayLoad = 0, mayStore = 0
1858 let hasSideEffects = 1 in {
1859 def SGPR_USE : InstSI <(outs),(ins), "", []>;
1862 // SI pseudo instructions. These are used by the CFG structurizer pass
1863 // and should be lowered to ISA instructions prior to codegen.
1865 let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in {
1866 let Uses = [EXEC], Defs = [EXEC] in {
1868 let isBranch = 1, isTerminator = 1 in {
1871 (outs SReg_64:$dst),
1872 (ins SReg_64:$vcc, brtarget:$target),
1874 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))]
1877 def SI_ELSE : InstSI <
1878 (outs SReg_64:$dst),
1879 (ins SReg_64:$src, brtarget:$target),
1881 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]
1883 let Constraints = "$src = $dst";
1886 def SI_LOOP : InstSI <
1888 (ins SReg_64:$saved, brtarget:$target),
1889 "si_loop $saved, $target",
1890 [(int_SI_loop i64:$saved, bb:$target)]
1893 } // end isBranch = 1, isTerminator = 1
1895 def SI_BREAK : InstSI <
1896 (outs SReg_64:$dst),
1898 "si_else $dst, $src",
1899 [(set i64:$dst, (int_SI_break i64:$src))]
1902 def SI_IF_BREAK : InstSI <
1903 (outs SReg_64:$dst),
1904 (ins SReg_64:$vcc, SReg_64:$src),
1905 "si_if_break $dst, $vcc, $src",
1906 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))]
1909 def SI_ELSE_BREAK : InstSI <
1910 (outs SReg_64:$dst),
1911 (ins SReg_64:$src0, SReg_64:$src1),
1912 "si_else_break $dst, $src0, $src1",
1913 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))]
1916 def SI_END_CF : InstSI <
1918 (ins SReg_64:$saved),
1920 [(int_SI_end_cf i64:$saved)]
1923 } // End Uses = [EXEC], Defs = [EXEC]
1925 let Uses = [EXEC], Defs = [EXEC,VCC] in {
1926 def SI_KILL : InstSI <
1930 [(int_AMDGPU_kill f32:$src)]
1932 } // End Uses = [EXEC], Defs = [EXEC,VCC]
1934 } // end mayLoad = 1, mayStore = 1, hasSideEffects = 1
1936 let Uses = [EXEC], Defs = [EXEC,VCC,M0] in {
1938 //defm SI_ : RegisterLoadStore <VGPR_32, FRAMEri, ADDRIndirect>;
1940 let UseNamedOperandTable = 1 in {
1942 def SI_RegisterLoad : InstSI <
1943 (outs VGPR_32:$dst, SReg_64:$temp),
1944 (ins FRAMEri32:$addr, i32imm:$chan),
1947 let isRegisterLoad = 1;
1951 class SIRegStore<dag outs> : InstSI <
1953 (ins VGPR_32:$val, FRAMEri32:$addr, i32imm:$chan),
1956 let isRegisterStore = 1;
1960 let usesCustomInserter = 1 in {
1961 def SI_RegisterStorePseudo : SIRegStore<(outs)>;
1962 } // End usesCustomInserter = 1
1963 def SI_RegisterStore : SIRegStore<(outs SReg_64:$temp)>;
1966 } // End UseNamedOperandTable = 1
1968 def SI_INDIRECT_SRC : InstSI <
1969 (outs VGPR_32:$dst, SReg_64:$temp),
1970 (ins unknown:$src, VSrc_32:$idx, i32imm:$off),
1971 "si_indirect_src $dst, $temp, $src, $idx, $off",
1975 class SI_INDIRECT_DST<RegisterClass rc> : InstSI <
1976 (outs rc:$dst, SReg_64:$temp),
1977 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VGPR_32:$val),
1978 "si_indirect_dst $dst, $temp, $src, $idx, $off, $val",
1981 let Constraints = "$src = $dst";
1984 def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VGPR_32>;
1985 def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>;
1986 def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>;
1987 def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>;
1988 def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>;
1990 } // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0]
1992 multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
1994 let UseNamedOperandTable = 1, Uses = [EXEC] in {
1995 def _SAVE : InstSI <
1997 (ins sgpr_class:$src, i32imm:$frame_idx, SReg_128:$scratch_rsrc,
1998 SReg_32:$scratch_offset),
2005 def _RESTORE : InstSI <
2006 (outs sgpr_class:$dst),
2007 (ins i32imm:$frame_idx, SReg_128:$scratch_rsrc, SReg_32:$scratch_offset),
2013 } // End UseNamedOperandTable = 1
2016 // It's unclear whether you can use M0 as the output of v_readlane_b32
2017 // instructions, so use SGPR_32 register class for spills to prevent
2018 // this from happening.
2019 defm SI_SPILL_S32 : SI_SPILL_SGPR <SGPR_32>;
2020 defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>;
2021 defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>;
2022 defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>;
2023 defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>;
2025 multiclass SI_SPILL_VGPR <RegisterClass vgpr_class> {
2026 let UseNamedOperandTable = 1, VGPRSpill = 1, Uses = [EXEC] in {
2027 def _SAVE : InstSI <
2029 (ins vgpr_class:$src, i32imm:$frame_idx, SReg_128:$scratch_rsrc,
2030 SReg_32:$scratch_offset),
2037 def _RESTORE : InstSI <
2038 (outs vgpr_class:$dst),
2039 (ins i32imm:$frame_idx, SReg_128:$scratch_rsrc, SReg_32:$scratch_offset),
2045 } // End UseNamedOperandTable = 1, VGPRSpill = 1
2048 defm SI_SPILL_V32 : SI_SPILL_VGPR <VGPR_32>;
2049 defm SI_SPILL_V64 : SI_SPILL_VGPR <VReg_64>;
2050 defm SI_SPILL_V96 : SI_SPILL_VGPR <VReg_96>;
2051 defm SI_SPILL_V128 : SI_SPILL_VGPR <VReg_128>;
2052 defm SI_SPILL_V256 : SI_SPILL_VGPR <VReg_256>;
2053 defm SI_SPILL_V512 : SI_SPILL_VGPR <VReg_512>;
2055 let Defs = [SCC] in {
2057 def SI_CONSTDATA_PTR : InstSI <
2058 (outs SReg_64:$dst),
2060 "", [(set SReg_64:$dst, (i64 SIconstdata_ptr))]
2063 } // End Defs = [SCC]
2065 } // end IsCodeGenOnly, isPseudo
2067 } // end SubtargetPredicate = isGCN
2069 let Predicates = [isGCN] in {
2072 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2),
2073 (V_CNDMASK_B32_e64 $src2, $src1,
2074 (V_CMP_GT_F32_e64 SRCMODS.NONE, 0, SRCMODS.NONE, $src0,
2075 DSTCLAMP.NONE, DSTOMOD.NONE))
2080 (SI_KILL 0xbf800000)
2083 /* int_SI_vs_load_input */
2085 (SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr),
2086 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $buf_idx_vgpr, $tlst, 0, imm:$attr_offset, 0, 0, 0)
2091 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
2092 f32:$src0, f32:$src1, f32:$src2, f32:$src3),
2093 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm,
2094 $src0, $src1, $src2, $src3)
2097 //===----------------------------------------------------------------------===//
2099 //===----------------------------------------------------------------------===//
2101 multiclass SMRD_Pattern <string Instr, ValueType vt> {
2105 (constant_load (SMRDImm i64:$sbase, i32:$offset)),
2106 (vt (!cast<SMRD>(Instr#"_IMM") $sbase, $offset))
2111 (constant_load (SMRDSgpr i64:$sbase, i32:$offset)),
2112 (vt (!cast<SMRD>(Instr#"_SGPR") $sbase, $offset))
2116 (constant_load (SMRDImm32 i64:$sbase, i32:$offset)),
2117 (vt (!cast<SMRD>(Instr#"_IMM_ci") $sbase, $offset))
2119 let Predicates = [isCIOnly];
2123 defm : SMRD_Pattern <"S_LOAD_DWORD", i32>;
2124 defm : SMRD_Pattern <"S_LOAD_DWORDX2", v2i32>;
2125 defm : SMRD_Pattern <"S_LOAD_DWORDX4", v4i32>;
2126 defm : SMRD_Pattern <"S_LOAD_DWORDX8", v32i8>;
2127 defm : SMRD_Pattern <"S_LOAD_DWORDX8", v8i32>;
2128 defm : SMRD_Pattern <"S_LOAD_DWORDX16", v16i32>;
2130 // 1. Offset as an immediate
2132 (SIload_constant v4i32:$sbase, (SMRDBufferImm i32:$offset)),
2133 (S_BUFFER_LOAD_DWORD_IMM $sbase, $offset)
2136 // 2. Offset loaded in an 32bit SGPR
2138 (SIload_constant v4i32:$sbase, (SMRDBufferSgpr i32:$offset)),
2139 (S_BUFFER_LOAD_DWORD_SGPR $sbase, $offset)
2142 let Predicates = [isCI] in {
2145 (SIload_constant v4i32:$sbase, (SMRDBufferImm32 i32:$offset)),
2146 (S_BUFFER_LOAD_DWORD_IMM_ci $sbase, $offset)
2149 } // End Predicates = [isCI]
2151 //===----------------------------------------------------------------------===//
2153 //===----------------------------------------------------------------------===//
2156 (i64 (ctpop i64:$src)),
2157 (i64 (REG_SEQUENCE SReg_64,
2158 (S_BCNT1_I32_B64 $src), sub0,
2159 (S_MOV_B32 0), sub1))
2162 //===----------------------------------------------------------------------===//
2164 //===----------------------------------------------------------------------===//
2166 // V_ADD_I32_e32/S_ADD_U32 produces carry in VCC/SCC. For the vector
2167 // case, the sgpr-copies pass will fix this to use the vector version.
2169 (i32 (addc i32:$src0, i32:$src1)),
2170 (S_ADD_U32 $src0, $src1)
2173 //===----------------------------------------------------------------------===//
2175 //===----------------------------------------------------------------------===//
2178 (int_AMDGPU_barrier_global),
2182 //===----------------------------------------------------------------------===//
2184 //===----------------------------------------------------------------------===//
2186 let Predicates = [UnsafeFPMath] in {
2188 //def : RcpPat<V_RCP_F64_e32, f64>;
2189 //defm : RsqPat<V_RSQ_F64_e32, f64>;
2190 //defm : RsqPat<V_RSQ_F32_e32, f32>;
2192 def : RsqPat<V_RSQ_F32_e32, f32>;
2193 def : RsqPat<V_RSQ_F64_e32, f64>;
2196 //===----------------------------------------------------------------------===//
2198 //===----------------------------------------------------------------------===//
2201 (i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)),
2202 (V_BCNT_U32_B32_e64 $popcnt, $val)
2206 (i32 (select i1:$src0, i32:$src1, i32:$src2)),
2207 (V_CNDMASK_B32_e64 $src2, $src1, $src0)
2210 // Pattern for V_MAC_F32
2212 (fmad (VOP3NoMods0 f32:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
2213 (VOP3NoMods f32:$src1, i32:$src1_modifiers),
2214 (VOP3NoMods f32:$src2, i32:$src2_modifiers)),
2215 (V_MAC_F32_e64 $src0_modifiers, $src0, $src1_modifiers, $src1,
2216 $src2_modifiers, $src2, $clamp, $omod)
2219 /********** ======================= **********/
2220 /********** Image sampling patterns **********/
2221 /********** ======================= **********/
2224 class SampleRawPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
2225 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i32:$unorm,
2226 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
2227 (opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da),
2228 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc),
2229 $addr, $rsrc, $sampler)
2232 multiclass SampleRawPatterns<SDPatternOperator name, string opcode> {
2233 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
2234 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
2235 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
2236 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V8), v8i32>;
2237 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V16), v16i32>;
2241 class ImagePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
2242 (name vt:$addr, v8i32:$rsrc, i32:$dmask, i32:$unorm,
2243 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
2244 (opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da),
2245 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc),
2249 multiclass ImagePatterns<SDPatternOperator name, string opcode> {
2250 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
2251 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
2252 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
2256 defm : SampleRawPatterns<int_SI_image_sample, "IMAGE_SAMPLE">;
2257 defm : SampleRawPatterns<int_SI_image_sample_cl, "IMAGE_SAMPLE_CL">;
2258 defm : SampleRawPatterns<int_SI_image_sample_d, "IMAGE_SAMPLE_D">;
2259 defm : SampleRawPatterns<int_SI_image_sample_d_cl, "IMAGE_SAMPLE_D_CL">;
2260 defm : SampleRawPatterns<int_SI_image_sample_l, "IMAGE_SAMPLE_L">;
2261 defm : SampleRawPatterns<int_SI_image_sample_b, "IMAGE_SAMPLE_B">;
2262 defm : SampleRawPatterns<int_SI_image_sample_b_cl, "IMAGE_SAMPLE_B_CL">;
2263 defm : SampleRawPatterns<int_SI_image_sample_lz, "IMAGE_SAMPLE_LZ">;
2264 defm : SampleRawPatterns<int_SI_image_sample_cd, "IMAGE_SAMPLE_CD">;
2265 defm : SampleRawPatterns<int_SI_image_sample_cd_cl, "IMAGE_SAMPLE_CD_CL">;
2267 // Sample with comparison
2268 defm : SampleRawPatterns<int_SI_image_sample_c, "IMAGE_SAMPLE_C">;
2269 defm : SampleRawPatterns<int_SI_image_sample_c_cl, "IMAGE_SAMPLE_C_CL">;
2270 defm : SampleRawPatterns<int_SI_image_sample_c_d, "IMAGE_SAMPLE_C_D">;
2271 defm : SampleRawPatterns<int_SI_image_sample_c_d_cl, "IMAGE_SAMPLE_C_D_CL">;
2272 defm : SampleRawPatterns<int_SI_image_sample_c_l, "IMAGE_SAMPLE_C_L">;
2273 defm : SampleRawPatterns<int_SI_image_sample_c_b, "IMAGE_SAMPLE_C_B">;
2274 defm : SampleRawPatterns<int_SI_image_sample_c_b_cl, "IMAGE_SAMPLE_C_B_CL">;
2275 defm : SampleRawPatterns<int_SI_image_sample_c_lz, "IMAGE_SAMPLE_C_LZ">;
2276 defm : SampleRawPatterns<int_SI_image_sample_c_cd, "IMAGE_SAMPLE_C_CD">;
2277 defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl, "IMAGE_SAMPLE_C_CD_CL">;
2279 // Sample with offsets
2280 defm : SampleRawPatterns<int_SI_image_sample_o, "IMAGE_SAMPLE_O">;
2281 defm : SampleRawPatterns<int_SI_image_sample_cl_o, "IMAGE_SAMPLE_CL_O">;
2282 defm : SampleRawPatterns<int_SI_image_sample_d_o, "IMAGE_SAMPLE_D_O">;
2283 defm : SampleRawPatterns<int_SI_image_sample_d_cl_o, "IMAGE_SAMPLE_D_CL_O">;
2284 defm : SampleRawPatterns<int_SI_image_sample_l_o, "IMAGE_SAMPLE_L_O">;
2285 defm : SampleRawPatterns<int_SI_image_sample_b_o, "IMAGE_SAMPLE_B_O">;
2286 defm : SampleRawPatterns<int_SI_image_sample_b_cl_o, "IMAGE_SAMPLE_B_CL_O">;
2287 defm : SampleRawPatterns<int_SI_image_sample_lz_o, "IMAGE_SAMPLE_LZ_O">;
2288 defm : SampleRawPatterns<int_SI_image_sample_cd_o, "IMAGE_SAMPLE_CD_O">;
2289 defm : SampleRawPatterns<int_SI_image_sample_cd_cl_o, "IMAGE_SAMPLE_CD_CL_O">;
2291 // Sample with comparison and offsets
2292 defm : SampleRawPatterns<int_SI_image_sample_c_o, "IMAGE_SAMPLE_C_O">;
2293 defm : SampleRawPatterns<int_SI_image_sample_c_cl_o, "IMAGE_SAMPLE_C_CL_O">;
2294 defm : SampleRawPatterns<int_SI_image_sample_c_d_o, "IMAGE_SAMPLE_C_D_O">;
2295 defm : SampleRawPatterns<int_SI_image_sample_c_d_cl_o, "IMAGE_SAMPLE_C_D_CL_O">;
2296 defm : SampleRawPatterns<int_SI_image_sample_c_l_o, "IMAGE_SAMPLE_C_L_O">;
2297 defm : SampleRawPatterns<int_SI_image_sample_c_b_o, "IMAGE_SAMPLE_C_B_O">;
2298 defm : SampleRawPatterns<int_SI_image_sample_c_b_cl_o, "IMAGE_SAMPLE_C_B_CL_O">;
2299 defm : SampleRawPatterns<int_SI_image_sample_c_lz_o, "IMAGE_SAMPLE_C_LZ_O">;
2300 defm : SampleRawPatterns<int_SI_image_sample_c_cd_o, "IMAGE_SAMPLE_C_CD_O">;
2301 defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl_o, "IMAGE_SAMPLE_C_CD_CL_O">;
2304 // Only the variants which make sense are defined.
2305 def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V2, v2i32>;
2306 def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V4, v4i32>;
2307 def : SampleRawPattern<int_SI_gather4_cl, IMAGE_GATHER4_CL_V4_V4, v4i32>;
2308 def : SampleRawPattern<int_SI_gather4_l, IMAGE_GATHER4_L_V4_V4, v4i32>;
2309 def : SampleRawPattern<int_SI_gather4_b, IMAGE_GATHER4_B_V4_V4, v4i32>;
2310 def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V4, v4i32>;
2311 def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V8, v8i32>;
2312 def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V2, v2i32>;
2313 def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V4, v4i32>;
2315 def : SampleRawPattern<int_SI_gather4_c, IMAGE_GATHER4_C_V4_V4, v4i32>;
2316 def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V4, v4i32>;
2317 def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V8, v8i32>;
2318 def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V4, v4i32>;
2319 def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V8, v8i32>;
2320 def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V4, v4i32>;
2321 def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V8, v8i32>;
2322 def : SampleRawPattern<int_SI_gather4_c_b_cl, IMAGE_GATHER4_C_B_CL_V4_V8, v8i32>;
2323 def : SampleRawPattern<int_SI_gather4_c_lz, IMAGE_GATHER4_C_LZ_V4_V4, v4i32>;
2325 def : SampleRawPattern<int_SI_gather4_o, IMAGE_GATHER4_O_V4_V4, v4i32>;
2326 def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V4, v4i32>;
2327 def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V8, v8i32>;
2328 def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V4, v4i32>;
2329 def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V8, v8i32>;
2330 def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V4, v4i32>;
2331 def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V8, v8i32>;
2332 def : SampleRawPattern<int_SI_gather4_b_cl_o, IMAGE_GATHER4_B_CL_O_V4_V8, v8i32>;
2333 def : SampleRawPattern<int_SI_gather4_lz_o, IMAGE_GATHER4_LZ_O_V4_V4, v4i32>;
2335 def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V4, v4i32>;
2336 def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V8, v8i32>;
2337 def : SampleRawPattern<int_SI_gather4_c_cl_o, IMAGE_GATHER4_C_CL_O_V4_V8, v8i32>;
2338 def : SampleRawPattern<int_SI_gather4_c_l_o, IMAGE_GATHER4_C_L_O_V4_V8, v8i32>;
2339 def : SampleRawPattern<int_SI_gather4_c_b_o, IMAGE_GATHER4_C_B_O_V4_V8, v8i32>;
2340 def : SampleRawPattern<int_SI_gather4_c_b_cl_o, IMAGE_GATHER4_C_B_CL_O_V4_V8, v8i32>;
2341 def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V4, v4i32>;
2342 def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V8, v8i32>;
2344 def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V1, i32>;
2345 def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V2, v2i32>;
2346 def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V4, v4i32>;
2348 def : ImagePattern<int_SI_getresinfo, IMAGE_GET_RESINFO_V4_V1, i32>;
2349 defm : ImagePatterns<int_SI_image_load, "IMAGE_LOAD">;
2350 defm : ImagePatterns<int_SI_image_load_mip, "IMAGE_LOAD_MIP">;
2352 /* SIsample for simple 1D texture lookup */
2354 (SIsample i32:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
2355 (IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2358 class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
2359 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
2360 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2363 class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
2364 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_RECT),
2365 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2368 class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
2369 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_ARRAY),
2370 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2373 class SampleShadowPattern<SDNode name, MIMG opcode,
2374 ValueType vt> : Pat <
2375 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW),
2376 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2379 class SampleShadowArrayPattern<SDNode name, MIMG opcode,
2380 ValueType vt> : Pat <
2381 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY),
2382 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2385 /* SIsample* for texture lookups consuming more address parameters */
2386 multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l,
2387 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b,
2388 MIMG sample_d, MIMG sample_c_d, ValueType addr_type> {
2389 def : SamplePattern <SIsample, sample, addr_type>;
2390 def : SampleRectPattern <SIsample, sample, addr_type>;
2391 def : SampleArrayPattern <SIsample, sample, addr_type>;
2392 def : SampleShadowPattern <SIsample, sample_c, addr_type>;
2393 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>;
2395 def : SamplePattern <SIsamplel, sample_l, addr_type>;
2396 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>;
2397 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>;
2398 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>;
2400 def : SamplePattern <SIsampleb, sample_b, addr_type>;
2401 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>;
2402 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>;
2403 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>;
2405 def : SamplePattern <SIsampled, sample_d, addr_type>;
2406 def : SampleArrayPattern <SIsampled, sample_d, addr_type>;
2407 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>;
2408 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>;
2411 defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2,
2412 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2,
2413 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2,
2414 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2,
2416 defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4,
2417 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4,
2418 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4,
2419 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4,
2421 defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8,
2422 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8,
2423 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8,
2424 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8,
2426 defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16,
2427 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16,
2428 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16,
2429 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16,
2432 /* int_SI_imageload for texture fetches consuming varying address parameters */
2433 class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2434 (name addr_type:$addr, v32i8:$rsrc, imm),
2435 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
2438 class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2439 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY),
2440 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
2443 class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2444 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA),
2445 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
2448 class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2449 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA),
2450 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
2453 multiclass ImageLoadPatterns<MIMG opcode, ValueType addr_type> {
2454 def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>;
2455 def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>;
2458 multiclass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> {
2459 def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>;
2460 def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>;
2463 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V2, v2i32>;
2464 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V4, v4i32>;
2466 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V2, v2i32>;
2467 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V4, v4i32>;
2469 /* Image resource information */
2471 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm),
2472 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
2476 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY),
2477 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
2481 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA),
2482 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
2485 /********** ============================================ **********/
2486 /********** Extraction, Insertion, Building and Casting **********/
2487 /********** ============================================ **********/
2489 foreach Index = 0-2 in {
2490 def Extract_Element_v2i32_#Index : Extract_Element <
2491 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
2493 def Insert_Element_v2i32_#Index : Insert_Element <
2494 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
2497 def Extract_Element_v2f32_#Index : Extract_Element <
2498 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
2500 def Insert_Element_v2f32_#Index : Insert_Element <
2501 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
2505 foreach Index = 0-3 in {
2506 def Extract_Element_v4i32_#Index : Extract_Element <
2507 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
2509 def Insert_Element_v4i32_#Index : Insert_Element <
2510 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
2513 def Extract_Element_v4f32_#Index : Extract_Element <
2514 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
2516 def Insert_Element_v4f32_#Index : Insert_Element <
2517 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
2521 foreach Index = 0-7 in {
2522 def Extract_Element_v8i32_#Index : Extract_Element <
2523 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
2525 def Insert_Element_v8i32_#Index : Insert_Element <
2526 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
2529 def Extract_Element_v8f32_#Index : Extract_Element <
2530 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
2532 def Insert_Element_v8f32_#Index : Insert_Element <
2533 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
2537 foreach Index = 0-15 in {
2538 def Extract_Element_v16i32_#Index : Extract_Element <
2539 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
2541 def Insert_Element_v16i32_#Index : Insert_Element <
2542 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
2545 def Extract_Element_v16f32_#Index : Extract_Element <
2546 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
2548 def Insert_Element_v16f32_#Index : Insert_Element <
2549 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
2553 def : BitConvert <i32, f32, SReg_32>;
2554 def : BitConvert <i32, f32, VGPR_32>;
2556 def : BitConvert <f32, i32, SReg_32>;
2557 def : BitConvert <f32, i32, VGPR_32>;
2559 def : BitConvert <i64, f64, VReg_64>;
2561 def : BitConvert <f64, i64, VReg_64>;
2563 def : BitConvert <v2f32, v2i32, VReg_64>;
2564 def : BitConvert <v2i32, v2f32, VReg_64>;
2565 def : BitConvert <v2i32, i64, VReg_64>;
2566 def : BitConvert <i64, v2i32, VReg_64>;
2567 def : BitConvert <v2f32, i64, VReg_64>;
2568 def : BitConvert <i64, v2f32, VReg_64>;
2569 def : BitConvert <v2i32, f64, VReg_64>;
2570 def : BitConvert <f64, v2i32, VReg_64>;
2571 def : BitConvert <v4f32, v4i32, VReg_128>;
2572 def : BitConvert <v4i32, v4f32, VReg_128>;
2574 def : BitConvert <v8f32, v8i32, SReg_256>;
2575 def : BitConvert <v8i32, v8f32, SReg_256>;
2576 def : BitConvert <v8i32, v32i8, SReg_256>;
2577 def : BitConvert <v32i8, v8i32, SReg_256>;
2578 def : BitConvert <v8i32, v32i8, VReg_256>;
2579 def : BitConvert <v8i32, v8f32, VReg_256>;
2580 def : BitConvert <v8f32, v8i32, VReg_256>;
2581 def : BitConvert <v32i8, v8i32, VReg_256>;
2583 def : BitConvert <v16i32, v16f32, VReg_512>;
2584 def : BitConvert <v16f32, v16i32, VReg_512>;
2586 /********** =================== **********/
2587 /********** Src & Dst modifiers **********/
2588 /********** =================== **********/
2591 (AMDGPUclamp (VOP3Mods0Clamp f32:$src0, i32:$src0_modifiers, i32:$omod),
2592 (f32 FP_ZERO), (f32 FP_ONE)),
2593 (V_ADD_F32_e64 $src0_modifiers, $src0, 0, 0, 1, $omod)
2596 /********** ================================ **********/
2597 /********** Floating point absolute/negative **********/
2598 /********** ================================ **********/
2600 // Prevent expanding both fneg and fabs.
2602 // FIXME: Should use S_OR_B32
2604 (fneg (fabs f32:$src)),
2605 (V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */
2608 // FIXME: Should use S_OR_B32
2610 (fneg (fabs f64:$src)),
2611 (REG_SEQUENCE VReg_64,
2612 (i32 (EXTRACT_SUBREG f64:$src, sub0)),
2614 (V_OR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
2615 (V_MOV_B32_e32 0x80000000)), // Set sign bit.
2621 (V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff))
2626 (V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000))
2631 (REG_SEQUENCE VReg_64,
2632 (i32 (EXTRACT_SUBREG f64:$src, sub0)),
2634 (V_AND_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
2635 (V_MOV_B32_e32 0x7fffffff)), // Set sign bit.
2641 (REG_SEQUENCE VReg_64,
2642 (i32 (EXTRACT_SUBREG f64:$src, sub0)),
2644 (V_XOR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
2645 (V_MOV_B32_e32 0x80000000)),
2649 /********** ================== **********/
2650 /********** Immediate Patterns **********/
2651 /********** ================== **********/
2654 (SGPRImm<(i32 imm)>:$imm),
2655 (S_MOV_B32 imm:$imm)
2659 (SGPRImm<(f32 fpimm)>:$imm),
2660 (S_MOV_B32 (f32 (bitcast_fpimm_to_i32 $imm)))
2665 (V_MOV_B32_e32 imm:$imm)
2670 (V_MOV_B32_e32 (f32 (bitcast_fpimm_to_i32 $imm)))
2674 (i64 InlineImm<i64>:$imm),
2675 (S_MOV_B64 InlineImm<i64>:$imm)
2678 // XXX - Should this use a s_cmp to set SCC?
2680 // Set to sign-extended 64-bit value (true = -1, false = 0)
2683 (S_MOV_B64 (i64 (as_i64imm $imm)))
2687 (f64 InlineFPImm<f64>:$imm),
2688 (S_MOV_B64 (f64 (bitcast_fpimm_to_i64 InlineFPImm<f64>:$imm)))
2691 /********** ================== **********/
2692 /********** Intrinsic Patterns **********/
2693 /********** ================== **********/
2695 /* llvm.AMDGPU.pow */
2696 def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>;
2699 (int_AMDGPU_div f32:$src0, f32:$src1),
2700 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1))
2704 (int_AMDGPU_cube v4f32:$src),
2705 (REG_SEQUENCE VReg_128,
2706 (V_CUBETC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0),
2707 0 /* src1_modifiers */, (EXTRACT_SUBREG $src, sub1),
2708 0 /* src2_modifiers */, (EXTRACT_SUBREG $src, sub2),
2709 0 /* clamp */, 0 /* omod */), sub0,
2710 (V_CUBESC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0),
2711 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
2712 0 /* src2_modifiers */,(EXTRACT_SUBREG $src, sub2),
2713 0 /* clamp */, 0 /* omod */), sub1,
2714 (V_CUBEMA_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0),
2715 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
2716 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2),
2717 0 /* clamp */, 0 /* omod */), sub2,
2718 (V_CUBEID_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0),
2719 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
2720 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2),
2721 0 /* clamp */, 0 /* omod */), sub3)
2725 (i32 (sext i1:$src0)),
2726 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0)
2729 class Ext32Pat <SDNode ext> : Pat <
2730 (i32 (ext i1:$src0)),
2731 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0)
2734 def : Ext32Pat <zext>;
2735 def : Ext32Pat <anyext>;
2737 // Offset in an 32Bit VGPR
2739 (SIload_constant v4i32:$sbase, i32:$voff),
2740 (BUFFER_LOAD_DWORD_OFFEN $voff, $sbase, 0, 0, 0, 0, 0)
2743 // The multiplication scales from [0,1] to the unsigned integer range
2745 (AMDGPUurecip i32:$src0),
2747 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1,
2748 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
2753 (V_MBCNT_HI_U32_B32_e64 0xffffffff,
2754 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0))
2757 //===----------------------------------------------------------------------===//
2759 //===----------------------------------------------------------------------===//
2761 def : IMad24Pat<V_MAD_I32_I24>;
2762 def : UMad24Pat<V_MAD_U32_U24>;
2765 (mulhu i32:$src0, i32:$src1),
2766 (V_MUL_HI_U32 $src0, $src1)
2770 (mulhs i32:$src0, i32:$src1),
2771 (V_MUL_HI_I32 $src0, $src1)
2774 defm : BFIPatterns <V_BFI_B32, S_MOV_B32, SReg_64>;
2775 def : ROTRPattern <V_ALIGNBIT_B32>;
2777 /********** ======================= **********/
2778 /********** Load/Store Patterns **********/
2779 /********** ======================= **********/
2781 class DSReadPat <DS inst, ValueType vt, PatFrag frag> : Pat <
2782 (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
2783 (inst $ptr, (as_i16imm $offset), (i1 0))
2786 def : DSReadPat <DS_READ_I8, i32, si_sextload_local_i8>;
2787 def : DSReadPat <DS_READ_U8, i32, si_az_extload_local_i8>;
2788 def : DSReadPat <DS_READ_I16, i32, si_sextload_local_i16>;
2789 def : DSReadPat <DS_READ_U16, i32, si_az_extload_local_i16>;
2790 def : DSReadPat <DS_READ_B32, i32, si_load_local>;
2792 let AddedComplexity = 100 in {
2794 def : DSReadPat <DS_READ_B64, v2i32, si_load_local_align8>;
2796 } // End AddedComplexity = 100
2799 (v2i32 (si_load_local (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
2801 (DS_READ2_B32 $ptr, $offset0, $offset1, (i1 0))
2804 class DSWritePat <DS inst, ValueType vt, PatFrag frag> : Pat <
2805 (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
2806 (inst $ptr, $value, (as_i16imm $offset), (i1 0))
2809 def : DSWritePat <DS_WRITE_B8, i32, si_truncstore_local_i8>;
2810 def : DSWritePat <DS_WRITE_B16, i32, si_truncstore_local_i16>;
2811 def : DSWritePat <DS_WRITE_B32, i32, si_store_local>;
2813 let AddedComplexity = 100 in {
2815 def : DSWritePat <DS_WRITE_B64, v2i32, si_store_local_align8>;
2816 } // End AddedComplexity = 100
2819 (si_store_local v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
2821 (DS_WRITE2_B32 $ptr, (EXTRACT_SUBREG $value, sub0),
2822 (EXTRACT_SUBREG $value, sub1), $offset0, $offset1,
2826 class DSAtomicRetPat<DS inst, ValueType vt, PatFrag frag> : Pat <
2827 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
2828 (inst $ptr, $value, (as_i16imm $offset), (i1 0))
2831 // Special case of DSAtomicRetPat for add / sub 1 -> inc / dec
2833 // We need to use something for the data0, so we set a register to
2834 // -1. For the non-rtn variants, the manual says it does
2835 // DS[A] = (DS[A] >= D0) ? 0 : DS[A] + 1, and setting D0 to uint_max
2836 // will always do the increment so I'm assuming it's the same.
2837 class DSAtomicIncRetPat<DS inst, ValueType vt,
2838 Instruction LoadImm, PatFrag frag> : Pat <
2839 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), (vt 1)),
2840 (inst $ptr, (LoadImm (vt -1)), (as_i16imm $offset), (i1 0))
2844 class DSAtomicCmpXChg <DS inst, ValueType vt, PatFrag frag> : Pat <
2845 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),
2846 (inst $ptr, $cmp, $swap, (as_i16imm $offset), (i1 0))
2851 def : DSAtomicIncRetPat<DS_INC_RTN_U32, i32,
2852 V_MOV_B32_e32, si_atomic_load_add_local>;
2853 def : DSAtomicIncRetPat<DS_DEC_RTN_U32, i32,
2854 V_MOV_B32_e32, si_atomic_load_sub_local>;
2856 def : DSAtomicRetPat<DS_WRXCHG_RTN_B32, i32, si_atomic_swap_local>;
2857 def : DSAtomicRetPat<DS_ADD_RTN_U32, i32, si_atomic_load_add_local>;
2858 def : DSAtomicRetPat<DS_SUB_RTN_U32, i32, si_atomic_load_sub_local>;
2859 def : DSAtomicRetPat<DS_AND_RTN_B32, i32, si_atomic_load_and_local>;
2860 def : DSAtomicRetPat<DS_OR_RTN_B32, i32, si_atomic_load_or_local>;
2861 def : DSAtomicRetPat<DS_XOR_RTN_B32, i32, si_atomic_load_xor_local>;
2862 def : DSAtomicRetPat<DS_MIN_RTN_I32, i32, si_atomic_load_min_local>;
2863 def : DSAtomicRetPat<DS_MAX_RTN_I32, i32, si_atomic_load_max_local>;
2864 def : DSAtomicRetPat<DS_MIN_RTN_U32, i32, si_atomic_load_umin_local>;
2865 def : DSAtomicRetPat<DS_MAX_RTN_U32, i32, si_atomic_load_umax_local>;
2867 def : DSAtomicCmpXChg<DS_CMPST_RTN_B32, i32, si_atomic_cmp_swap_32_local>;
2870 def : DSAtomicIncRetPat<DS_INC_RTN_U64, i64,
2871 V_MOV_B64_PSEUDO, si_atomic_load_add_local>;
2872 def : DSAtomicIncRetPat<DS_DEC_RTN_U64, i64,
2873 V_MOV_B64_PSEUDO, si_atomic_load_sub_local>;
2875 def : DSAtomicRetPat<DS_WRXCHG_RTN_B64, i64, si_atomic_swap_local>;
2876 def : DSAtomicRetPat<DS_ADD_RTN_U64, i64, si_atomic_load_add_local>;
2877 def : DSAtomicRetPat<DS_SUB_RTN_U64, i64, si_atomic_load_sub_local>;
2878 def : DSAtomicRetPat<DS_AND_RTN_B64, i64, si_atomic_load_and_local>;
2879 def : DSAtomicRetPat<DS_OR_RTN_B64, i64, si_atomic_load_or_local>;
2880 def : DSAtomicRetPat<DS_XOR_RTN_B64, i64, si_atomic_load_xor_local>;
2881 def : DSAtomicRetPat<DS_MIN_RTN_I64, i64, si_atomic_load_min_local>;
2882 def : DSAtomicRetPat<DS_MAX_RTN_I64, i64, si_atomic_load_max_local>;
2883 def : DSAtomicRetPat<DS_MIN_RTN_U64, i64, si_atomic_load_umin_local>;
2884 def : DSAtomicRetPat<DS_MAX_RTN_U64, i64, si_atomic_load_umax_local>;
2886 def : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, si_atomic_cmp_swap_64_local>;
2889 //===----------------------------------------------------------------------===//
2891 //===----------------------------------------------------------------------===//
2893 multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt,
2894 PatFrag constant_ld> {
2896 (vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
2897 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))),
2898 (Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset, $glc, $slc, $tfe)
2902 let Predicates = [isSICI] in {
2903 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32, sextloadi8_constant>;
2904 defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32, az_extloadi8_constant>;
2905 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32, sextloadi16_constant>;
2906 defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32, az_extloadi16_constant>;
2907 } // End Predicates = [isSICI]
2909 class MUBUFScratchLoadPat <MUBUF Instr, ValueType vt, PatFrag ld> : Pat <
2910 (vt (ld (MUBUFScratch v4i32:$srsrc, i32:$vaddr,
2911 i32:$soffset, u16imm:$offset))),
2912 (Instr $vaddr, $srsrc, $soffset, $offset, 0, 0, 0)
2915 def : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, i32, sextloadi8_private>;
2916 def : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, i32, extloadi8_private>;
2917 def : MUBUFScratchLoadPat <BUFFER_LOAD_SSHORT_OFFEN, i32, sextloadi16_private>;
2918 def : MUBUFScratchLoadPat <BUFFER_LOAD_USHORT_OFFEN, i32, extloadi16_private>;
2919 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORD_OFFEN, i32, load_private>;
2920 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX2_OFFEN, v2i32, load_private>;
2921 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX4_OFFEN, v4i32, load_private>;
2923 // BUFFER_LOAD_DWORD*, addr64=0
2924 multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen,
2928 (vt (int_SI_buffer_load_dword v4i32:$rsrc, (i32 imm), i32:$soffset,
2929 imm:$offset, 0, 0, imm:$glc, imm:$slc,
2931 (offset $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc),
2932 (as_i1imm $slc), (as_i1imm $tfe))
2936 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2937 imm:$offset, 1, 0, imm:$glc, imm:$slc,
2939 (offen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc),
2944 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2945 imm:$offset, 0, 1, imm:$glc, imm:$slc,
2947 (idxen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc),
2948 (as_i1imm $slc), (as_i1imm $tfe))
2952 (vt (int_SI_buffer_load_dword v4i32:$rsrc, v2i32:$vaddr, i32:$soffset,
2953 imm:$offset, 1, 1, imm:$glc, imm:$slc,
2955 (bothen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc),
2960 defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN,
2961 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>;
2962 defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN,
2963 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>;
2964 defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN,
2965 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>;
2967 class MUBUFScratchStorePat <MUBUF Instr, ValueType vt, PatFrag st> : Pat <
2968 (st vt:$value, (MUBUFScratch v4i32:$srsrc, i32:$vaddr, i32:$soffset,
2970 (Instr $value, $vaddr, $srsrc, $soffset, $offset, 0, 0, 0)
2973 def : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, i32, truncstorei8_private>;
2974 def : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, i32, truncstorei16_private>;
2975 def : MUBUFScratchStorePat <BUFFER_STORE_DWORD_OFFEN, i32, store_private>;
2976 def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX2_OFFEN, v2i32, store_private>;
2977 def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX4_OFFEN, v4i32, store_private>;
2980 class MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> : Pat <
2981 (st vt:$value, (MUBUFScratch v4i32:$srsrc, i64:$vaddr, u16imm:$offset)),
2982 (Instr $value, $srsrc, $vaddr, $offset)
2985 let Predicates = [isSICI] in {
2986 def : MUBUFStore_Pattern <BUFFER_STORE_BYTE_ADDR64, i32, truncstorei8_private>;
2987 def : MUBUFStore_Pattern <BUFFER_STORE_SHORT_ADDR64, i32, truncstorei16_private>;
2988 def : MUBUFStore_Pattern <BUFFER_STORE_DWORD_ADDR64, i32, store_private>;
2989 def : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2_ADDR64, v2i32, store_private>;
2990 def : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4_ADDR64, v4i32, store_private>;
2991 } // End Predicates = [isSICI]
2995 //===----------------------------------------------------------------------===//
2997 //===----------------------------------------------------------------------===//
2999 // TBUFFER_STORE_FORMAT_*, addr64=0
3000 class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat<
3001 (SItbuffer_store v4i32:$rsrc, vt:$vdata, num_channels, i32:$vaddr,
3002 i32:$soffset, imm:$inst_offset, imm:$dfmt,
3003 imm:$nfmt, imm:$offen, imm:$idxen,
3004 imm:$glc, imm:$slc, imm:$tfe),
3006 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen),
3007 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc,
3008 (as_i1imm $slc), (as_i1imm $tfe), $soffset)
3011 def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>;
3012 def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>;
3013 def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>;
3014 def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>;
3016 /********** ====================== **********/
3017 /********** Indirect adressing **********/
3018 /********** ====================== **********/
3020 multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, SI_INDIRECT_DST IndDst> {
3022 // 1. Extract with offset
3024 (eltvt (vector_extract vt:$vec, (add i32:$idx, imm:$off))),
3025 (SI_INDIRECT_SRC $vec, $idx, imm:$off)
3028 // 2. Extract without offset
3030 (eltvt (vector_extract vt:$vec, i32:$idx)),
3031 (SI_INDIRECT_SRC $vec, $idx, 0)
3034 // 3. Insert with offset
3036 (vector_insert vt:$vec, eltvt:$val, (add i32:$idx, imm:$off)),
3037 (IndDst $vec, $idx, imm:$off, $val)
3040 // 4. Insert without offset
3042 (vector_insert vt:$vec, eltvt:$val, i32:$idx),
3043 (IndDst $vec, $idx, 0, $val)
3047 defm : SI_INDIRECT_Pattern <v2f32, f32, SI_INDIRECT_DST_V2>;
3048 defm : SI_INDIRECT_Pattern <v4f32, f32, SI_INDIRECT_DST_V4>;
3049 defm : SI_INDIRECT_Pattern <v8f32, f32, SI_INDIRECT_DST_V8>;
3050 defm : SI_INDIRECT_Pattern <v16f32, f32, SI_INDIRECT_DST_V16>;
3052 defm : SI_INDIRECT_Pattern <v2i32, i32, SI_INDIRECT_DST_V2>;
3053 defm : SI_INDIRECT_Pattern <v4i32, i32, SI_INDIRECT_DST_V4>;
3054 defm : SI_INDIRECT_Pattern <v8i32, i32, SI_INDIRECT_DST_V8>;
3055 defm : SI_INDIRECT_Pattern <v16i32, i32, SI_INDIRECT_DST_V16>;
3057 //===----------------------------------------------------------------------===//
3058 // Conversion Patterns
3059 //===----------------------------------------------------------------------===//
3061 def : Pat<(i32 (sext_inreg i32:$src, i1)),
3062 (S_BFE_I32 i32:$src, 65536)>; // 0 | 1 << 16
3064 // Handle sext_inreg in i64
3066 (i64 (sext_inreg i64:$src, i1)),
3067 (S_BFE_I64 i64:$src, 0x10000) // 0 | 1 << 16
3071 (i64 (sext_inreg i64:$src, i8)),
3072 (S_BFE_I64 i64:$src, 0x80000) // 0 | 8 << 16
3076 (i64 (sext_inreg i64:$src, i16)),
3077 (S_BFE_I64 i64:$src, 0x100000) // 0 | 16 << 16
3081 (i64 (sext_inreg i64:$src, i32)),
3082 (S_BFE_I64 i64:$src, 0x200000) // 0 | 32 << 16
3085 class ZExt_i64_i32_Pat <SDNode ext> : Pat <
3086 (i64 (ext i32:$src)),
3087 (REG_SEQUENCE SReg_64, $src, sub0, (S_MOV_B32 0), sub1)
3090 class ZExt_i64_i1_Pat <SDNode ext> : Pat <
3091 (i64 (ext i1:$src)),
3092 (REG_SEQUENCE VReg_64,
3093 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src), sub0,
3094 (S_MOV_B32 0), sub1)
3098 def : ZExt_i64_i32_Pat<zext>;
3099 def : ZExt_i64_i32_Pat<anyext>;
3100 def : ZExt_i64_i1_Pat<zext>;
3101 def : ZExt_i64_i1_Pat<anyext>;
3104 (i64 (sext i32:$src)),
3105 (REG_SEQUENCE SReg_64, $src, sub0,
3106 (S_ASHR_I32 $src, 31), sub1)
3110 (i64 (sext i1:$src)),
3111 (REG_SEQUENCE VReg_64,
3112 (V_CNDMASK_B32_e64 0, -1, $src), sub0,
3113 (V_CNDMASK_B32_e64 0, -1, $src), sub1)
3116 // If we need to perform a logical operation on i1 values, we need to
3117 // use vector comparisons since there is only one SCC register. Vector
3118 // comparisions still write to a pair of SGPRs, so treat these as
3119 // 64-bit comparisons. When legalizing SGPR copies, instructions
3120 // resulting in the copies from SCC to these instructions will be
3121 // moved to the VALU.
3123 (i1 (and i1:$src0, i1:$src1)),
3124 (S_AND_B64 $src0, $src1)
3128 (i1 (or i1:$src0, i1:$src1)),
3129 (S_OR_B64 $src0, $src1)
3133 (i1 (xor i1:$src0, i1:$src1)),
3134 (S_XOR_B64 $src0, $src1)
3138 (f32 (sint_to_fp i1:$src)),
3139 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_NEG_ONE, $src)
3143 (f32 (uint_to_fp i1:$src)),
3144 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_ONE, $src)
3148 (f64 (sint_to_fp i1:$src)),
3149 (V_CVT_F64_I32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src))
3153 (f64 (uint_to_fp i1:$src)),
3154 (V_CVT_F64_U32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src))
3157 //===----------------------------------------------------------------------===//
3158 // Miscellaneous Patterns
3159 //===----------------------------------------------------------------------===//
3162 (i32 (trunc i64:$a)),
3163 (EXTRACT_SUBREG $a, sub0)
3167 (i1 (trunc i32:$a)),
3168 (V_CMP_EQ_I32_e64 (V_AND_B32_e64 (i32 1), $a), 1)
3172 (i1 (trunc i64:$a)),
3173 (V_CMP_EQ_I32_e64 (V_AND_B32_e64 (i32 1),
3174 (EXTRACT_SUBREG $a, sub0)), 1)
3178 (i32 (bswap i32:$a)),
3179 (V_BFI_B32 (S_MOV_B32 0x00ff00ff),
3180 (V_ALIGNBIT_B32 $a, $a, 24),
3181 (V_ALIGNBIT_B32 $a, $a, 8))
3185 (f32 (select i1:$src2, f32:$src1, f32:$src0)),
3186 (V_CNDMASK_B32_e64 $src0, $src1, $src2)
3189 multiclass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> {
3191 (vt (shl (vt (add (vt (shl 1, vt:$a)), -1)), vt:$b)),
3196 (vt (add (vt (shl 1, vt:$a)), -1)),
3201 defm : BFMPatterns <i32, S_BFM_B32, S_MOV_B32>;
3202 // FIXME: defm : BFMPatterns <i64, S_BFM_B64, S_MOV_B64>;
3204 def : BFEPattern <V_BFE_U32, S_MOV_B32>;
3206 //===----------------------------------------------------------------------===//
3208 //===----------------------------------------------------------------------===//
3210 let Predicates = [isSI] in {
3212 // V_FRACT is buggy on SI, so the F32 version is never used and (x-floor(x)) is
3213 // used instead. However, SI doesn't have V_FLOOR_F64, so the most efficient
3214 // way to implement it is using V_FRACT_F64.
3215 // The workaround for the V_FRACT bug is:
3216 // fract(x) = isnan(x) ? x : min(V_FRACT(x), 0.99999999999999999)
3218 // Convert (x + (-floor(x)) to fract(x)
3220 (f64 (fadd (f64 (VOP3Mods f64:$x, i32:$mods)),
3221 (f64 (fneg (f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))))))),
3222 (V_CNDMASK_B64_PSEUDO
3225 (V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE),
3227 (V_MOV_B64_PSEUDO 0x3fefffffffffffff),
3228 DSTCLAMP.NONE, DSTOMOD.NONE),
3230 (V_CMP_CLASS_F64_e64 SRCMODS.NONE, $x, 3/*NaN*/))
3233 // Convert floor(x) to (x - fract(x))
3235 (f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))),
3240 (V_CNDMASK_B64_PSEUDO
3243 (V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE),
3245 (V_MOV_B64_PSEUDO 0x3fefffffffffffff),
3246 DSTCLAMP.NONE, DSTOMOD.NONE),
3248 (V_CMP_CLASS_F64_e64 SRCMODS.NONE, $x, 3/*NaN*/)),
3249 DSTCLAMP.NONE, DSTOMOD.NONE)
3252 } // End Predicates = [isSI]
3254 //============================================================================//
3255 // Miscellaneous Optimization Patterns
3256 //============================================================================//
3258 def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e64>;
3260 //============================================================================//
3261 // Assembler aliases
3262 //============================================================================//
3264 def : MnemonicAlias<"v_add_u32", "v_add_i32">;
3265 def : MnemonicAlias<"v_sub_u32", "v_sub_i32">;
3266 def : MnemonicAlias<"v_subrev_u32", "v_subrev_i32">;
3268 } // End isGCN predicate