1 //===-- SILowerControlFlow.cpp - Use predicates for control flow ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This pass lowers the pseudo control flow instructions to real
12 /// machine instructions.
14 /// All control flow is handled using predicated instructions and
15 /// a predicate stack. Each Scalar ALU controls the operations of 64 Vector
16 /// ALUs. The Scalar ALU can update the predicate for any of the Vector ALUs
17 /// by writting to the 64-bit EXEC register (each bit corresponds to a
18 /// single vector ALU). Typically, for predicates, a vector ALU will write
19 /// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
20 /// Vector ALU) and then the ScalarALU will AND the VCC register with the
21 /// EXEC to update the predicates.
24 /// %VCC = V_CMP_GT_F32 %VGPR1, %VGPR2
25 /// %SGPR0 = SI_IF %VCC
26 /// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0
27 /// %SGPR0 = SI_ELSE %SGPR0
28 /// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR0
33 /// %SGPR0 = S_AND_SAVEEXEC_B64 %VCC // Save and update the exec mask
34 /// %SGPR0 = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
35 /// S_CBRANCH_EXECZ label0 // This instruction is an optional
36 /// // optimization which allows us to
37 /// // branch if all the bits of
39 /// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0 // Do the IF block of the branch
42 /// %SGPR0 = S_OR_SAVEEXEC_B64 %EXEC // Restore the exec mask for the Then block
43 /// %EXEC = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
44 /// S_BRANCH_EXECZ label1 // Use our branch optimization
45 /// // instruction again.
46 /// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR // Do the THEN block
48 /// %EXEC = S_OR_B64 %EXEC, %SGPR0 // Re-enable saved exec mask bits
49 //===----------------------------------------------------------------------===//
52 #include "AMDGPUSubtarget.h"
53 #include "SIInstrInfo.h"
54 #include "SIMachineFunctionInfo.h"
55 #include "llvm/CodeGen/MachineFrameInfo.h"
56 #include "llvm/CodeGen/MachineFunction.h"
57 #include "llvm/CodeGen/MachineFunctionPass.h"
58 #include "llvm/CodeGen/MachineInstrBuilder.h"
59 #include "llvm/CodeGen/MachineRegisterInfo.h"
60 #include "llvm/IR/Constants.h"
66 class SILowerControlFlowPass : public MachineFunctionPass {
69 static const unsigned SkipThreshold = 12;
72 const SIRegisterInfo *TRI;
73 const SIInstrInfo *TII;
75 bool shouldSkip(MachineBasicBlock *From, MachineBasicBlock *To);
77 void Skip(MachineInstr &From, MachineOperand &To);
78 void SkipIfDead(MachineInstr &MI);
80 void If(MachineInstr &MI);
81 void Else(MachineInstr &MI);
82 void Break(MachineInstr &MI);
83 void IfBreak(MachineInstr &MI);
84 void ElseBreak(MachineInstr &MI);
85 void Loop(MachineInstr &MI);
86 void EndCf(MachineInstr &MI);
88 void Kill(MachineInstr &MI);
89 void Branch(MachineInstr &MI);
91 void LoadM0(MachineInstr &MI, MachineInstr *MovRel, int Offset = 0);
92 void computeIndirectRegAndOffset(unsigned VecReg, unsigned &Reg, int &Offset);
93 void IndirectSrc(MachineInstr &MI);
94 void IndirectDst(MachineInstr &MI);
97 SILowerControlFlowPass(TargetMachine &tm) :
98 MachineFunctionPass(ID), TRI(nullptr), TII(nullptr) { }
100 bool runOnMachineFunction(MachineFunction &MF) override;
102 const char *getPassName() const override {
103 return "SI Lower control flow instructions";
108 } // End anonymous namespace
110 char SILowerControlFlowPass::ID = 0;
112 FunctionPass *llvm::createSILowerControlFlowPass(TargetMachine &tm) {
113 return new SILowerControlFlowPass(tm);
116 bool SILowerControlFlowPass::shouldSkip(MachineBasicBlock *From,
117 MachineBasicBlock *To) {
119 unsigned NumInstr = 0;
121 for (MachineBasicBlock *MBB = From; MBB != To && !MBB->succ_empty();
122 MBB = *MBB->succ_begin()) {
124 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
125 NumInstr < SkipThreshold && I != E; ++I) {
127 if (I->isBundle() || !I->isBundled())
128 if (++NumInstr >= SkipThreshold)
136 void SILowerControlFlowPass::Skip(MachineInstr &From, MachineOperand &To) {
138 if (!shouldSkip(*From.getParent()->succ_begin(), To.getMBB()))
141 DebugLoc DL = From.getDebugLoc();
142 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
144 .addReg(AMDGPU::EXEC);
147 void SILowerControlFlowPass::SkipIfDead(MachineInstr &MI) {
149 MachineBasicBlock &MBB = *MI.getParent();
150 DebugLoc DL = MI.getDebugLoc();
152 if (MBB.getParent()->getInfo<SIMachineFunctionInfo>()->getShaderType() !=
154 !shouldSkip(&MBB, &MBB.getParent()->back()))
157 MachineBasicBlock::iterator Insert = &MI;
160 // If the exec mask is non-zero, skip the next two instructions
161 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
163 .addReg(AMDGPU::EXEC);
165 // Exec mask is zero: Export to NULL target...
166 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP))
168 .addImm(0x09) // V_008DFC_SQ_EXP_NULL
172 .addReg(AMDGPU::VGPR0)
173 .addReg(AMDGPU::VGPR0)
174 .addReg(AMDGPU::VGPR0)
175 .addReg(AMDGPU::VGPR0);
177 // ... and terminate wavefront
178 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
181 void SILowerControlFlowPass::If(MachineInstr &MI) {
182 MachineBasicBlock &MBB = *MI.getParent();
183 DebugLoc DL = MI.getDebugLoc();
184 unsigned Reg = MI.getOperand(0).getReg();
185 unsigned Vcc = MI.getOperand(1).getReg();
187 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
190 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
191 .addReg(AMDGPU::EXEC)
194 Skip(MI, MI.getOperand(2));
196 MI.eraseFromParent();
199 void SILowerControlFlowPass::Else(MachineInstr &MI) {
200 MachineBasicBlock &MBB = *MI.getParent();
201 DebugLoc DL = MI.getDebugLoc();
202 unsigned Dst = MI.getOperand(0).getReg();
203 unsigned Src = MI.getOperand(1).getReg();
205 BuildMI(MBB, MBB.getFirstNonPHI(), DL,
206 TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
207 .addReg(Src); // Saved EXEC
209 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
210 .addReg(AMDGPU::EXEC)
213 Skip(MI, MI.getOperand(2));
215 MI.eraseFromParent();
218 void SILowerControlFlowPass::Break(MachineInstr &MI) {
219 MachineBasicBlock &MBB = *MI.getParent();
220 DebugLoc DL = MI.getDebugLoc();
222 unsigned Dst = MI.getOperand(0).getReg();
223 unsigned Src = MI.getOperand(1).getReg();
225 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
226 .addReg(AMDGPU::EXEC)
229 MI.eraseFromParent();
232 void SILowerControlFlowPass::IfBreak(MachineInstr &MI) {
233 MachineBasicBlock &MBB = *MI.getParent();
234 DebugLoc DL = MI.getDebugLoc();
236 unsigned Dst = MI.getOperand(0).getReg();
237 unsigned Vcc = MI.getOperand(1).getReg();
238 unsigned Src = MI.getOperand(2).getReg();
240 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
244 MI.eraseFromParent();
247 void SILowerControlFlowPass::ElseBreak(MachineInstr &MI) {
248 MachineBasicBlock &MBB = *MI.getParent();
249 DebugLoc DL = MI.getDebugLoc();
251 unsigned Dst = MI.getOperand(0).getReg();
252 unsigned Saved = MI.getOperand(1).getReg();
253 unsigned Src = MI.getOperand(2).getReg();
255 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
259 MI.eraseFromParent();
262 void SILowerControlFlowPass::Loop(MachineInstr &MI) {
263 MachineBasicBlock &MBB = *MI.getParent();
264 DebugLoc DL = MI.getDebugLoc();
265 unsigned Src = MI.getOperand(0).getReg();
267 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ANDN2_B64), AMDGPU::EXEC)
268 .addReg(AMDGPU::EXEC)
271 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
272 .addOperand(MI.getOperand(1))
273 .addReg(AMDGPU::EXEC);
275 MI.eraseFromParent();
278 void SILowerControlFlowPass::EndCf(MachineInstr &MI) {
279 MachineBasicBlock &MBB = *MI.getParent();
280 DebugLoc DL = MI.getDebugLoc();
281 unsigned Reg = MI.getOperand(0).getReg();
283 BuildMI(MBB, MBB.getFirstNonPHI(), DL,
284 TII->get(AMDGPU::S_OR_B64), AMDGPU::EXEC)
285 .addReg(AMDGPU::EXEC)
288 MI.eraseFromParent();
291 void SILowerControlFlowPass::Branch(MachineInstr &MI) {
292 if (MI.getOperand(0).getMBB() == MI.getParent()->getNextNode())
293 MI.eraseFromParent();
295 // If these aren't equal, this is probably an infinite loop.
298 void SILowerControlFlowPass::Kill(MachineInstr &MI) {
299 MachineBasicBlock &MBB = *MI.getParent();
300 DebugLoc DL = MI.getDebugLoc();
301 const MachineOperand &Op = MI.getOperand(0);
304 const SIMachineFunctionInfo *MFI
305 = MBB.getParent()->getInfo<SIMachineFunctionInfo>();
306 // Kill is only allowed in pixel / geometry shaders.
307 assert(MFI->getShaderType() == ShaderType::PIXEL ||
308 MFI->getShaderType() == ShaderType::GEOMETRY);
311 // Clear this thread from the exec mask if the operand is negative
313 // Constant operand: Set exec mask to 0 or do nothing
314 if (Op.getImm() & 0x80000000) {
315 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
319 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC)
324 MI.eraseFromParent();
327 void SILowerControlFlowPass::LoadM0(MachineInstr &MI, MachineInstr *MovRel, int Offset) {
329 MachineBasicBlock &MBB = *MI.getParent();
330 DebugLoc DL = MI.getDebugLoc();
331 MachineBasicBlock::iterator I = MI;
333 unsigned Save = MI.getOperand(1).getReg();
334 unsigned Idx = MI.getOperand(3).getReg();
336 if (AMDGPU::SReg_32RegClass.contains(Idx)) {
338 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
342 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
345 MBB.insert(I, MovRel);
348 assert(AMDGPU::SReg_64RegClass.contains(Save));
349 assert(AMDGPU::VGPR_32RegClass.contains(Idx));
351 // Save the EXEC mask
352 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), Save)
353 .addReg(AMDGPU::EXEC);
355 // Read the next variant into VCC (lower 32 bits) <- also loop target
356 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
360 // Move index from VCC into M0
361 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
362 .addReg(AMDGPU::VCC_LO);
364 // Compare the just read M0 value to all possible Idx values
365 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e32), AMDGPU::VCC)
369 // Update EXEC, save the original EXEC value to VCC
370 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), AMDGPU::VCC)
371 .addReg(AMDGPU::VCC);
374 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
378 // Do the actual move
379 MBB.insert(I, MovRel);
381 // Update EXEC, switch all done bits to 0 and all todo bits to 1
382 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
383 .addReg(AMDGPU::EXEC)
384 .addReg(AMDGPU::VCC);
386 // Loop back to V_READFIRSTLANE_B32 if there are still variants to cover
387 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
389 .addReg(AMDGPU::EXEC);
392 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
396 MI.eraseFromParent();
399 /// \param @VecReg The register which holds element zero of the vector
400 /// being addressed into.
401 /// \param[out] @Reg The base register to use in the indirect addressing instruction.
402 /// \param[in,out] @Offset As an input, this is the constant offset part of the
403 // indirect Index. e.g. v0 = v[VecReg + Offset]
404 // As an output, this is a constant value that needs
405 // to be added to the value stored in M0.
406 void SILowerControlFlowPass::computeIndirectRegAndOffset(unsigned VecReg,
409 unsigned SubReg = TRI->getSubReg(VecReg, AMDGPU::sub0);
413 const TargetRegisterClass *RC = TRI->getPhysRegClass(SubReg);
414 int RegIdx = TRI->getHWRegIndex(SubReg) + Offset;
423 Reg = RC->getRegister(RegIdx);
426 void SILowerControlFlowPass::IndirectSrc(MachineInstr &MI) {
428 MachineBasicBlock &MBB = *MI.getParent();
429 DebugLoc DL = MI.getDebugLoc();
431 unsigned Dst = MI.getOperand(0).getReg();
432 unsigned Vec = MI.getOperand(2).getReg();
433 int Off = MI.getOperand(4).getImm();
436 computeIndirectRegAndOffset(Vec, Reg, Off);
438 MachineInstr *MovRel =
439 BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
441 .addReg(AMDGPU::M0, RegState::Implicit)
442 .addReg(Vec, RegState::Implicit);
444 LoadM0(MI, MovRel, Off);
447 void SILowerControlFlowPass::IndirectDst(MachineInstr &MI) {
449 MachineBasicBlock &MBB = *MI.getParent();
450 DebugLoc DL = MI.getDebugLoc();
452 unsigned Dst = MI.getOperand(0).getReg();
453 int Off = MI.getOperand(4).getImm();
454 unsigned Val = MI.getOperand(5).getReg();
457 computeIndirectRegAndOffset(Dst, Reg, Off);
459 MachineInstr *MovRel =
460 BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELD_B32_e32))
461 .addReg(Reg, RegState::Define)
463 .addReg(AMDGPU::M0, RegState::Implicit)
464 .addReg(Dst, RegState::Implicit);
466 LoadM0(MI, MovRel, Off);
469 bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
470 TII = static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo());
472 static_cast<const SIRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
473 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
475 bool HaveKill = false;
476 bool NeedWQM = false;
477 bool NeedFlat = false;
480 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
483 MachineBasicBlock &MBB = *BI;
484 MachineBasicBlock::iterator I, Next;
485 for (I = MBB.begin(); I != MBB.end(); I = Next) {
488 MachineInstr &MI = *I;
489 if (TII->isWQM(MI.getOpcode()) || TII->isDS(MI.getOpcode()))
492 // Flat uses m0 in case it needs to access LDS.
493 if (TII->isFLAT(MI.getOpcode()))
496 switch (MI.getOpcode()) {
503 case AMDGPU::SI_ELSE:
507 case AMDGPU::SI_BREAK:
511 case AMDGPU::SI_IF_BREAK:
515 case AMDGPU::SI_ELSE_BREAK:
519 case AMDGPU::SI_LOOP:
524 case AMDGPU::SI_END_CF:
525 if (--Depth == 0 && HaveKill) {
532 case AMDGPU::SI_KILL:
540 case AMDGPU::S_BRANCH:
544 case AMDGPU::SI_INDIRECT_SRC:
548 case AMDGPU::SI_INDIRECT_DST_V1:
549 case AMDGPU::SI_INDIRECT_DST_V2:
550 case AMDGPU::SI_INDIRECT_DST_V4:
551 case AMDGPU::SI_INDIRECT_DST_V8:
552 case AMDGPU::SI_INDIRECT_DST_V16:
559 if (NeedWQM && MFI->getShaderType() == ShaderType::PIXEL) {
560 MachineBasicBlock &MBB = MF.front();
561 BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_WQM_B64),
562 AMDGPU::EXEC).addReg(AMDGPU::EXEC);
565 // FIXME: This seems inappropriate to do here.
566 if (NeedFlat && MFI->IsKernel) {
567 // Insert the prologue initializing the SGPRs pointing to the scratch space
568 // for flat accesses.
569 const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
571 // TODO: What to use with function calls?
573 // FIXME: This is reporting stack size that is used in a scratch buffer
574 // rather than registers as well.
575 uint64_t StackSizeBytes = FrameInfo->getStackSize();
578 = static_cast<const AMDGPUInstrInfo*>(TII)->getIndirectIndexBegin(MF);
579 // Convert register index to 256-byte unit.
580 uint64_t StackOffset = IndirectBegin < 0 ? 0 : (4 * IndirectBegin / 256);
582 assert((StackSizeBytes < 0xffff) && StackOffset < 0xffff &&
583 "Stack limits should be smaller than 16-bits");
585 // Initialize the flat scratch register pair.
586 // TODO: Can we use one s_mov_b64 here?
588 // Offset is in units of 256-bytes.
589 MachineBasicBlock &MBB = MF.front();
591 MachineBasicBlock::iterator Start = MBB.getFirstNonPHI();
592 const MCInstrDesc &SMovK = TII->get(AMDGPU::S_MOVK_I32);
594 assert(isInt<16>(StackOffset) && isInt<16>(StackSizeBytes));
596 BuildMI(MBB, Start, NoDL, SMovK, AMDGPU::FLAT_SCR_LO)
597 .addImm(StackOffset);
599 // Documentation says size is "per-thread scratch size in bytes"
600 BuildMI(MBB, Start, NoDL, SMovK, AMDGPU::FLAT_SCR_HI)
601 .addImm(StackSizeBytes);