1 //===- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface -*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_R600_SIMACHINEFUNCTIONINFO_H
16 #define LLVM_LIB_TARGET_R600_SIMACHINEFUNCTIONINFO_H
18 #include "AMDGPUMachineFunction.h"
19 #include "SIRegisterInfo.h"
24 class MachineRegisterInfo;
26 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
27 /// tells the hardware which interpolation parameters to load.
28 class SIMachineFunctionInfo : public AMDGPUMachineFunction {
29 void anchor() override;
40 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { }
41 SpilledReg() : VGPR(0), Lane(-1) { }
42 bool hasLane() { return Lane != -1;}
45 // SIMachineFunctionInfo definition
47 SIMachineFunctionInfo(const MachineFunction &MF);
48 SpilledReg getSpilledReg(MachineFunction *MF, unsigned FrameIndex,
51 unsigned NumUserSGPRs;
52 std::map<unsigned, unsigned> LaneVGPRs;
53 unsigned LDSWaveSpillSize;
54 unsigned ScratchOffsetReg;
55 bool hasCalculatedTID() const { return TIDReg != AMDGPU::NoRegister; };
56 unsigned getTIDReg() const { return TIDReg; };
57 void setTIDReg(unsigned Reg) { TIDReg = Reg; }
59 bool hasSpilledSGPRs() const {
60 return HasSpilledSGPRs;
63 void setHasSpilledSGPRs(bool Spill = true) {
64 HasSpilledSGPRs = Spill;
67 bool hasSpilledVGPRs() const {
68 return HasSpilledVGPRs;
71 void setHasSpilledVGPRs(bool Spill = true) {
72 HasSpilledVGPRs = Spill;
75 unsigned getMaximumWorkGroupSize(const MachineFunction &MF) const;
78 } // End namespace llvm