1 //===- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface -*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_R600_SIMACHINEFUNCTIONINFO_H
16 #define LLVM_LIB_TARGET_R600_SIMACHINEFUNCTIONINFO_H
18 #include "AMDGPUMachineFunction.h"
19 #include "SIRegisterInfo.h"
24 class MachineRegisterInfo;
26 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
27 /// tells the hardware which interpolation parameters to load.
28 class SIMachineFunctionInfo : public AMDGPUMachineFunction {
29 // FIXME: This should be removed and getPreloadedValue moved here.
30 friend struct SIRegisterInfo;
31 void anchor() override;
35 // Registers that may be reserved for spilling purposes. These may be the same
36 // as the input registers.
37 unsigned ScratchRSrcReg;
38 unsigned ScratchWaveOffsetReg;
40 // Input registers setup for the HSA ABI.
41 // User SGPRs in allocation order.
42 unsigned PrivateSegmentBufferUserSGPR;
43 unsigned DispatchPtrUserSGPR;
44 unsigned QueuePtrUserSGPR;
45 unsigned KernargSegmentPtrUserSGPR;
46 unsigned DispatchIDUserSGPR;
47 unsigned FlatScratchInitUserSGPR;
48 unsigned PrivateSegmentSizeUserSGPR;
49 unsigned GridWorkGroupCountXUserSGPR;
50 unsigned GridWorkGroupCountYUserSGPR;
51 unsigned GridWorkGroupCountZUserSGPR;
53 // System SGPRs in allocation order.
54 unsigned WorkGroupIDXSystemSGPR;
55 unsigned WorkGroupIDYSystemSGPR;
56 unsigned WorkGroupIDZSystemSGPR;
57 unsigned WorkGroupInfoSystemSGPR;
58 unsigned PrivateSegmentWaveByteOffsetSystemSGPR;
65 // FIXME: Make private
66 unsigned LDSWaveSpillSize;
68 std::map<unsigned, unsigned> LaneVGPRs;
69 unsigned ScratchOffsetReg;
70 unsigned NumUserSGPRs;
71 unsigned NumSystemSGPRs;
77 // Feature bits required for inputs passed in user SGPRs.
78 bool PrivateSegmentBuffer : 1;
82 bool KernargSegmentPtr : 1;
83 bool FlatScratchInit : 1;
84 bool GridWorkgroupCountX : 1;
85 bool GridWorkgroupCountY : 1;
86 bool GridWorkgroupCountZ : 1;
88 // Feature bits required for inputs passed in system SGPRs.
89 bool WorkGroupIDX : 1; // Always initialized.
90 bool WorkGroupIDY : 1;
91 bool WorkGroupIDZ : 1;
92 bool WorkGroupInfo : 1;
93 bool PrivateSegmentWaveByteOffset : 1;
95 bool WorkItemIDX : 1; // Always initialized.
100 MCPhysReg getNextUserSGPR() const {
101 assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
102 return AMDGPU::SGPR0 + NumUserSGPRs;
105 MCPhysReg getNextSystemSGPR() const {
106 return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
113 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { }
114 SpilledReg() : VGPR(0), Lane(-1) { }
115 bool hasLane() { return Lane != -1;}
118 // SIMachineFunctionInfo definition
120 SIMachineFunctionInfo(const MachineFunction &MF);
121 SpilledReg getSpilledReg(MachineFunction *MF, unsigned FrameIndex,
123 bool hasCalculatedTID() const { return TIDReg != AMDGPU::NoRegister; };
124 unsigned getTIDReg() const { return TIDReg; };
125 void setTIDReg(unsigned Reg) { TIDReg = Reg; }
128 unsigned addPrivateSegmentBuffer(const SIRegisterInfo &TRI);
129 unsigned addDispatchPtr(const SIRegisterInfo &TRI);
130 unsigned addQueuePtr(const SIRegisterInfo &TRI);
131 unsigned addKernargSegmentPtr(const SIRegisterInfo &TRI);
134 unsigned addWorkGroupIDX() {
135 WorkGroupIDXSystemSGPR = getNextSystemSGPR();
137 return WorkGroupIDXSystemSGPR;
140 unsigned addWorkGroupIDY() {
141 WorkGroupIDYSystemSGPR = getNextSystemSGPR();
143 return WorkGroupIDYSystemSGPR;
146 unsigned addWorkGroupIDZ() {
147 WorkGroupIDZSystemSGPR = getNextSystemSGPR();
149 return WorkGroupIDZSystemSGPR;
152 unsigned addWorkGroupInfo() {
153 WorkGroupInfoSystemSGPR = getNextSystemSGPR();
155 return WorkGroupInfoSystemSGPR;
158 unsigned addPrivateSegmentWaveByteOffset() {
159 PrivateSegmentWaveByteOffsetSystemSGPR = getNextSystemSGPR();
161 return PrivateSegmentWaveByteOffsetSystemSGPR;
164 bool hasPrivateSegmentBuffer() const {
165 return PrivateSegmentBuffer;
168 bool hasDispatchPtr() const {
172 bool hasQueuePtr() const {
176 bool hasDispatchID() const {
180 bool hasKernargSegmentPtr() const {
181 return KernargSegmentPtr;
184 bool hasFlatScratchInit() const {
185 return FlatScratchInit;
188 bool hasGridWorkgroupCountX() const {
189 return GridWorkgroupCountX;
192 bool hasGridWorkgroupCountY() const {
193 return GridWorkgroupCountY;
196 bool hasGridWorkgroupCountZ() const {
197 return GridWorkgroupCountZ;
200 bool hasWorkGroupIDX() const {
204 bool hasWorkGroupIDY() const {
208 bool hasWorkGroupIDZ() const {
212 bool hasWorkGroupInfo() const {
213 return WorkGroupInfo;
216 bool hasPrivateSegmentWaveByteOffset() const {
217 return PrivateSegmentWaveByteOffset;
220 bool hasWorkItemIDX() const {
224 bool hasWorkItemIDY() const {
228 bool hasWorkItemIDZ() const {
232 unsigned getNumUserSGPRs() const {
236 unsigned getNumPreloadedSGPRs() const {
237 return NumUserSGPRs + NumSystemSGPRs;
240 unsigned getPrivateSegmentWaveByteOffsetSystemSGPR() const {
241 return PrivateSegmentWaveByteOffsetSystemSGPR;
244 /// \brief Returns the physical register reserved for use as the resource
245 /// descriptor for scratch accesses.
246 unsigned getScratchRSrcReg() const {
247 return ScratchRSrcReg;
250 void setScratchRSrcReg(unsigned Reg) {
251 assert(Reg != AMDGPU::NoRegister && "Should never be unset");
252 ScratchRSrcReg = Reg;
255 unsigned getScratchWaveOffsetReg() const {
256 return ScratchWaveOffsetReg;
259 void setScratchWaveOffsetReg(unsigned Reg) {
260 assert(Reg != AMDGPU::NoRegister && "Should never be unset");
261 ScratchWaveOffsetReg = Reg;
264 bool hasSpilledSGPRs() const {
265 return HasSpilledSGPRs;
268 void setHasSpilledSGPRs(bool Spill = true) {
269 HasSpilledSGPRs = Spill;
272 bool hasSpilledVGPRs() const {
273 return HasSpilledVGPRs;
276 void setHasSpilledVGPRs(bool Spill = true) {
277 HasSpilledVGPRs = Spill;
280 unsigned getPSInputAddr() const {
284 bool isPSInputAllocated(unsigned Index) const {
285 return PSInputAddr & (1 << Index);
288 void markPSInputAllocated(unsigned Index) {
289 PSInputAddr |= 1 << Index;
292 bool returnsVoid() const {
296 void setIfReturnsVoid(bool Value) {
300 unsigned getMaximumWorkGroupSize(const MachineFunction &MF) const;
303 } // End namespace llvm