1 //===-- SIPrepareScratchRegs.cpp - Use predicates for control flow --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 /// This pass loads scratch pointer and scratch offset into a register or a
13 /// frame index which can be used anywhere in the program. These values will
14 /// be used for spilling VGPRs.
16 //===----------------------------------------------------------------------===//
19 #include "AMDGPUSubtarget.h"
20 #include "SIDefines.h"
21 #include "SIInstrInfo.h"
22 #include "SIMachineFunctionInfo.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/LLVMContext.h"
36 class SIPrepareScratchRegs : public MachineFunctionPass {
42 SIPrepareScratchRegs() : MachineFunctionPass(ID) { }
44 bool runOnMachineFunction(MachineFunction &MF) override;
46 const char *getPassName() const override {
47 return "SI prepare scratch registers";
50 void getAnalysisUsage(AnalysisUsage &AU) const override {
52 MachineFunctionPass::getAnalysisUsage(AU);
56 } // End anonymous namespace
58 char SIPrepareScratchRegs::ID = 0;
60 FunctionPass *llvm::createSIPrepareScratchRegs() {
61 return new SIPrepareScratchRegs();
64 bool SIPrepareScratchRegs::runOnMachineFunction(MachineFunction &MF) {
65 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
66 const SIInstrInfo *TII =
67 static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo());
68 const SIRegisterInfo *TRI = &TII->getRegisterInfo();
69 MachineRegisterInfo &MRI = MF.getRegInfo();
70 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
71 MachineBasicBlock *Entry = &MF.front();
72 MachineBasicBlock::iterator I = Entry->begin();
73 DebugLoc DL = I->getDebugLoc();
75 // FIXME: If we don't have enough VGPRs for SGPR spilling we will need to
77 if (!MFI->hasSpilledVGPRs())
80 unsigned ScratchPtrPreloadReg =
81 TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_PTR);
82 unsigned ScratchOffsetPreloadReg =
83 TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_WAVE_OFFSET);
85 if (!Entry->isLiveIn(ScratchPtrPreloadReg))
86 Entry->addLiveIn(ScratchPtrPreloadReg);
88 if (!Entry->isLiveIn(ScratchOffsetPreloadReg))
89 Entry->addLiveIn(ScratchOffsetPreloadReg);
91 // Load the scratch offset.
92 unsigned ScratchOffsetReg =
93 TRI->findUnusedRegister(MRI, &AMDGPU::SGPR_32RegClass);
94 int ScratchOffsetFI = -1;
96 if (ScratchOffsetReg != AMDGPU::NoRegister) {
97 // Found an SGPR to use
98 BuildMI(*Entry, I, DL, TII->get(AMDGPU::S_MOV_B32), ScratchOffsetReg)
99 .addReg(ScratchOffsetPreloadReg);
101 // No SGPR is available, we must spill.
102 ScratchOffsetFI = FrameInfo->CreateSpillStackObject(4,4);
103 BuildMI(*Entry, I, DL, TII->get(AMDGPU::SI_SPILL_S32_SAVE))
104 .addReg(ScratchOffsetPreloadReg)
105 .addFrameIndex(ScratchOffsetFI)
106 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
107 .addReg(AMDGPU::SGPR0, RegState::Undef);
111 // Now that we have the scratch pointer and offset values, we need to
112 // add them to all the SI_SPILL_V* instructions.
115 unsigned ScratchRsrcFI = FrameInfo->CreateSpillStackObject(16, 4);
116 RS.addScavengingFrameIndex(ScratchRsrcFI);
118 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
121 MachineBasicBlock &MBB = *BI;
122 // Add the scratch offset reg as a live-in so that the register scavenger
123 // doesn't re-use it.
124 if (!MBB.isLiveIn(ScratchOffsetReg) &&
125 ScratchOffsetReg != AMDGPU::NoRegister)
126 MBB.addLiveIn(ScratchOffsetReg);
127 RS.enterBasicBlock(&MBB);
129 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
131 MachineInstr &MI = *I;
133 DebugLoc DL = MI.getDebugLoc();
134 if (!TII->isVGPRSpill(MI.getOpcode()))
138 unsigned ScratchRsrcReg =
139 RS.scavengeRegister(&AMDGPU::SReg_128RegClass, 0);
141 uint64_t Rsrc23 = TII->getScratchRsrcWords23();
143 unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
144 unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
145 unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);
146 unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);
148 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc0)
149 .addExternalSymbol("SCRATCH_RSRC_DWORD0")
150 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
152 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc1)
153 .addExternalSymbol("SCRATCH_RSRC_DWORD1")
154 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
156 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc2)
157 .addImm(Rsrc23 & 0xffffffff)
158 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
160 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc3)
161 .addImm(Rsrc23 >> 32)
162 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
165 if (ScratchOffsetReg == AMDGPU::NoRegister) {
166 ScratchOffsetReg = RS.scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
167 BuildMI(MBB, I, DL, TII->get(AMDGPU::SI_SPILL_S32_RESTORE),
169 .addFrameIndex(ScratchOffsetFI)
170 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
171 .addReg(AMDGPU::SGPR0, RegState::Undef);
172 } else if (!MBB.isLiveIn(ScratchOffsetReg)) {
173 MBB.addLiveIn(ScratchOffsetReg);
176 if (ScratchRsrcReg == AMDGPU::NoRegister ||
177 ScratchOffsetReg == AMDGPU::NoRegister) {
178 LLVMContext &Ctx = MF.getFunction()->getContext();
179 Ctx.emitError("ran out of SGPRs for spilling VGPRs");
180 ScratchRsrcReg = AMDGPU::SGPR0;
181 ScratchOffsetReg = AMDGPU::SGPR0;
183 MI.getOperand(2).setReg(ScratchRsrcReg);
184 MI.getOperand(2).setIsKill(true);
185 MI.getOperand(2).setIsUndef(false);
186 MI.getOperand(3).setReg(ScratchOffsetReg);
187 MI.getOperand(3).setIsUndef(false);
188 MI.getOperand(3).setIsKill(false);
189 MI.addOperand(MachineOperand::CreateReg(Rsrc0, false, true, true));
190 MI.addOperand(MachineOperand::CreateReg(Rsrc1, false, true, true));
191 MI.addOperand(MachineOperand::CreateReg(Rsrc2, false, true, true));
192 MI.addOperand(MachineOperand::CreateReg(Rsrc3, false, true, true));