1 //===-- SIPrepareScratchRegs.cpp - Use predicates for control flow --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 /// This pass loads scratch pointer and scratch offset into a register or a
13 /// frame index which can be used anywhere in the program. These values will
14 /// be used for spilling VGPRs.
16 //===----------------------------------------------------------------------===//
19 #include "AMDGPUSubtarget.h"
20 #include "SIDefines.h"
21 #include "SIInstrInfo.h"
22 #include "SIMachineFunctionInfo.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/LLVMContext.h"
36 class SIPrepareScratchRegs : public MachineFunctionPass {
42 SIPrepareScratchRegs() : MachineFunctionPass(ID) { }
44 bool runOnMachineFunction(MachineFunction &MF) override;
46 const char *getPassName() const override {
47 return "SI prepare scratch registers";
52 } // End anonymous namespace
54 char SIPrepareScratchRegs::ID = 0;
56 FunctionPass *llvm::createSIPrepareScratchRegs() {
57 return new SIPrepareScratchRegs();
60 bool SIPrepareScratchRegs::runOnMachineFunction(MachineFunction &MF) {
61 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
62 const SIInstrInfo *TII =
63 static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo());
64 const SIRegisterInfo *TRI = &TII->getRegisterInfo();
65 MachineRegisterInfo &MRI = MF.getRegInfo();
66 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
67 MachineBasicBlock *Entry = MF.begin();
68 MachineBasicBlock::iterator I = Entry->begin();
69 DebugLoc DL = I->getDebugLoc();
71 // FIXME: If we don't have enough VGPRs for SGPR spilling we will need to
73 if (!MFI->hasSpilledVGPRs())
76 unsigned ScratchPtrPreloadReg =
77 TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_PTR);
78 unsigned ScratchOffsetPreloadReg =
79 TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_WAVE_OFFSET);
81 if (!Entry->isLiveIn(ScratchPtrPreloadReg))
82 Entry->addLiveIn(ScratchPtrPreloadReg);
84 if (!Entry->isLiveIn(ScratchOffsetPreloadReg))
85 Entry->addLiveIn(ScratchOffsetPreloadReg);
87 // Load the scratch offset.
88 unsigned ScratchOffsetReg =
89 TRI->findUnusedRegister(MRI, &AMDGPU::SGPR_32RegClass);
90 int ScratchOffsetFI = -1;
92 if (ScratchOffsetReg != AMDGPU::NoRegister) {
93 // Found an SGPR to use
94 BuildMI(*Entry, I, DL, TII->get(AMDGPU::S_MOV_B32), ScratchOffsetReg)
95 .addReg(ScratchOffsetPreloadReg);
97 // No SGPR is available, we must spill.
98 ScratchOffsetFI = FrameInfo->CreateSpillStackObject(4,4);
99 BuildMI(*Entry, I, DL, TII->get(AMDGPU::SI_SPILL_S32_SAVE))
100 .addReg(ScratchOffsetPreloadReg)
101 .addFrameIndex(ScratchOffsetFI)
102 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
103 .addReg(AMDGPU::SGPR0, RegState::Undef);
107 // Now that we have the scratch pointer and offset values, we need to
108 // add them to all the SI_SPILL_V* instructions.
111 unsigned ScratchRsrcFI = FrameInfo->CreateSpillStackObject(16, 4);
112 RS.addScavengingFrameIndex(ScratchRsrcFI);
114 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
117 MachineBasicBlock &MBB = *BI;
118 // Add the scratch offset reg as a live-in so that the register scavenger
119 // doesn't re-use it.
120 if (!MBB.isLiveIn(ScratchOffsetReg) &&
121 ScratchOffsetReg != AMDGPU::NoRegister)
122 MBB.addLiveIn(ScratchOffsetReg);
123 RS.enterBasicBlock(&MBB);
125 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
127 MachineInstr &MI = *I;
129 DebugLoc DL = MI.getDebugLoc();
130 if (!TII->isVGPRSpill(MI.getOpcode()))
134 unsigned ScratchRsrcReg =
135 RS.scavengeRegister(&AMDGPU::SReg_128RegClass, 0);
137 uint64_t Rsrc = AMDGPU::RSRC_DATA_FORMAT | AMDGPU::RSRC_TID_ENABLE |
140 unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
141 unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
142 unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);
143 unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);
145 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc0)
146 .addExternalSymbol("SCRATCH_RSRC_DWORD0")
147 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
149 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc1)
150 .addExternalSymbol("SCRATCH_RSRC_DWORD1")
151 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
153 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc2)
154 .addImm(Rsrc & 0xffffffff)
155 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
157 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc3)
159 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
162 if (ScratchOffsetReg == AMDGPU::NoRegister) {
163 ScratchOffsetReg = RS.scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
164 BuildMI(MBB, I, DL, TII->get(AMDGPU::SI_SPILL_S32_RESTORE),
166 .addFrameIndex(ScratchOffsetFI)
167 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
168 .addReg(AMDGPU::SGPR0, RegState::Undef);
169 } else if (!MBB.isLiveIn(ScratchOffsetReg)) {
170 MBB.addLiveIn(ScratchOffsetReg);
173 if (ScratchRsrcReg == AMDGPU::NoRegister ||
174 ScratchOffsetReg == AMDGPU::NoRegister) {
175 LLVMContext &Ctx = MF.getFunction()->getContext();
176 Ctx.emitError("ran out of SGPRs for spilling VGPRs");
177 ScratchRsrcReg = AMDGPU::SGPR0;
178 ScratchOffsetReg = AMDGPU::SGPR0;
180 MI.getOperand(2).setReg(ScratchRsrcReg);
181 MI.getOperand(2).setIsKill(true);
182 MI.getOperand(2).setIsUndef(false);
183 MI.getOperand(3).setReg(ScratchOffsetReg);
184 MI.getOperand(3).setIsUndef(false);
185 MI.getOperand(3).setIsKill(false);
186 MI.addOperand(MachineOperand::CreateReg(Rsrc0, false, true, true));
187 MI.addOperand(MachineOperand::CreateReg(Rsrc1, false, true, true));
188 MI.addOperand(MachineOperand::CreateReg(Rsrc2, false, true, true));
189 MI.addOperand(MachineOperand::CreateReg(Rsrc3, false, true, true));