1 //===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI implementation of the TargetRegisterInfo class.
13 //===----------------------------------------------------------------------===//
15 #include "SIRegisterInfo.h"
16 #include "SIInstrInfo.h"
17 #include "SIMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/RegisterScavenging.h"
21 #include "llvm/IR/Function.h"
22 #include "llvm/IR/LLVMContext.h"
26 SIRegisterInfo::SIRegisterInfo() : AMDGPURegisterInfo() {}
28 void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
29 MCRegAliasIterator R(Reg, this, true);
31 for (; R.isValid(); ++R)
35 BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
36 BitVector Reserved(getNumRegs());
37 Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
39 // EXEC_LO and EXEC_HI could be allocated and used as regular register, but
40 // this seems likely to result in bugs, so I'm marking them as reserved.
41 reserveRegisterTuples(Reserved, AMDGPU::EXEC);
42 reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR);
44 // Reserve some VGPRs to use as temp registers in case we have to spill VGPRs
45 reserveRegisterTuples(Reserved, AMDGPU::VGPR254);
46 reserveRegisterTuples(Reserved, AMDGPU::VGPR255);
48 // Tonga and Iceland can only allocate a fixed number of SGPRs due
50 if (MF.getSubtarget<AMDGPUSubtarget>().hasSGPRInitBug()) {
51 unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
52 // Reserve some SGPRs for FLAT_SCRATCH and VCC (4 SGPRs).
53 // Assume XNACK_MASK is unused.
54 unsigned Limit = AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG - 4;
56 for (unsigned i = Limit; i < NumSGPRs; ++i) {
57 unsigned Reg = AMDGPU::SGPR_32RegClass.getRegister(i);
58 reserveRegisterTuples(Reserved, Reg);
65 unsigned SIRegisterInfo::getRegPressureSetLimit(const MachineFunction &MF,
68 const AMDGPUSubtarget &STI = MF.getSubtarget<AMDGPUSubtarget>();
69 // FIXME: We should adjust the max number of waves based on LDS size.
70 unsigned SGPRLimit = getNumSGPRsAllowed(STI.getGeneration(),
71 STI.getMaxWavesPerCU());
72 unsigned VGPRLimit = getNumVGPRsAllowed(STI.getMaxWavesPerCU());
74 for (regclass_iterator I = regclass_begin(), E = regclass_end();
77 unsigned NumSubRegs = std::max((int)(*I)->getSize() / 4, 1);
80 if (isSGPRClass(*I)) {
81 Limit = SGPRLimit / NumSubRegs;
83 Limit = VGPRLimit / NumSubRegs;
86 const int *Sets = getRegClassPressureSets(*I);
88 for (unsigned i = 0; Sets[i] != -1; ++i) {
89 if (Sets[i] == (int)Idx)
96 bool SIRegisterInfo::requiresRegisterScavenging(const MachineFunction &Fn) const {
97 return Fn.getFrameInfo()->hasStackObjects();
100 static unsigned getNumSubRegsForSpillOp(unsigned Op) {
103 case AMDGPU::SI_SPILL_S512_SAVE:
104 case AMDGPU::SI_SPILL_S512_RESTORE:
105 case AMDGPU::SI_SPILL_V512_SAVE:
106 case AMDGPU::SI_SPILL_V512_RESTORE:
108 case AMDGPU::SI_SPILL_S256_SAVE:
109 case AMDGPU::SI_SPILL_S256_RESTORE:
110 case AMDGPU::SI_SPILL_V256_SAVE:
111 case AMDGPU::SI_SPILL_V256_RESTORE:
113 case AMDGPU::SI_SPILL_S128_SAVE:
114 case AMDGPU::SI_SPILL_S128_RESTORE:
115 case AMDGPU::SI_SPILL_V128_SAVE:
116 case AMDGPU::SI_SPILL_V128_RESTORE:
118 case AMDGPU::SI_SPILL_V96_SAVE:
119 case AMDGPU::SI_SPILL_V96_RESTORE:
121 case AMDGPU::SI_SPILL_S64_SAVE:
122 case AMDGPU::SI_SPILL_S64_RESTORE:
123 case AMDGPU::SI_SPILL_V64_SAVE:
124 case AMDGPU::SI_SPILL_V64_RESTORE:
126 case AMDGPU::SI_SPILL_S32_SAVE:
127 case AMDGPU::SI_SPILL_S32_RESTORE:
128 case AMDGPU::SI_SPILL_V32_SAVE:
129 case AMDGPU::SI_SPILL_V32_RESTORE:
131 default: llvm_unreachable("Invalid spill opcode");
135 void SIRegisterInfo::buildScratchLoadStore(MachineBasicBlock::iterator MI,
136 unsigned LoadStoreOp,
138 unsigned ScratchRsrcReg,
139 unsigned ScratchOffset,
141 RegScavenger *RS) const {
143 MachineBasicBlock *MBB = MI->getParent();
144 const MachineFunction *MF = MI->getParent()->getParent();
145 const SIInstrInfo *TII =
146 static_cast<const SIInstrInfo *>(MF->getSubtarget().getInstrInfo());
147 LLVMContext &Ctx = MF->getFunction()->getContext();
148 DebugLoc DL = MI->getDebugLoc();
149 bool IsLoad = TII->get(LoadStoreOp).mayLoad();
151 bool RanOutOfSGPRs = false;
152 unsigned SOffset = ScratchOffset;
154 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
155 unsigned Size = NumSubRegs * 4;
157 if (!isUInt<12>(Offset + Size)) {
158 SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0);
159 if (SOffset == AMDGPU::NoRegister) {
160 RanOutOfSGPRs = true;
161 SOffset = AMDGPU::SGPR0;
163 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), SOffset)
164 .addReg(ScratchOffset)
170 Ctx.emitError("Ran out of SGPRs for spilling VGPRS");
172 for (unsigned i = 0, e = NumSubRegs; i != e; ++i, Offset += 4) {
173 unsigned SubReg = NumSubRegs > 1 ?
174 getPhysRegSubReg(Value, &AMDGPU::VGPR_32RegClass, i) :
176 bool IsKill = (i == e - 1);
178 BuildMI(*MBB, MI, DL, TII->get(LoadStoreOp))
179 .addReg(SubReg, getDefRegState(IsLoad))
180 .addReg(ScratchRsrcReg, getKillRegState(IsKill))
186 .addReg(Value, RegState::Implicit | getDefRegState(IsLoad))
187 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
191 void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
192 int SPAdj, unsigned FIOperandNum,
193 RegScavenger *RS) const {
194 MachineFunction *MF = MI->getParent()->getParent();
195 MachineBasicBlock *MBB = MI->getParent();
196 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
197 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
198 const SIInstrInfo *TII =
199 static_cast<const SIInstrInfo *>(MF->getSubtarget().getInstrInfo());
200 DebugLoc DL = MI->getDebugLoc();
202 MachineOperand &FIOp = MI->getOperand(FIOperandNum);
203 int Index = MI->getOperand(FIOperandNum).getIndex();
205 switch (MI->getOpcode()) {
206 // SGPR register spill
207 case AMDGPU::SI_SPILL_S512_SAVE:
208 case AMDGPU::SI_SPILL_S256_SAVE:
209 case AMDGPU::SI_SPILL_S128_SAVE:
210 case AMDGPU::SI_SPILL_S64_SAVE:
211 case AMDGPU::SI_SPILL_S32_SAVE: {
212 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
214 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
215 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
216 &AMDGPU::SGPR_32RegClass, i);
217 struct SIMachineFunctionInfo::SpilledReg Spill =
218 MFI->getSpilledReg(MF, Index, i);
220 if (Spill.VGPR == AMDGPU::NoRegister) {
221 LLVMContext &Ctx = MF->getFunction()->getContext();
222 Ctx.emitError("Ran out of VGPRs for spilling SGPR");
225 BuildMI(*MBB, MI, DL,
226 TII->getMCOpcodeFromPseudo(AMDGPU::V_WRITELANE_B32),
232 MI->eraseFromParent();
236 // SGPR register restore
237 case AMDGPU::SI_SPILL_S512_RESTORE:
238 case AMDGPU::SI_SPILL_S256_RESTORE:
239 case AMDGPU::SI_SPILL_S128_RESTORE:
240 case AMDGPU::SI_SPILL_S64_RESTORE:
241 case AMDGPU::SI_SPILL_S32_RESTORE: {
242 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
244 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
245 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
246 &AMDGPU::SGPR_32RegClass, i);
247 struct SIMachineFunctionInfo::SpilledReg Spill =
248 MFI->getSpilledReg(MF, Index, i);
250 if (Spill.VGPR == AMDGPU::NoRegister) {
251 LLVMContext &Ctx = MF->getFunction()->getContext();
252 Ctx.emitError("Ran out of VGPRs for spilling SGPR");
255 BuildMI(*MBB, MI, DL,
256 TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32),
260 .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
263 // TODO: only do this when it is needed
264 switch (MF->getSubtarget<AMDGPUSubtarget>().getGeneration()) {
265 case AMDGPUSubtarget::SOUTHERN_ISLANDS:
266 // "VALU writes SGPR" -> "SMRD reads that SGPR" needs "S_NOP 3" on SI
267 TII->insertNOPs(MI, 3);
269 case AMDGPUSubtarget::SEA_ISLANDS:
271 default: // VOLCANIC_ISLANDS and later
272 // "VALU writes SGPR -> VMEM reads that SGPR" needs "S_NOP 4" on VI
273 // and later. This also applies to VALUs which write VCC, but we're
274 // unlikely to see VMEM use VCC.
275 TII->insertNOPs(MI, 4);
278 MI->eraseFromParent();
282 // VGPR register spill
283 case AMDGPU::SI_SPILL_V512_SAVE:
284 case AMDGPU::SI_SPILL_V256_SAVE:
285 case AMDGPU::SI_SPILL_V128_SAVE:
286 case AMDGPU::SI_SPILL_V96_SAVE:
287 case AMDGPU::SI_SPILL_V64_SAVE:
288 case AMDGPU::SI_SPILL_V32_SAVE:
289 buildScratchLoadStore(MI, AMDGPU::BUFFER_STORE_DWORD_OFFSET,
290 TII->getNamedOperand(*MI, AMDGPU::OpName::src)->getReg(),
291 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(),
292 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(),
293 FrameInfo->getObjectOffset(Index), RS);
294 MI->eraseFromParent();
296 case AMDGPU::SI_SPILL_V32_RESTORE:
297 case AMDGPU::SI_SPILL_V64_RESTORE:
298 case AMDGPU::SI_SPILL_V96_RESTORE:
299 case AMDGPU::SI_SPILL_V128_RESTORE:
300 case AMDGPU::SI_SPILL_V256_RESTORE:
301 case AMDGPU::SI_SPILL_V512_RESTORE: {
302 buildScratchLoadStore(MI, AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
303 TII->getNamedOperand(*MI, AMDGPU::OpName::dst)->getReg(),
304 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(),
305 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(),
306 FrameInfo->getObjectOffset(Index), RS);
307 MI->eraseFromParent();
312 int64_t Offset = FrameInfo->getObjectOffset(Index);
313 FIOp.ChangeToImmediate(Offset);
314 if (!TII->isImmOperandLegal(MI, FIOperandNum, FIOp)) {
315 unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, SPAdj);
316 BuildMI(*MBB, MI, MI->getDebugLoc(),
317 TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
319 FIOp.ChangeToRegister(TmpReg, false, false, true);
325 unsigned SIRegisterInfo::getHWRegIndex(unsigned Reg) const {
326 return getEncodingValue(Reg) & 0xff;
329 const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
330 assert(!TargetRegisterInfo::isVirtualRegister(Reg));
332 static const TargetRegisterClass *BaseClasses[] = {
333 &AMDGPU::VGPR_32RegClass,
334 &AMDGPU::SReg_32RegClass,
335 &AMDGPU::VReg_64RegClass,
336 &AMDGPU::SReg_64RegClass,
337 &AMDGPU::VReg_96RegClass,
338 &AMDGPU::VReg_128RegClass,
339 &AMDGPU::SReg_128RegClass,
340 &AMDGPU::VReg_256RegClass,
341 &AMDGPU::SReg_256RegClass,
342 &AMDGPU::VReg_512RegClass,
343 &AMDGPU::SReg_512RegClass
346 for (const TargetRegisterClass *BaseClass : BaseClasses) {
347 if (BaseClass->contains(Reg)) {
354 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
355 return getCommonSubClass(&AMDGPU::VGPR_32RegClass, RC) ||
356 getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) ||
357 getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) ||
358 getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) ||
359 getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) ||
360 getCommonSubClass(&AMDGPU::VReg_512RegClass, RC);
363 const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
364 const TargetRegisterClass *SRC) const {
367 } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_32RegClass)) {
368 return &AMDGPU::VGPR_32RegClass;
369 } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_64RegClass)) {
370 return &AMDGPU::VReg_64RegClass;
371 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_128RegClass)) {
372 return &AMDGPU::VReg_128RegClass;
373 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_256RegClass)) {
374 return &AMDGPU::VReg_256RegClass;
375 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_512RegClass)) {
376 return &AMDGPU::VReg_512RegClass;
381 const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
382 const TargetRegisterClass *RC, unsigned SubIdx) const {
383 if (SubIdx == AMDGPU::NoSubRegister)
386 // If this register has a sub-register, we can safely assume it is a 32-bit
387 // register, because all of SI's sub-registers are 32-bit.
388 if (isSGPRClass(RC)) {
389 return &AMDGPU::SGPR_32RegClass;
391 return &AMDGPU::VGPR_32RegClass;
395 unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
396 const TargetRegisterClass *SubRC,
397 unsigned Channel) const {
402 case 0: return AMDGPU::VCC_LO;
403 case 1: return AMDGPU::VCC_HI;
404 default: llvm_unreachable("Invalid SubIdx for VCC");
407 case AMDGPU::FLAT_SCR:
410 return AMDGPU::FLAT_SCR_LO;
412 return AMDGPU::FLAT_SCR_HI;
414 llvm_unreachable("Invalid SubIdx for FLAT_SCR");
421 return AMDGPU::EXEC_LO;
423 return AMDGPU::EXEC_HI;
425 llvm_unreachable("Invalid SubIdx for EXEC");
430 const TargetRegisterClass *RC = getPhysRegClass(Reg);
431 // 32-bit registers don't have sub-registers, so we can just return the
432 // Reg. We need to have this check here, because the calculation below
433 // using getHWRegIndex() will fail with special 32-bit registers like
434 // VCC_LO, VCC_HI, EXEC_LO, EXEC_HI and M0.
435 if (RC->getSize() == 4) {
436 assert(Channel == 0);
440 unsigned Index = getHWRegIndex(Reg);
441 return SubRC->getRegister(Index + Channel);
444 bool SIRegisterInfo::opCanUseLiteralConstant(unsigned OpType) const {
445 return OpType == AMDGPU::OPERAND_REG_IMM32;
448 bool SIRegisterInfo::opCanUseInlineConstant(unsigned OpType) const {
449 if (opCanUseLiteralConstant(OpType))
452 return OpType == AMDGPU::OPERAND_REG_INLINE_C;
455 unsigned SIRegisterInfo::getPreloadedValue(const MachineFunction &MF,
456 enum PreloadedValue Value) const {
458 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
460 case SIRegisterInfo::TGID_X:
461 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 0);
462 case SIRegisterInfo::TGID_Y:
463 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 1);
464 case SIRegisterInfo::TGID_Z:
465 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 2);
466 case SIRegisterInfo::SCRATCH_WAVE_OFFSET:
467 if (MFI->getShaderType() != ShaderType::COMPUTE)
468 return MFI->ScratchOffsetReg;
469 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 4);
470 case SIRegisterInfo::SCRATCH_PTR:
471 return AMDGPU::SGPR2_SGPR3;
472 case SIRegisterInfo::INPUT_PTR:
473 return AMDGPU::SGPR0_SGPR1;
474 case SIRegisterInfo::TIDIG_X:
475 return AMDGPU::VGPR0;
476 case SIRegisterInfo::TIDIG_Y:
477 return AMDGPU::VGPR1;
478 case SIRegisterInfo::TIDIG_Z:
479 return AMDGPU::VGPR2;
481 llvm_unreachable("unexpected preloaded value type");
484 /// \brief Returns a register that is not used at any point in the function.
485 /// If all registers are used, then this function will return
486 // AMDGPU::NoRegister.
487 unsigned SIRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI,
488 const TargetRegisterClass *RC) const {
489 for (unsigned Reg : *RC)
490 if (!MRI.isPhysRegUsed(Reg))
492 return AMDGPU::NoRegister;
495 unsigned SIRegisterInfo::getNumVGPRsAllowed(unsigned WaveCount) const {
510 unsigned SIRegisterInfo::getNumSGPRsAllowed(AMDGPUSubtarget::Generation gen,
511 unsigned WaveCount) const {
512 if (gen >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {