1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIRegisterInfo
13 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_R600_SIREGISTERINFO_H
17 #define LLVM_LIB_TARGET_R600_SIREGISTERINFO_H
19 #include "AMDGPURegisterInfo.h"
20 #include "AMDGPUSubtarget.h"
21 #include "llvm/Support/Debug.h"
25 struct SIRegisterInfo : public AMDGPURegisterInfo {
27 void reserveRegisterTuples(BitVector &, unsigned Reg) const;
32 BitVector getReservedRegs(const MachineFunction &MF) const override;
34 unsigned getRegPressureSetLimit(const MachineFunction &MF,
35 unsigned Idx) const override;
37 bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
39 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
40 unsigned FIOperandNum,
41 RegScavenger *RS) const override;
43 unsigned getHWRegIndex(unsigned Reg) const override;
45 /// \brief Return the 'base' register class for this register.
46 /// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
47 const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
49 /// \returns true if this class contains only SGPR registers
50 bool isSGPRClass(const TargetRegisterClass *RC) const {
54 /// \returns true if this class ID contains only SGPR registers
55 bool isSGPRClassID(unsigned RCID) const {
56 return isSGPRClass(getRegClass(RCID));
59 /// \returns true if this class contains VGPR registers.
60 bool hasVGPRs(const TargetRegisterClass *RC) const;
62 /// \returns A VGPR reg class with the same width as \p SRC
63 const TargetRegisterClass *getEquivalentVGPRClass(
64 const TargetRegisterClass *SRC) const;
66 /// \returns The register class that is used for a sub-register of \p RC for
67 /// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
69 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
70 unsigned SubIdx) const;
72 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
74 const TargetRegisterClass *SrcRC,
75 unsigned SrcSubReg) const override;
77 /// \p Channel This is the register channel (e.g. a value from 0-16), not the
79 /// \returns The sub-register of Reg that is in Channel.
80 unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC,
81 unsigned Channel) const;
83 /// \returns True if operands defined with this operand type can accept
84 /// a literal constant (i.e. any 32-bit immediate).
85 bool opCanUseLiteralConstant(unsigned OpType) const;
87 /// \returns True if operands defined with this operand type can accept
88 /// an inline constant. i.e. An integer value in the range (-16, 64) or
89 /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.
90 bool opCanUseInlineConstant(unsigned OpType) const;
99 SCRATCH_WAVE_OFFSET = 14,
101 FIRST_VGPR_VALUE = 15,
102 TIDIG_X = FIRST_VGPR_VALUE,
107 /// \brief Returns the physical register that \p Value is stored in.
108 unsigned getPreloadedValue(const MachineFunction &MF,
109 enum PreloadedValue Value) const;
111 /// \brief Give the maximum number of VGPRs that can be used by \p WaveCount
112 /// concurrent waves.
113 unsigned getNumVGPRsAllowed(unsigned WaveCount) const;
115 /// \brief Give the maximum number of SGPRs that can be used by \p WaveCount
116 /// concurrent waves.
117 unsigned getNumSGPRsAllowed(AMDGPUSubtarget::Generation gen,
118 unsigned WaveCount) const;
120 unsigned findUnusedRegister(const MachineRegisterInfo &MRI,
121 const TargetRegisterClass *RC) const;
124 void buildScratchLoadStore(MachineBasicBlock::iterator MI,
125 unsigned LoadStoreOp, unsigned Value,
126 unsigned ScratchRsrcReg, unsigned ScratchOffset,
127 int64_t Offset, RegScavenger *RS) const;
130 } // End namespace llvm