1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIRegisterInfo
13 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_R600_SIREGISTERINFO_H
17 #define LLVM_LIB_TARGET_R600_SIREGISTERINFO_H
19 #include "AMDGPURegisterInfo.h"
20 #include "AMDGPUSubtarget.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Support/Debug.h"
26 struct SIRegisterInfo : public AMDGPURegisterInfo {
31 void reserveRegisterTuples(BitVector &, unsigned Reg) const;
36 /// Return the end register initially reserved for the scratch buffer in case
37 /// spilling is needed.
38 unsigned reservedPrivateSegmentBufferReg(const MachineFunction &MF) const;
40 /// Return the end register initially reserved for the scratch wave offset in
41 /// case spilling is needed.
42 unsigned reservedPrivateSegmentWaveByteOffsetReg(
43 const MachineFunction &MF) const;
45 BitVector getReservedRegs(const MachineFunction &MF) const override;
47 unsigned getRegPressureSetLimit(const MachineFunction &MF,
48 unsigned Idx) const override;
50 bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
52 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
53 unsigned FIOperandNum,
54 RegScavenger *RS) const override;
56 unsigned getHWRegIndex(unsigned Reg) const override;
58 /// \brief Return the 'base' register class for this register.
59 /// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
60 const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
62 /// \returns true if this class contains only SGPR registers
63 bool isSGPRClass(const TargetRegisterClass *RC) const {
67 /// \returns true if this class ID contains only SGPR registers
68 bool isSGPRClassID(unsigned RCID) const {
69 return isSGPRClass(getRegClass(RCID));
72 bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const {
73 if (TargetRegisterInfo::isVirtualRegister(Reg))
74 return isSGPRClass(MRI.getRegClass(Reg));
75 return getPhysRegClass(Reg);
78 /// \returns true if this class contains VGPR registers.
79 bool hasVGPRs(const TargetRegisterClass *RC) const;
81 /// returns true if this is a pseudoregister class combination of VGPRs and
82 /// SGPRs for operand modeling. FIXME: We should set isAllocatable = 0 on
84 static bool isPseudoRegClass(const TargetRegisterClass *RC) {
85 return RC == &AMDGPU::VS_32RegClass || RC == &AMDGPU::VS_64RegClass;
88 /// \returns A VGPR reg class with the same width as \p SRC
89 const TargetRegisterClass *getEquivalentVGPRClass(
90 const TargetRegisterClass *SRC) const;
92 /// \returns The register class that is used for a sub-register of \p RC for
93 /// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
95 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
96 unsigned SubIdx) const;
98 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
100 const TargetRegisterClass *SrcRC,
101 unsigned SrcSubReg) const override;
103 /// \p Channel This is the register channel (e.g. a value from 0-16), not the
105 /// \returns The sub-register of Reg that is in Channel.
106 unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC,
107 unsigned Channel) const;
109 /// \returns True if operands defined with this operand type can accept
110 /// a literal constant (i.e. any 32-bit immediate).
111 bool opCanUseLiteralConstant(unsigned OpType) const;
113 /// \returns True if operands defined with this operand type can accept
114 /// an inline constant. i.e. An integer value in the range (-16, 64) or
115 /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.
116 bool opCanUseInlineConstant(unsigned OpType) const;
118 enum PreloadedValue {
120 PRIVATE_SEGMENT_BUFFER = 0,
123 KERNARG_SEGMENT_PTR = 3,
127 PRIVATE_SEGMENT_WAVE_BYTE_OFFSET = 14,
130 FIRST_VGPR_VALUE = 15,
131 WORKITEM_ID_X = FIRST_VGPR_VALUE,
136 /// \brief Returns the physical register that \p Value is stored in.
137 unsigned getPreloadedValue(const MachineFunction &MF,
138 enum PreloadedValue Value) const;
140 /// \brief Give the maximum number of VGPRs that can be used by \p WaveCount
141 /// concurrent waves.
142 unsigned getNumVGPRsAllowed(unsigned WaveCount) const;
144 /// \brief Give the maximum number of SGPRs that can be used by \p WaveCount
145 /// concurrent waves.
146 unsigned getNumSGPRsAllowed(AMDGPUSubtarget::Generation gen,
147 unsigned WaveCount) const;
149 unsigned findUnusedRegister(const MachineRegisterInfo &MRI,
150 const TargetRegisterClass *RC) const;
152 unsigned getSGPR32PressureSet() const { return SGPR32SetID; };
153 unsigned getVGPR32PressureSet() const { return VGPR32SetID; };
156 void buildScratchLoadStore(MachineBasicBlock::iterator MI,
157 unsigned LoadStoreOp, unsigned Value,
158 unsigned ScratchRsrcReg, unsigned ScratchOffset,
159 int64_t Offset, RegScavenger *RS) const;
162 } // End namespace llvm