1 //===-- SIRegisterInfo.td - SI Register defs ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the SI registers
12 //===----------------------------------------------------------------------===//
13 class SIReg <string n, bits<16> regIdx = 0> : Register<n>,
14 DwarfRegNum<[!cast<int>(HWEncoding)]> {
15 let Namespace = "AMDGPU";
17 // This is the not yet the complete register encoding. An additional
18 // bit is set for VGPRs.
19 let HWEncoding = regIdx;
23 def VCC_LO : SIReg<"vcc_lo", 106>;
24 def VCC_HI : SIReg<"vcc_hi", 107>;
26 // VCC for 64-bit instructions
27 def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]>,
28 DwarfRegAlias<VCC_LO> {
29 let Namespace = "AMDGPU";
30 let SubRegIndices = [sub0, sub1];
34 def EXEC_LO : SIReg<"exec_lo", 126>;
35 def EXEC_HI : SIReg<"exec_hi", 127>;
37 def EXEC : RegisterWithSubRegs<"EXEC", [EXEC_LO, EXEC_HI]>,
38 DwarfRegAlias<EXEC_LO> {
39 let Namespace = "AMDGPU";
40 let SubRegIndices = [sub0, sub1];
44 def SCC : SIReg<"scc", 253>;
45 def M0 : SIReg <"m0", 124>;
47 def FLAT_SCR_LO : SIReg<"flat_scr_lo", 104>; // Offset in units of 256-bytes.
48 def FLAT_SCR_HI : SIReg<"flat_scr_hi", 105>; // Size is the per-thread scratch size, in bytes.
50 // Pair to indicate location of scratch space for flat accesses.
51 def FLAT_SCR : RegisterWithSubRegs <"flat_scr", [FLAT_SCR_LO, FLAT_SCR_HI]>,
52 DwarfRegAlias<FLAT_SCR_LO> {
53 let Namespace = "AMDGPU";
54 let SubRegIndices = [sub0, sub1];
59 foreach Index = 0-101 in {
60 def SGPR#Index : SIReg <"SGPR"#Index, Index>;
64 foreach Index = 0-255 in {
65 def VGPR#Index : SIReg <"VGPR"#Index, Index> {
66 let HWEncoding{8} = 1;
70 //===----------------------------------------------------------------------===//
71 // Groupings using register classes and tuples
72 //===----------------------------------------------------------------------===//
74 // TODO: Do we need to set DwarfRegAlias on register tuples?
76 // SGPR 32-bit registers
77 def SGPR_32 : RegisterClass<"AMDGPU", [i32, f32], 32,
78 (add (sequence "SGPR%u", 0, 101))>;
80 // SGPR 64-bit registers
81 def SGPR_64Regs : RegisterTuples<[sub0, sub1],
82 [(add (decimate (trunc SGPR_32, 101), 2)),
83 (add (decimate (shl SGPR_32, 1), 2))]>;
85 // SGPR 128-bit registers
86 def SGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
87 [(add (decimate (trunc SGPR_32, 99), 4)),
88 (add (decimate (shl SGPR_32, 1), 4)),
89 (add (decimate (shl SGPR_32, 2), 4)),
90 (add (decimate (shl SGPR_32, 3), 4))]>;
92 // SGPR 256-bit registers
93 def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
94 [(add (decimate (trunc SGPR_32, 95), 4)),
95 (add (decimate (shl SGPR_32, 1), 4)),
96 (add (decimate (shl SGPR_32, 2), 4)),
97 (add (decimate (shl SGPR_32, 3), 4)),
98 (add (decimate (shl SGPR_32, 4), 4)),
99 (add (decimate (shl SGPR_32, 5), 4)),
100 (add (decimate (shl SGPR_32, 6), 4)),
101 (add (decimate (shl SGPR_32, 7), 4))]>;
103 // SGPR 512-bit registers
104 def SGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
105 sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15],
106 [(add (decimate (trunc SGPR_32, 87), 4)),
107 (add (decimate (shl SGPR_32, 1), 4)),
108 (add (decimate (shl SGPR_32, 2), 4)),
109 (add (decimate (shl SGPR_32, 3), 4)),
110 (add (decimate (shl SGPR_32, 4), 4)),
111 (add (decimate (shl SGPR_32, 5), 4)),
112 (add (decimate (shl SGPR_32, 6), 4)),
113 (add (decimate (shl SGPR_32, 7), 4)),
114 (add (decimate (shl SGPR_32, 8), 4)),
115 (add (decimate (shl SGPR_32, 9), 4)),
116 (add (decimate (shl SGPR_32, 10), 4)),
117 (add (decimate (shl SGPR_32, 11), 4)),
118 (add (decimate (shl SGPR_32, 12), 4)),
119 (add (decimate (shl SGPR_32, 13), 4)),
120 (add (decimate (shl SGPR_32, 14), 4)),
121 (add (decimate (shl SGPR_32, 15), 4))]>;
123 // VGPR 32-bit registers
124 def VGPR_32 : RegisterClass<"AMDGPU", [i32, f32], 32,
125 (add (sequence "VGPR%u", 0, 255))>;
127 // VGPR 64-bit registers
128 def VGPR_64 : RegisterTuples<[sub0, sub1],
129 [(add (trunc VGPR_32, 255)),
130 (add (shl VGPR_32, 1))]>;
132 // VGPR 96-bit registers
133 def VGPR_96 : RegisterTuples<[sub0, sub1, sub2],
134 [(add (trunc VGPR_32, 254)),
135 (add (shl VGPR_32, 1)),
136 (add (shl VGPR_32, 2))]>;
138 // VGPR 128-bit registers
139 def VGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
140 [(add (trunc VGPR_32, 253)),
141 (add (shl VGPR_32, 1)),
142 (add (shl VGPR_32, 2)),
143 (add (shl VGPR_32, 3))]>;
145 // VGPR 256-bit registers
146 def VGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
147 [(add (trunc VGPR_32, 249)),
148 (add (shl VGPR_32, 1)),
149 (add (shl VGPR_32, 2)),
150 (add (shl VGPR_32, 3)),
151 (add (shl VGPR_32, 4)),
152 (add (shl VGPR_32, 5)),
153 (add (shl VGPR_32, 6)),
154 (add (shl VGPR_32, 7))]>;
156 // VGPR 512-bit registers
157 def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
158 sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15],
159 [(add (trunc VGPR_32, 241)),
160 (add (shl VGPR_32, 1)),
161 (add (shl VGPR_32, 2)),
162 (add (shl VGPR_32, 3)),
163 (add (shl VGPR_32, 4)),
164 (add (shl VGPR_32, 5)),
165 (add (shl VGPR_32, 6)),
166 (add (shl VGPR_32, 7)),
167 (add (shl VGPR_32, 8)),
168 (add (shl VGPR_32, 9)),
169 (add (shl VGPR_32, 10)),
170 (add (shl VGPR_32, 11)),
171 (add (shl VGPR_32, 12)),
172 (add (shl VGPR_32, 13)),
173 (add (shl VGPR_32, 14)),
174 (add (shl VGPR_32, 15))]>;
176 //===----------------------------------------------------------------------===//
177 // Register classes used as source and destination
178 //===----------------------------------------------------------------------===//
180 class RegImmMatcher<string name> : AsmOperandClass {
182 let RenderMethod = "addRegOrImmOperands";
185 // Register class for all scalar registers (SGPRs + Special Registers)
186 def SReg_32 : RegisterClass<"AMDGPU", [i32, f32], 32,
187 (add SGPR_32, M0, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI)
190 def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 64, (add SGPR_64Regs)>;
192 def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 64,
193 (add SGPR_64, VCC, EXEC, FLAT_SCR)
196 def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8], 128, (add SGPR_128)>;
198 def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add SGPR_256)>;
200 def SReg_512 : RegisterClass<"AMDGPU", [v64i8, v16i32], 512, (add SGPR_512)>;
202 // Register class for all vector registers (VGPRs + Interploation Registers)
203 def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32], 64, (add VGPR_64)>;
205 def VReg_96 : RegisterClass<"AMDGPU", [untyped], 96, (add VGPR_96)> {
209 def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32], 128, (add VGPR_128)>;
211 def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add VGPR_256)>;
213 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>;
215 def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> {
219 class RegImmOperand <RegisterClass rc> : RegisterOperand<rc> {
220 let OperandNamespace = "AMDGPU";
221 let OperandType = "OPERAND_REG_IMM32";
224 class RegInlineOperand <RegisterClass rc> : RegisterOperand<rc> {
225 let OperandNamespace = "AMDGPU";
226 let OperandType = "OPERAND_REG_INLINE_C";
229 //===----------------------------------------------------------------------===//
230 // SSrc_* Operands with an SGPR or a 32-bit immediate
231 //===----------------------------------------------------------------------===//
233 def SSrc_32 : RegImmOperand<SReg_32> {
234 let ParserMatchClass = RegImmMatcher<"SSrc32">;
237 def SSrc_64 : RegImmOperand<SReg_64> {
238 let ParserMatchClass = RegImmMatcher<"SSrc64">;
241 //===----------------------------------------------------------------------===//
242 // SCSrc_* Operands with an SGPR or a inline constant
243 //===----------------------------------------------------------------------===//
245 def SCSrc_32 : RegInlineOperand<SReg_32> {
246 let ParserMatchClass = RegImmMatcher<"SCSrc32">;
249 //===----------------------------------------------------------------------===//
250 // VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate
251 //===----------------------------------------------------------------------===//
253 def VS_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VGPR_32, SReg_32)>;
255 def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 64, (add VReg_64, SReg_64)>;
257 def VSrc_32 : RegisterOperand<VS_32> {
258 let OperandNamespace = "AMDGPU";
259 let OperandType = "OPERAND_REG_IMM32";
260 let ParserMatchClass = RegImmMatcher<"VSrc32">;
263 def VSrc_64 : RegisterOperand<VS_64> {
264 let OperandNamespace = "AMDGPU";
265 let OperandType = "OPERAND_REG_IMM32";
266 let ParserMatchClass = RegImmMatcher<"VSrc64">;
269 //===----------------------------------------------------------------------===//
270 // VCSrc_* Operands with an SGPR, VGPR or an inline constant
271 //===----------------------------------------------------------------------===//
273 def VCSrc_32 : RegisterOperand<VS_32> {
274 let OperandNamespace = "AMDGPU";
275 let OperandType = "OPERAND_REG_INLINE_C";
276 let ParserMatchClass = RegImmMatcher<"VCSrc32">;
279 def VCSrc_64 : RegisterOperand<VS_64> {
280 let OperandNamespace = "AMDGPU";
281 let OperandType = "OPERAND_REG_INLINE_C";
282 let ParserMatchClass = RegImmMatcher<"VCSrc64">;
285 //===----------------------------------------------------------------------===//
286 // SCSrc_* Operands with an SGPR or an inline constant
287 //===----------------------------------------------------------------------===//
289 def SCSrc_64 : RegisterOperand<SReg_64> {
290 let OperandNamespace = "AMDGPU";
291 let OperandType = "OPERAND_REG_INLINE_C";
292 let ParserMatchClass = RegImmMatcher<"SCSrc64">;