1 //===-- SISchedule.td - SI Scheduling definitons -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // MachineModel definitions for Southern Islands (SI)
12 //===----------------------------------------------------------------------===//
14 def WriteBranch : SchedWrite;
15 def WriteExport : SchedWrite;
16 def WriteLDS : SchedWrite;
17 def WriteSALU : SchedWrite;
18 def WriteSMEM : SchedWrite;
19 def WriteVMEM : SchedWrite;
20 def WriteBarrier : SchedWrite;
22 // Vector ALU instructions
23 def Write32Bit : SchedWrite;
24 def WriteQuarterRate32 : SchedWrite;
26 def WriteFloatFMA : SchedWrite;
28 def WriteDouble : SchedWrite;
29 def WriteDoubleAdd : SchedWrite;
31 def SIFullSpeedModel : SchedMachineModel;
32 def SIQuarterSpeedModel : SchedMachineModel;
34 // BufferSize = 0 means the processors are in-order.
35 let BufferSize = 0 in {
37 // XXX: Are the resource counts correct?
38 def HWBranch : ProcResource<1>;
39 def HWExport : ProcResource<7>; // Taken from S_WAITCNT
40 def HWLGKM : ProcResource<31>; // Taken from S_WAITCNT
41 def HWSALU : ProcResource<1>;
42 def HWVMEM : ProcResource<15>; // Taken from S_WAITCNT
43 def HWVALU : ProcResource<1>;
47 class HWWriteRes<SchedWrite write, list<ProcResourceKind> resources,
48 int latency> : WriteRes<write, resources> {
49 let Latency = latency;
52 class HWVALUWriteRes<SchedWrite write, int latency> :
53 HWWriteRes<write, [HWVALU], latency>;
56 // The latency numbers are taken from AMD Accelerated Parallel Processing
57 // guide. They may not be acurate.
59 // The latency values are 1 / (operations / cycle) / 4.
60 multiclass SICommonWriteRes {
62 def : HWWriteRes<WriteBranch, [HWBranch], 100>; // XXX: Guessed ???
63 def : HWWriteRes<WriteExport, [HWExport], 100>; // XXX: Guessed ???
64 def : HWWriteRes<WriteLDS, [HWLGKM], 32>; // 2 - 64
65 def : HWWriteRes<WriteSALU, [HWSALU], 1>;
66 def : HWWriteRes<WriteSMEM, [HWLGKM], 10>; // XXX: Guessed ???
67 def : HWWriteRes<WriteVMEM, [HWVMEM], 450>; // 300 - 600
68 def : HWWriteRes<WriteBarrier, [HWBranch], 500>; // XXX: Guessed ???
70 def : HWVALUWriteRes<Write32Bit, 1>;
71 def : HWVALUWriteRes<WriteQuarterRate32, 4>;
75 let SchedModel = SIFullSpeedModel in {
77 defm : SICommonWriteRes;
79 def : HWVALUWriteRes<WriteFloatFMA, 1>;
80 def : HWVALUWriteRes<WriteDouble, 4>;
81 def : HWVALUWriteRes<WriteDoubleAdd, 2>;
83 } // End SchedModel = SIFullSpeedModel
85 let SchedModel = SIQuarterSpeedModel in {
87 defm : SICommonWriteRes;
89 def : HWVALUWriteRes<WriteFloatFMA, 16>;
90 def : HWVALUWriteRes<WriteDouble, 16>;
91 def : HWVALUWriteRes<WriteDoubleAdd, 8>;
93 } // End SchedModel = SIQuarterSpeedModel