1 //=== A15SDOptimizerPass.cpp - Optimize DPR and SPR register accesses on A15==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // The Cortex-A15 processor employs a tracking scheme in its register renaming
11 // in order to process each instruction's micro-ops speculatively and
12 // out-of-order with appropriate forwarding. The ARM architecture allows VFP
13 // instructions to read and write 32-bit S-registers. Each S-register
14 // corresponds to one half (upper or lower) of an overlaid 64-bit D-register.
16 // There are several instruction patterns which can be used to provide this
17 // capability which can provide higher performance than other, potentially more
18 // direct patterns, specifically around when one micro-op reads a D-register
19 // operand that has recently been written as one or more S-register results.
21 // This file defines a pre-regalloc pass which looks for SPR producers which
22 // are going to be used by a DPR (or QPR) consumers and creates the more
23 // optimized access pattern.
25 //===----------------------------------------------------------------------===//
27 #define DEBUG_TYPE "a15-sd-optimizer"
29 #include "ARMBaseInstrInfo.h"
30 #include "ARMISelLowering.h"
31 #include "ARMSubtarget.h"
32 #include "ARMTargetMachine.h"
33 #include "llvm/ADT/SmallPtrSet.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/CodeGen/MachineFunctionPass.h"
36 #include "llvm/CodeGen/MachineInstr.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/Target/TargetRegisterInfo.h"
48 struct A15SDOptimizer : public MachineFunctionPass {
50 A15SDOptimizer() : MachineFunctionPass(ID) {}
52 virtual bool runOnMachineFunction(MachineFunction &Fn);
54 virtual const char *getPassName() const {
55 return "ARM A15 S->D optimizer";
59 const ARMBaseInstrInfo *TII;
60 const TargetRegisterInfo *TRI;
61 MachineRegisterInfo *MRI;
63 bool runOnInstruction(MachineInstr *MI);
66 // Instruction builder helpers
68 unsigned createDupLane(MachineBasicBlock &MBB,
69 MachineBasicBlock::iterator InsertBefore,
71 unsigned Reg, unsigned Lane,
74 unsigned createExtractSubreg(MachineBasicBlock &MBB,
75 MachineBasicBlock::iterator InsertBefore,
77 unsigned DReg, unsigned Lane,
78 const TargetRegisterClass *TRC);
80 unsigned createVExt(MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator InsertBefore,
83 unsigned Ssub0, unsigned Ssub1);
85 unsigned createRegSequence(MachineBasicBlock &MBB,
86 MachineBasicBlock::iterator InsertBefore,
88 unsigned Reg1, unsigned Reg2);
90 unsigned createInsertSubreg(MachineBasicBlock &MBB,
91 MachineBasicBlock::iterator InsertBefore,
92 DebugLoc DL, unsigned DReg, unsigned Lane,
95 unsigned createImplicitDef(MachineBasicBlock &MBB,
96 MachineBasicBlock::iterator InsertBefore,
100 // Various property checkers
102 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
103 bool hasPartialWrite(MachineInstr *MI);
104 SmallVector<unsigned, 8> getReadDPRs(MachineInstr *MI);
105 unsigned getDPRLaneFromSPR(unsigned SReg);
108 // Methods used for getting the definitions of partial registers
111 MachineInstr *elideCopies(MachineInstr *MI);
112 void elideCopiesAndPHIs(MachineInstr *MI,
113 SmallVectorImpl<MachineInstr*> &Outs);
116 // Pattern optimization methods
118 unsigned optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg);
119 unsigned optimizeSDPattern(MachineInstr *MI);
120 unsigned getPrefSPRLane(unsigned SReg);
123 // Sanitizing method - used to make sure if don't leave dead code around.
125 void eraseInstrWithNoUses(MachineInstr *MI);
128 // A map used to track the changes done by this pass.
130 std::map<MachineInstr*, unsigned> Replacements;
131 std::set<MachineInstr *> DeadInstr;
133 char A15SDOptimizer::ID = 0;
134 } // end anonymous namespace
136 // Returns true if this is a use of a SPR register.
137 bool A15SDOptimizer::usesRegClass(MachineOperand &MO,
138 const TargetRegisterClass *TRC) {
141 unsigned Reg = MO.getReg();
143 if (TargetRegisterInfo::isVirtualRegister(Reg))
144 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
146 return TRC->contains(Reg);
149 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) {
150 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
152 if (DReg != ARM::NoRegister) return ARM::ssub_1;
156 // Get the subreg type that is most likely to be coalesced
157 // for an SPR register that will be used in VDUP32d pseudo.
158 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) {
159 if (!TRI->isVirtualRegister(SReg))
160 return getDPRLaneFromSPR(SReg);
162 MachineInstr *MI = MRI->getVRegDef(SReg);
163 if (!MI) return ARM::ssub_0;
164 MachineOperand *MO = MI->findRegisterDefOperand(SReg);
166 assert(MO->isReg() && "Non-register operand found!");
167 if (!MO) return ARM::ssub_0;
169 if (MI->isCopy() && usesRegClass(MI->getOperand(1),
170 &ARM::SPRRegClass)) {
171 SReg = MI->getOperand(1).getReg();
174 if (TargetRegisterInfo::isVirtualRegister(SReg)) {
175 if (MO->getSubReg() == ARM::ssub_1) return ARM::ssub_1;
178 return getDPRLaneFromSPR(SReg);
181 // MI is known to be dead. Figure out what instructions
182 // are also made dead by this and mark them for removal.
183 void A15SDOptimizer::eraseInstrWithNoUses(MachineInstr *MI) {
184 SmallVector<MachineInstr *, 8> Front;
185 DeadInstr.insert(MI);
187 DEBUG(dbgs() << "Deleting base instruction " << *MI << "\n");
190 while (Front.size() != 0) {
194 // MI is already known to be dead. We need to see
195 // if other instructions can also be removed.
196 for (unsigned int i = 0; i < MI->getNumOperands(); ++i) {
197 MachineOperand &MO = MI->getOperand(i);
198 if ((!MO.isReg()) || (!MO.isUse()))
200 unsigned Reg = MO.getReg();
201 if (!TRI->isVirtualRegister(Reg))
203 MachineOperand *Op = MI->findRegisterDefOperand(Reg);
208 MachineInstr *Def = Op->getParent();
210 // We don't need to do anything if we have already marked
211 // this instruction as being dead.
212 if (DeadInstr.find(Def) != DeadInstr.end())
215 // Check if all the uses of this instruction are marked as
216 // dead. If so, we can also mark this instruction as being
219 for (unsigned int j = 0; j < Def->getNumOperands(); ++j) {
220 MachineOperand &MODef = Def->getOperand(j);
221 if ((!MODef.isReg()) || (!MODef.isDef()))
223 unsigned DefReg = MODef.getReg();
224 if (!TRI->isVirtualRegister(DefReg)) {
228 for (MachineRegisterInfo::use_iterator II = MRI->use_begin(Reg),
231 // We don't care about self references.
234 if (DeadInstr.find(&*II) == DeadInstr.end()) {
241 if (!IsDead) continue;
243 DEBUG(dbgs() << "Deleting instruction " << *Def << "\n");
244 DeadInstr.insert(Def);
249 // Creates the more optimized patterns and generally does all the code
250 // transformations in this pass.
251 unsigned A15SDOptimizer::optimizeSDPattern(MachineInstr *MI) {
253 return optimizeAllLanesPattern(MI, MI->getOperand(1).getReg());
256 if (MI->isInsertSubreg()) {
257 unsigned DPRReg = MI->getOperand(1).getReg();
258 unsigned SPRReg = MI->getOperand(2).getReg();
260 if (TRI->isVirtualRegister(DPRReg) && TRI->isVirtualRegister(SPRReg)) {
261 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg());
262 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg());
264 if (DPRMI && SPRMI) {
265 // See if the first operand of this insert_subreg is IMPLICIT_DEF
266 MachineInstr *ECDef = elideCopies(DPRMI);
267 if (ECDef != 0 && ECDef->isImplicitDef()) {
268 // Another corner case - if we're inserting something that is purely
269 // a subreg copy of a DPR, just use that DPR.
271 MachineInstr *EC = elideCopies(SPRMI);
272 // Is it a subreg copy of ssub_0?
273 if (EC && EC->isCopy() &&
274 EC->getOperand(1).getSubReg() == ARM::ssub_0) {
275 DEBUG(dbgs() << "Found a subreg copy: " << *SPRMI);
277 // Find the thing we're subreg copying out of - is it of the same
278 // regclass as DPRMI? (i.e. a DPR or QPR).
279 unsigned FullReg = SPRMI->getOperand(1).getReg();
280 const TargetRegisterClass *TRC =
281 MRI->getRegClass(MI->getOperand(1).getReg());
282 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) {
283 DEBUG(dbgs() << "Subreg copy is compatible - returning ");
284 DEBUG(dbgs() << PrintReg(FullReg) << "\n");
285 eraseInstrWithNoUses(MI);
290 return optimizeAllLanesPattern(MI, MI->getOperand(2).getReg());
294 return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
297 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1),
298 &ARM::SPRRegClass)) {
299 // See if all bar one of the operands are IMPLICIT_DEF and insert the
300 // optimizer pattern accordingly.
301 unsigned NumImplicit = 0, NumTotal = 0;
302 unsigned NonImplicitReg = ~0U;
304 for (unsigned I = 1; I < MI->getNumExplicitOperands(); ++I) {
305 if (!MI->getOperand(I).isReg())
308 unsigned OpReg = MI->getOperand(I).getReg();
310 if (!TRI->isVirtualRegister(OpReg))
313 MachineInstr *Def = MRI->getVRegDef(OpReg);
316 if (Def->isImplicitDef())
319 NonImplicitReg = MI->getOperand(I).getReg();
322 if (NumImplicit == NumTotal - 1)
323 return optimizeAllLanesPattern(MI, NonImplicitReg);
325 return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
328 assert(0 && "Unhandled update pattern!");
332 // Return true if this MachineInstr inserts a scalar (SPR) value into
333 // a D or Q register.
334 bool A15SDOptimizer::hasPartialWrite(MachineInstr *MI) {
335 // The only way we can do a partial register update is through a COPY,
336 // INSERT_SUBREG or REG_SEQUENCE.
337 if (MI->isCopy() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
340 if (MI->isInsertSubreg() && usesRegClass(MI->getOperand(2),
344 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
350 // Looks through full copies to get the instruction that defines the input
352 MachineInstr *A15SDOptimizer::elideCopies(MachineInstr *MI) {
353 if (!MI->isFullCopy())
355 if (!TRI->isVirtualRegister(MI->getOperand(1).getReg()))
357 MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg());
360 return elideCopies(Def);
363 // Look through full copies and PHIs to get the set of non-copy MachineInstrs
364 // that can produce MI.
365 void A15SDOptimizer::elideCopiesAndPHIs(MachineInstr *MI,
366 SmallVectorImpl<MachineInstr*> &Outs) {
367 // Looking through PHIs may create loops so we need to track what
368 // instructions we have visited before.
369 std::set<MachineInstr *> Reached;
370 SmallVector<MachineInstr *, 8> Front;
372 while (Front.size() != 0) {
376 // If we have already explored this MachineInstr, ignore it.
377 if (Reached.find(MI) != Reached.end())
381 for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
382 unsigned Reg = MI->getOperand(I).getReg();
383 if (!TRI->isVirtualRegister(Reg)) {
386 MachineInstr *NewMI = MRI->getVRegDef(Reg);
389 Front.push_back(NewMI);
391 } else if (MI->isFullCopy()) {
392 if (!TRI->isVirtualRegister(MI->getOperand(1).getReg()))
394 MachineInstr *NewMI = MRI->getVRegDef(MI->getOperand(1).getReg());
397 Front.push_back(NewMI);
399 DEBUG(dbgs() << "Found partial copy" << *MI <<"\n");
405 // Return the DPR virtual registers that are read by this machine instruction
407 SmallVector<unsigned, 8> A15SDOptimizer::getReadDPRs(MachineInstr *MI) {
408 if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() ||
410 return SmallVector<unsigned, 8>();
412 SmallVector<unsigned, 8> Defs;
413 for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
414 MachineOperand &MO = MI->getOperand(i);
416 if (!MO.isReg() || !MO.isUse())
418 if (!usesRegClass(MO, &ARM::DPRRegClass) &&
419 !usesRegClass(MO, &ARM::QPRRegClass))
422 Defs.push_back(MO.getReg());
427 // Creates a DPR register from an SPR one by using a VDUP.
429 A15SDOptimizer::createDupLane(MachineBasicBlock &MBB,
430 MachineBasicBlock::iterator InsertBefore,
432 unsigned Reg, unsigned Lane, bool QPR) {
433 unsigned Out = MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass :
435 AddDefaultPred(BuildMI(MBB,
438 TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d),
446 // Creates a SPR register from a DPR by copying the value in lane 0.
448 A15SDOptimizer::createExtractSubreg(MachineBasicBlock &MBB,
449 MachineBasicBlock::iterator InsertBefore,
451 unsigned DReg, unsigned Lane,
452 const TargetRegisterClass *TRC) {
453 unsigned Out = MRI->createVirtualRegister(TRC);
457 TII->get(TargetOpcode::COPY), Out)
458 .addReg(DReg, 0, Lane);
463 // Takes two SPR registers and creates a DPR by using a REG_SEQUENCE.
465 A15SDOptimizer::createRegSequence(MachineBasicBlock &MBB,
466 MachineBasicBlock::iterator InsertBefore,
468 unsigned Reg1, unsigned Reg2) {
469 unsigned Out = MRI->createVirtualRegister(&ARM::QPRRegClass);
473 TII->get(TargetOpcode::REG_SEQUENCE), Out)
477 .addImm(ARM::dsub_1);
481 // Takes two DPR registers that have previously been VDUPed (Ssub0 and Ssub1)
482 // and merges them into one DPR register.
484 A15SDOptimizer::createVExt(MachineBasicBlock &MBB,
485 MachineBasicBlock::iterator InsertBefore,
487 unsigned Ssub0, unsigned Ssub1) {
488 unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
489 AddDefaultPred(BuildMI(MBB,
492 TII->get(ARM::VEXTd32), Out)
500 A15SDOptimizer::createInsertSubreg(MachineBasicBlock &MBB,
501 MachineBasicBlock::iterator InsertBefore,
502 DebugLoc DL, unsigned DReg, unsigned Lane,
504 unsigned Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass);
508 TII->get(TargetOpcode::INSERT_SUBREG), Out)
517 A15SDOptimizer::createImplicitDef(MachineBasicBlock &MBB,
518 MachineBasicBlock::iterator InsertBefore,
520 unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
524 TII->get(TargetOpcode::IMPLICIT_DEF), Out);
528 // This function inserts instructions in order to optimize interactions between
529 // SPR registers and DPR/QPR registers. It does so by performing VDUPs on all
530 // lanes, and the using VEXT instructions to recompose the result.
532 A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg) {
533 MachineBasicBlock::iterator InsertPt(MI);
534 DebugLoc DL = MI->getDebugLoc();
535 MachineBasicBlock &MBB = *MI->getParent();
539 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass)) {
540 unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg,
541 ARM::dsub_0, &ARM::DPRRegClass);
542 unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg,
543 ARM::dsub_1, &ARM::DPRRegClass);
545 unsigned Out1 = createDupLane(MBB, InsertPt, DL, DSub0, 0);
546 unsigned Out2 = createDupLane(MBB, InsertPt, DL, DSub0, 1);
547 Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
549 unsigned Out3 = createDupLane(MBB, InsertPt, DL, DSub1, 0);
550 unsigned Out4 = createDupLane(MBB, InsertPt, DL, DSub1, 1);
551 Out2 = createVExt(MBB, InsertPt, DL, Out3, Out4);
553 Out = createRegSequence(MBB, InsertPt, DL, Out, Out2);
555 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) {
556 unsigned Out1 = createDupLane(MBB, InsertPt, DL, Reg, 0);
557 unsigned Out2 = createDupLane(MBB, InsertPt, DL, Reg, 1);
558 Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
561 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) &&
562 "Found unexpected regclass!");
564 unsigned PrefLane = getPrefSPRLane(Reg);
567 case ARM::ssub_0: Lane = 0; break;
568 case ARM::ssub_1: Lane = 1; break;
569 default: llvm_unreachable("Unknown preferred lane!");
572 bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass);
574 Out = createImplicitDef(MBB, InsertPt, DL);
575 Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);
576 Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);
577 eraseInstrWithNoUses(MI);
582 bool A15SDOptimizer::runOnInstruction(MachineInstr *MI) {
583 // We look for instructions that write S registers that are then read as
584 // D/Q registers. These can only be caused by COPY, INSERT_SUBREG and
585 // REG_SEQUENCE pseudos that insert an SPR value into a DPR register or
586 // merge two SPR values to form a DPR register. In order avoid false
587 // positives we make sure that there is an SPR producer so we look past
588 // COPY and PHI nodes to find it.
590 // The best code pattern for when an SPR producer is going to be used by a
591 // DPR or QPR consumer depends on whether the other lanes of the
592 // corresponding DPR/QPR are currently defined.
594 // We can handle these efficiently, depending on the type of
595 // pseudo-instruction that is producing the pattern
597 // * COPY: * VDUP all lanes and merge the results together
600 // * INSERT_SUBREG: * If the SPR value was originally in another DPR/QPR
601 // lane, and the other lane(s) of the DPR/QPR register
602 // that we are inserting in are undefined, use the
603 // original DPR/QPR value.
604 // * Otherwise, fall back on the same stategy as COPY.
606 // * REG_SEQUENCE: * If all except one of the input operands are
607 // IMPLICIT_DEFs, insert the VDUP pattern for just the
608 // defined input operand
609 // * Otherwise, fall back on the same stategy as COPY.
612 // First, get all the reads of D-registers done by this instruction.
613 SmallVector<unsigned, 8> Defs = getReadDPRs(MI);
614 bool Modified = false;
616 for (SmallVectorImpl<unsigned>::iterator I = Defs.begin(), E = Defs.end();
618 // Follow the def-use chain for this DPR through COPYs, and also through
619 // PHIs (which are essentially multi-way COPYs). It is because of PHIs that
620 // we can end up with multiple defs of this DPR.
622 SmallVector<MachineInstr *, 8> DefSrcs;
623 if (!TRI->isVirtualRegister(*I))
625 MachineInstr *Def = MRI->getVRegDef(*I);
629 elideCopiesAndPHIs(Def, DefSrcs);
631 for (SmallVectorImpl<MachineInstr *>::iterator II = DefSrcs.begin(),
632 EE = DefSrcs.end(); II != EE; ++II) {
633 MachineInstr *MI = *II;
635 // If we've already analyzed and replaced this operand, don't do
637 if (Replacements.find(MI) != Replacements.end())
640 // Now, work out if the instruction causes a SPR->DPR dependency.
641 if (!hasPartialWrite(MI))
644 // Collect all the uses of this MI's DPR def for updating later.
645 SmallVector<MachineOperand*, 8> Uses;
646 unsigned DPRDefReg = MI->getOperand(0).getReg();
647 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DPRDefReg),
648 E = MRI->use_end(); I != E; ++I)
649 Uses.push_back(&I.getOperand());
651 // We can optimize this.
652 unsigned NewReg = optimizeSDPattern(MI);
656 for (SmallVectorImpl<MachineOperand *>::const_iterator I = Uses.begin(),
657 E = Uses.end(); I != E; ++I) {
658 // Make sure to constrain the register class of the new register to
659 // match what we're replacing. Otherwise we can optimize a DPR_VFP2
660 // reference into a plain DPR, and that will end poorly. NewReg is
661 // always virtual here, so there will always be a matching subclass
663 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
665 DEBUG(dbgs() << "Replacing operand "
667 << PrintReg(NewReg) << "\n");
668 (*I)->substVirtReg(NewReg, 0, *TRI);
671 Replacements[MI] = NewReg;
677 bool A15SDOptimizer::runOnMachineFunction(MachineFunction &Fn) {
678 TII = static_cast<const ARMBaseInstrInfo*>(Fn.getTarget().getInstrInfo());
679 TRI = Fn.getTarget().getRegisterInfo();
680 MRI = &Fn.getRegInfo();
681 bool Modified = false;
683 DEBUG(dbgs() << "Running on function " << Fn.getName()<< "\n");
686 Replacements.clear();
688 for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
691 for (MachineBasicBlock::iterator MI = MFI->begin(), ME = MFI->end();
693 Modified |= runOnInstruction(MI++);
698 for (std::set<MachineInstr *>::iterator I = DeadInstr.begin(),
701 (*I)->eraseFromParent();
707 FunctionPass *llvm::createA15SDOptimizerPass() {
708 return new A15SDOptimizer();