1 //=== A15SDOptimizerPass.cpp - Optimize DPR and SPR register accesses on A15==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // The Cortex-A15 processor employs a tracking scheme in its register renaming
11 // in order to process each instruction's micro-ops speculatively and
12 // out-of-order with appropriate forwarding. The ARM architecture allows VFP
13 // instructions to read and write 32-bit S-registers. Each S-register
14 // corresponds to one half (upper or lower) of an overlaid 64-bit D-register.
16 // There are several instruction patterns which can be used to provide this
17 // capability which can provide higher performance than other, potentially more
18 // direct patterns, specifically around when one micro-op reads a D-register
19 // operand that has recently been written as one or more S-register results.
21 // This file defines a pre-regalloc pass which looks for SPR producers which
22 // are going to be used by a DPR (or QPR) consumers and creates the more
23 // optimized access pattern.
25 //===----------------------------------------------------------------------===//
28 #include "ARMBaseInstrInfo.h"
29 #include "ARMBaseRegisterInfo.h"
30 #include "llvm/ADT/Statistic.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineInstr.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Target/TargetRegisterInfo.h"
37 #include "llvm/Target/TargetSubtargetInfo.h"
43 #define DEBUG_TYPE "a15-sd-optimizer"
46 struct A15SDOptimizer : public MachineFunctionPass {
48 A15SDOptimizer() : MachineFunctionPass(ID) {}
50 bool runOnMachineFunction(MachineFunction &Fn) override;
52 const char *getPassName() const override {
53 return "ARM A15 S->D optimizer";
57 const ARMBaseInstrInfo *TII;
58 const TargetRegisterInfo *TRI;
59 MachineRegisterInfo *MRI;
61 bool runOnInstruction(MachineInstr *MI);
64 // Instruction builder helpers
66 unsigned createDupLane(MachineBasicBlock &MBB,
67 MachineBasicBlock::iterator InsertBefore,
69 unsigned Reg, unsigned Lane,
72 unsigned createExtractSubreg(MachineBasicBlock &MBB,
73 MachineBasicBlock::iterator InsertBefore,
75 unsigned DReg, unsigned Lane,
76 const TargetRegisterClass *TRC);
78 unsigned createVExt(MachineBasicBlock &MBB,
79 MachineBasicBlock::iterator InsertBefore,
81 unsigned Ssub0, unsigned Ssub1);
83 unsigned createRegSequence(MachineBasicBlock &MBB,
84 MachineBasicBlock::iterator InsertBefore,
86 unsigned Reg1, unsigned Reg2);
88 unsigned createInsertSubreg(MachineBasicBlock &MBB,
89 MachineBasicBlock::iterator InsertBefore,
90 DebugLoc DL, unsigned DReg, unsigned Lane,
93 unsigned createImplicitDef(MachineBasicBlock &MBB,
94 MachineBasicBlock::iterator InsertBefore,
98 // Various property checkers
100 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
101 bool hasPartialWrite(MachineInstr *MI);
102 SmallVector<unsigned, 8> getReadDPRs(MachineInstr *MI);
103 unsigned getDPRLaneFromSPR(unsigned SReg);
106 // Methods used for getting the definitions of partial registers
109 MachineInstr *elideCopies(MachineInstr *MI);
110 void elideCopiesAndPHIs(MachineInstr *MI,
111 SmallVectorImpl<MachineInstr*> &Outs);
114 // Pattern optimization methods
116 unsigned optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg);
117 unsigned optimizeSDPattern(MachineInstr *MI);
118 unsigned getPrefSPRLane(unsigned SReg);
121 // Sanitizing method - used to make sure if don't leave dead code around.
123 void eraseInstrWithNoUses(MachineInstr *MI);
126 // A map used to track the changes done by this pass.
128 std::map<MachineInstr*, unsigned> Replacements;
129 std::set<MachineInstr *> DeadInstr;
131 char A15SDOptimizer::ID = 0;
132 } // end anonymous namespace
134 // Returns true if this is a use of a SPR register.
135 bool A15SDOptimizer::usesRegClass(MachineOperand &MO,
136 const TargetRegisterClass *TRC) {
139 unsigned Reg = MO.getReg();
141 if (TargetRegisterInfo::isVirtualRegister(Reg))
142 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
144 return TRC->contains(Reg);
147 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) {
148 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
150 if (DReg != ARM::NoRegister) return ARM::ssub_1;
154 // Get the subreg type that is most likely to be coalesced
155 // for an SPR register that will be used in VDUP32d pseudo.
156 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) {
157 if (!TRI->isVirtualRegister(SReg))
158 return getDPRLaneFromSPR(SReg);
160 MachineInstr *MI = MRI->getVRegDef(SReg);
161 if (!MI) return ARM::ssub_0;
162 MachineOperand *MO = MI->findRegisterDefOperand(SReg);
164 assert(MO->isReg() && "Non-register operand found!");
165 if (!MO) return ARM::ssub_0;
167 if (MI->isCopy() && usesRegClass(MI->getOperand(1),
168 &ARM::SPRRegClass)) {
169 SReg = MI->getOperand(1).getReg();
172 if (TargetRegisterInfo::isVirtualRegister(SReg)) {
173 if (MO->getSubReg() == ARM::ssub_1) return ARM::ssub_1;
176 return getDPRLaneFromSPR(SReg);
179 // MI is known to be dead. Figure out what instructions
180 // are also made dead by this and mark them for removal.
181 void A15SDOptimizer::eraseInstrWithNoUses(MachineInstr *MI) {
182 SmallVector<MachineInstr *, 8> Front;
183 DeadInstr.insert(MI);
185 DEBUG(dbgs() << "Deleting base instruction " << *MI << "\n");
188 while (Front.size() != 0) {
192 // MI is already known to be dead. We need to see
193 // if other instructions can also be removed.
194 for (unsigned int i = 0; i < MI->getNumOperands(); ++i) {
195 MachineOperand &MO = MI->getOperand(i);
196 if ((!MO.isReg()) || (!MO.isUse()))
198 unsigned Reg = MO.getReg();
199 if (!TRI->isVirtualRegister(Reg))
201 MachineOperand *Op = MI->findRegisterDefOperand(Reg);
206 MachineInstr *Def = Op->getParent();
208 // We don't need to do anything if we have already marked
209 // this instruction as being dead.
210 if (DeadInstr.find(Def) != DeadInstr.end())
213 // Check if all the uses of this instruction are marked as
214 // dead. If so, we can also mark this instruction as being
217 for (unsigned int j = 0; j < Def->getNumOperands(); ++j) {
218 MachineOperand &MODef = Def->getOperand(j);
219 if ((!MODef.isReg()) || (!MODef.isDef()))
221 unsigned DefReg = MODef.getReg();
222 if (!TRI->isVirtualRegister(DefReg)) {
226 for (MachineRegisterInfo::use_instr_iterator
227 II = MRI->use_instr_begin(Reg), EE = MRI->use_instr_end();
229 // We don't care about self references.
232 if (DeadInstr.find(&*II) == DeadInstr.end()) {
239 if (!IsDead) continue;
241 DEBUG(dbgs() << "Deleting instruction " << *Def << "\n");
242 DeadInstr.insert(Def);
247 // Creates the more optimized patterns and generally does all the code
248 // transformations in this pass.
249 unsigned A15SDOptimizer::optimizeSDPattern(MachineInstr *MI) {
251 return optimizeAllLanesPattern(MI, MI->getOperand(1).getReg());
254 if (MI->isInsertSubreg()) {
255 unsigned DPRReg = MI->getOperand(1).getReg();
256 unsigned SPRReg = MI->getOperand(2).getReg();
258 if (TRI->isVirtualRegister(DPRReg) && TRI->isVirtualRegister(SPRReg)) {
259 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg());
260 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg());
262 if (DPRMI && SPRMI) {
263 // See if the first operand of this insert_subreg is IMPLICIT_DEF
264 MachineInstr *ECDef = elideCopies(DPRMI);
265 if (ECDef && ECDef->isImplicitDef()) {
266 // Another corner case - if we're inserting something that is purely
267 // a subreg copy of a DPR, just use that DPR.
269 MachineInstr *EC = elideCopies(SPRMI);
270 // Is it a subreg copy of ssub_0?
271 if (EC && EC->isCopy() &&
272 EC->getOperand(1).getSubReg() == ARM::ssub_0) {
273 DEBUG(dbgs() << "Found a subreg copy: " << *SPRMI);
275 // Find the thing we're subreg copying out of - is it of the same
276 // regclass as DPRMI? (i.e. a DPR or QPR).
277 unsigned FullReg = SPRMI->getOperand(1).getReg();
278 const TargetRegisterClass *TRC =
279 MRI->getRegClass(MI->getOperand(1).getReg());
280 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) {
281 DEBUG(dbgs() << "Subreg copy is compatible - returning ");
282 DEBUG(dbgs() << PrintReg(FullReg) << "\n");
283 eraseInstrWithNoUses(MI);
288 return optimizeAllLanesPattern(MI, MI->getOperand(2).getReg());
292 return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
295 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1),
296 &ARM::SPRRegClass)) {
297 // See if all bar one of the operands are IMPLICIT_DEF and insert the
298 // optimizer pattern accordingly.
299 unsigned NumImplicit = 0, NumTotal = 0;
300 unsigned NonImplicitReg = ~0U;
302 for (unsigned I = 1; I < MI->getNumExplicitOperands(); ++I) {
303 if (!MI->getOperand(I).isReg())
306 unsigned OpReg = MI->getOperand(I).getReg();
308 if (!TRI->isVirtualRegister(OpReg))
311 MachineInstr *Def = MRI->getVRegDef(OpReg);
314 if (Def->isImplicitDef())
317 NonImplicitReg = MI->getOperand(I).getReg();
320 if (NumImplicit == NumTotal - 1)
321 return optimizeAllLanesPattern(MI, NonImplicitReg);
323 return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
326 llvm_unreachable("Unhandled update pattern!");
329 // Return true if this MachineInstr inserts a scalar (SPR) value into
330 // a D or Q register.
331 bool A15SDOptimizer::hasPartialWrite(MachineInstr *MI) {
332 // The only way we can do a partial register update is through a COPY,
333 // INSERT_SUBREG or REG_SEQUENCE.
334 if (MI->isCopy() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
337 if (MI->isInsertSubreg() && usesRegClass(MI->getOperand(2),
341 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
347 // Looks through full copies to get the instruction that defines the input
349 MachineInstr *A15SDOptimizer::elideCopies(MachineInstr *MI) {
350 if (!MI->isFullCopy())
352 if (!TRI->isVirtualRegister(MI->getOperand(1).getReg()))
354 MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg());
357 return elideCopies(Def);
360 // Look through full copies and PHIs to get the set of non-copy MachineInstrs
361 // that can produce MI.
362 void A15SDOptimizer::elideCopiesAndPHIs(MachineInstr *MI,
363 SmallVectorImpl<MachineInstr*> &Outs) {
364 // Looking through PHIs may create loops so we need to track what
365 // instructions we have visited before.
366 std::set<MachineInstr *> Reached;
367 SmallVector<MachineInstr *, 8> Front;
369 while (Front.size() != 0) {
373 // If we have already explored this MachineInstr, ignore it.
374 if (Reached.find(MI) != Reached.end())
378 for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
379 unsigned Reg = MI->getOperand(I).getReg();
380 if (!TRI->isVirtualRegister(Reg)) {
383 MachineInstr *NewMI = MRI->getVRegDef(Reg);
386 Front.push_back(NewMI);
388 } else if (MI->isFullCopy()) {
389 if (!TRI->isVirtualRegister(MI->getOperand(1).getReg()))
391 MachineInstr *NewMI = MRI->getVRegDef(MI->getOperand(1).getReg());
394 Front.push_back(NewMI);
396 DEBUG(dbgs() << "Found partial copy" << *MI <<"\n");
402 // Return the DPR virtual registers that are read by this machine instruction
404 SmallVector<unsigned, 8> A15SDOptimizer::getReadDPRs(MachineInstr *MI) {
405 if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() ||
407 return SmallVector<unsigned, 8>();
409 SmallVector<unsigned, 8> Defs;
410 for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
411 MachineOperand &MO = MI->getOperand(i);
413 if (!MO.isReg() || !MO.isUse())
415 if (!usesRegClass(MO, &ARM::DPRRegClass) &&
416 !usesRegClass(MO, &ARM::QPRRegClass) &&
417 !usesRegClass(MO, &ARM::DPairRegClass)) // Treat DPair as QPR
420 Defs.push_back(MO.getReg());
425 // Creates a DPR register from an SPR one by using a VDUP.
427 A15SDOptimizer::createDupLane(MachineBasicBlock &MBB,
428 MachineBasicBlock::iterator InsertBefore,
430 unsigned Reg, unsigned Lane, bool QPR) {
431 unsigned Out = MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass :
433 AddDefaultPred(BuildMI(MBB,
436 TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d),
444 // Creates a SPR register from a DPR by copying the value in lane 0.
446 A15SDOptimizer::createExtractSubreg(MachineBasicBlock &MBB,
447 MachineBasicBlock::iterator InsertBefore,
449 unsigned DReg, unsigned Lane,
450 const TargetRegisterClass *TRC) {
451 unsigned Out = MRI->createVirtualRegister(TRC);
455 TII->get(TargetOpcode::COPY), Out)
456 .addReg(DReg, 0, Lane);
461 // Takes two SPR registers and creates a DPR by using a REG_SEQUENCE.
463 A15SDOptimizer::createRegSequence(MachineBasicBlock &MBB,
464 MachineBasicBlock::iterator InsertBefore,
466 unsigned Reg1, unsigned Reg2) {
467 unsigned Out = MRI->createVirtualRegister(&ARM::QPRRegClass);
471 TII->get(TargetOpcode::REG_SEQUENCE), Out)
475 .addImm(ARM::dsub_1);
479 // Takes two DPR registers that have previously been VDUPed (Ssub0 and Ssub1)
480 // and merges them into one DPR register.
482 A15SDOptimizer::createVExt(MachineBasicBlock &MBB,
483 MachineBasicBlock::iterator InsertBefore,
485 unsigned Ssub0, unsigned Ssub1) {
486 unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
487 AddDefaultPred(BuildMI(MBB,
490 TII->get(ARM::VEXTd32), Out)
498 A15SDOptimizer::createInsertSubreg(MachineBasicBlock &MBB,
499 MachineBasicBlock::iterator InsertBefore,
500 DebugLoc DL, unsigned DReg, unsigned Lane,
502 unsigned Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass);
506 TII->get(TargetOpcode::INSERT_SUBREG), Out)
515 A15SDOptimizer::createImplicitDef(MachineBasicBlock &MBB,
516 MachineBasicBlock::iterator InsertBefore,
518 unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
522 TII->get(TargetOpcode::IMPLICIT_DEF), Out);
526 // This function inserts instructions in order to optimize interactions between
527 // SPR registers and DPR/QPR registers. It does so by performing VDUPs on all
528 // lanes, and the using VEXT instructions to recompose the result.
530 A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg) {
531 MachineBasicBlock::iterator InsertPt(MI);
532 DebugLoc DL = MI->getDebugLoc();
533 MachineBasicBlock &MBB = *MI->getParent();
537 // DPair has the same length as QPR and also has two DPRs as subreg.
538 // Treat DPair as QPR.
539 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) ||
540 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) {
541 unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg,
542 ARM::dsub_0, &ARM::DPRRegClass);
543 unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg,
544 ARM::dsub_1, &ARM::DPRRegClass);
546 unsigned Out1 = createDupLane(MBB, InsertPt, DL, DSub0, 0);
547 unsigned Out2 = createDupLane(MBB, InsertPt, DL, DSub0, 1);
548 Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
550 unsigned Out3 = createDupLane(MBB, InsertPt, DL, DSub1, 0);
551 unsigned Out4 = createDupLane(MBB, InsertPt, DL, DSub1, 1);
552 Out2 = createVExt(MBB, InsertPt, DL, Out3, Out4);
554 Out = createRegSequence(MBB, InsertPt, DL, Out, Out2);
556 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) {
557 unsigned Out1 = createDupLane(MBB, InsertPt, DL, Reg, 0);
558 unsigned Out2 = createDupLane(MBB, InsertPt, DL, Reg, 1);
559 Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
562 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) &&
563 "Found unexpected regclass!");
565 unsigned PrefLane = getPrefSPRLane(Reg);
568 case ARM::ssub_0: Lane = 0; break;
569 case ARM::ssub_1: Lane = 1; break;
570 default: llvm_unreachable("Unknown preferred lane!");
573 // Treat DPair as QPR
574 bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass) ||
575 usesRegClass(MI->getOperand(0), &ARM::DPairRegClass);
577 Out = createImplicitDef(MBB, InsertPt, DL);
578 Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);
579 Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);
580 eraseInstrWithNoUses(MI);
585 bool A15SDOptimizer::runOnInstruction(MachineInstr *MI) {
586 // We look for instructions that write S registers that are then read as
587 // D/Q registers. These can only be caused by COPY, INSERT_SUBREG and
588 // REG_SEQUENCE pseudos that insert an SPR value into a DPR register or
589 // merge two SPR values to form a DPR register. In order avoid false
590 // positives we make sure that there is an SPR producer so we look past
591 // COPY and PHI nodes to find it.
593 // The best code pattern for when an SPR producer is going to be used by a
594 // DPR or QPR consumer depends on whether the other lanes of the
595 // corresponding DPR/QPR are currently defined.
597 // We can handle these efficiently, depending on the type of
598 // pseudo-instruction that is producing the pattern
600 // * COPY: * VDUP all lanes and merge the results together
603 // * INSERT_SUBREG: * If the SPR value was originally in another DPR/QPR
604 // lane, and the other lane(s) of the DPR/QPR register
605 // that we are inserting in are undefined, use the
606 // original DPR/QPR value.
607 // * Otherwise, fall back on the same stategy as COPY.
609 // * REG_SEQUENCE: * If all except one of the input operands are
610 // IMPLICIT_DEFs, insert the VDUP pattern for just the
611 // defined input operand
612 // * Otherwise, fall back on the same stategy as COPY.
615 // First, get all the reads of D-registers done by this instruction.
616 SmallVector<unsigned, 8> Defs = getReadDPRs(MI);
617 bool Modified = false;
619 for (SmallVectorImpl<unsigned>::iterator I = Defs.begin(), E = Defs.end();
621 // Follow the def-use chain for this DPR through COPYs, and also through
622 // PHIs (which are essentially multi-way COPYs). It is because of PHIs that
623 // we can end up with multiple defs of this DPR.
625 SmallVector<MachineInstr *, 8> DefSrcs;
626 if (!TRI->isVirtualRegister(*I))
628 MachineInstr *Def = MRI->getVRegDef(*I);
632 elideCopiesAndPHIs(Def, DefSrcs);
634 for (SmallVectorImpl<MachineInstr *>::iterator II = DefSrcs.begin(),
635 EE = DefSrcs.end(); II != EE; ++II) {
636 MachineInstr *MI = *II;
638 // If we've already analyzed and replaced this operand, don't do
640 if (Replacements.find(MI) != Replacements.end())
643 // Now, work out if the instruction causes a SPR->DPR dependency.
644 if (!hasPartialWrite(MI))
647 // Collect all the uses of this MI's DPR def for updating later.
648 SmallVector<MachineOperand*, 8> Uses;
649 unsigned DPRDefReg = MI->getOperand(0).getReg();
650 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DPRDefReg),
651 E = MRI->use_end(); I != E; ++I)
654 // We can optimize this.
655 unsigned NewReg = optimizeSDPattern(MI);
659 for (SmallVectorImpl<MachineOperand *>::const_iterator I = Uses.begin(),
660 E = Uses.end(); I != E; ++I) {
661 // Make sure to constrain the register class of the new register to
662 // match what we're replacing. Otherwise we can optimize a DPR_VFP2
663 // reference into a plain DPR, and that will end poorly. NewReg is
664 // always virtual here, so there will always be a matching subclass
666 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
668 DEBUG(dbgs() << "Replacing operand "
670 << PrintReg(NewReg) << "\n");
671 (*I)->substVirtReg(NewReg, 0, *TRI);
674 Replacements[MI] = NewReg;
680 bool A15SDOptimizer::runOnMachineFunction(MachineFunction &Fn) {
681 TII = static_cast<const ARMBaseInstrInfo *>(Fn.getSubtarget().getInstrInfo());
682 TRI = Fn.getSubtarget().getRegisterInfo();
683 MRI = &Fn.getRegInfo();
684 bool Modified = false;
686 DEBUG(dbgs() << "Running on function " << Fn.getName()<< "\n");
689 Replacements.clear();
691 for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
694 for (MachineBasicBlock::iterator MI = MFI->begin(), ME = MFI->end();
696 Modified |= runOnInstruction(MI++);
701 for (std::set<MachineInstr *>::iterator I = DeadInstr.begin(),
704 (*I)->eraseFromParent();
710 FunctionPass *llvm::createA15SDOptimizerPass() {
711 return new A15SDOptimizer();