1 //=== A15SDOptimizerPass.cpp - Optimize DPR and SPR register accesses on A15==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // The Cortex-A15 processor employs a tracking scheme in its register renaming
11 // in order to process each instruction's micro-ops speculatively and
12 // out-of-order with appropriate forwarding. The ARM architecture allows VFP
13 // instructions to read and write 32-bit S-registers. Each S-register
14 // corresponds to one half (upper or lower) of an overlaid 64-bit D-register.
16 // There are several instruction patterns which can be used to provide this
17 // capability which can provide higher performance than other, potentially more
18 // direct patterns, specifically around when one micro-op reads a D-register
19 // operand that has recently been written as one or more S-register results.
21 // This file defines a pre-regalloc pass which looks for SPR producers which
22 // are going to be used by a DPR (or QPR) consumers and creates the more
23 // optimized access pattern.
25 //===----------------------------------------------------------------------===//
28 #include "ARMBaseInstrInfo.h"
29 #include "ARMBaseRegisterInfo.h"
30 #include "llvm/ADT/Statistic.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineInstr.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Target/TargetRegisterInfo.h"
41 #define DEBUG_TYPE "a15-sd-optimizer"
44 struct A15SDOptimizer : public MachineFunctionPass {
46 A15SDOptimizer() : MachineFunctionPass(ID) {}
48 bool runOnMachineFunction(MachineFunction &Fn) override;
50 const char *getPassName() const override {
51 return "ARM A15 S->D optimizer";
55 const ARMBaseInstrInfo *TII;
56 const TargetRegisterInfo *TRI;
57 MachineRegisterInfo *MRI;
59 bool runOnInstruction(MachineInstr *MI);
62 // Instruction builder helpers
64 unsigned createDupLane(MachineBasicBlock &MBB,
65 MachineBasicBlock::iterator InsertBefore,
67 unsigned Reg, unsigned Lane,
70 unsigned createExtractSubreg(MachineBasicBlock &MBB,
71 MachineBasicBlock::iterator InsertBefore,
73 unsigned DReg, unsigned Lane,
74 const TargetRegisterClass *TRC);
76 unsigned createVExt(MachineBasicBlock &MBB,
77 MachineBasicBlock::iterator InsertBefore,
79 unsigned Ssub0, unsigned Ssub1);
81 unsigned createRegSequence(MachineBasicBlock &MBB,
82 MachineBasicBlock::iterator InsertBefore,
84 unsigned Reg1, unsigned Reg2);
86 unsigned createInsertSubreg(MachineBasicBlock &MBB,
87 MachineBasicBlock::iterator InsertBefore,
88 DebugLoc DL, unsigned DReg, unsigned Lane,
91 unsigned createImplicitDef(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator InsertBefore,
96 // Various property checkers
98 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
99 bool hasPartialWrite(MachineInstr *MI);
100 SmallVector<unsigned, 8> getReadDPRs(MachineInstr *MI);
101 unsigned getDPRLaneFromSPR(unsigned SReg);
104 // Methods used for getting the definitions of partial registers
107 MachineInstr *elideCopies(MachineInstr *MI);
108 void elideCopiesAndPHIs(MachineInstr *MI,
109 SmallVectorImpl<MachineInstr*> &Outs);
112 // Pattern optimization methods
114 unsigned optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg);
115 unsigned optimizeSDPattern(MachineInstr *MI);
116 unsigned getPrefSPRLane(unsigned SReg);
119 // Sanitizing method - used to make sure if don't leave dead code around.
121 void eraseInstrWithNoUses(MachineInstr *MI);
124 // A map used to track the changes done by this pass.
126 std::map<MachineInstr*, unsigned> Replacements;
127 std::set<MachineInstr *> DeadInstr;
129 char A15SDOptimizer::ID = 0;
130 } // end anonymous namespace
132 // Returns true if this is a use of a SPR register.
133 bool A15SDOptimizer::usesRegClass(MachineOperand &MO,
134 const TargetRegisterClass *TRC) {
137 unsigned Reg = MO.getReg();
139 if (TargetRegisterInfo::isVirtualRegister(Reg))
140 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
142 return TRC->contains(Reg);
145 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) {
146 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
148 if (DReg != ARM::NoRegister) return ARM::ssub_1;
152 // Get the subreg type that is most likely to be coalesced
153 // for an SPR register that will be used in VDUP32d pseudo.
154 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) {
155 if (!TRI->isVirtualRegister(SReg))
156 return getDPRLaneFromSPR(SReg);
158 MachineInstr *MI = MRI->getVRegDef(SReg);
159 if (!MI) return ARM::ssub_0;
160 MachineOperand *MO = MI->findRegisterDefOperand(SReg);
162 assert(MO->isReg() && "Non-register operand found!");
163 if (!MO) return ARM::ssub_0;
165 if (MI->isCopy() && usesRegClass(MI->getOperand(1),
166 &ARM::SPRRegClass)) {
167 SReg = MI->getOperand(1).getReg();
170 if (TargetRegisterInfo::isVirtualRegister(SReg)) {
171 if (MO->getSubReg() == ARM::ssub_1) return ARM::ssub_1;
174 return getDPRLaneFromSPR(SReg);
177 // MI is known to be dead. Figure out what instructions
178 // are also made dead by this and mark them for removal.
179 void A15SDOptimizer::eraseInstrWithNoUses(MachineInstr *MI) {
180 SmallVector<MachineInstr *, 8> Front;
181 DeadInstr.insert(MI);
183 DEBUG(dbgs() << "Deleting base instruction " << *MI << "\n");
186 while (Front.size() != 0) {
190 // MI is already known to be dead. We need to see
191 // if other instructions can also be removed.
192 for (unsigned int i = 0; i < MI->getNumOperands(); ++i) {
193 MachineOperand &MO = MI->getOperand(i);
194 if ((!MO.isReg()) || (!MO.isUse()))
196 unsigned Reg = MO.getReg();
197 if (!TRI->isVirtualRegister(Reg))
199 MachineOperand *Op = MI->findRegisterDefOperand(Reg);
204 MachineInstr *Def = Op->getParent();
206 // We don't need to do anything if we have already marked
207 // this instruction as being dead.
208 if (DeadInstr.find(Def) != DeadInstr.end())
211 // Check if all the uses of this instruction are marked as
212 // dead. If so, we can also mark this instruction as being
215 for (unsigned int j = 0; j < Def->getNumOperands(); ++j) {
216 MachineOperand &MODef = Def->getOperand(j);
217 if ((!MODef.isReg()) || (!MODef.isDef()))
219 unsigned DefReg = MODef.getReg();
220 if (!TRI->isVirtualRegister(DefReg)) {
224 for (MachineRegisterInfo::use_instr_iterator
225 II = MRI->use_instr_begin(Reg), EE = MRI->use_instr_end();
227 // We don't care about self references.
230 if (DeadInstr.find(&*II) == DeadInstr.end()) {
237 if (!IsDead) continue;
239 DEBUG(dbgs() << "Deleting instruction " << *Def << "\n");
240 DeadInstr.insert(Def);
245 // Creates the more optimized patterns and generally does all the code
246 // transformations in this pass.
247 unsigned A15SDOptimizer::optimizeSDPattern(MachineInstr *MI) {
249 return optimizeAllLanesPattern(MI, MI->getOperand(1).getReg());
252 if (MI->isInsertSubreg()) {
253 unsigned DPRReg = MI->getOperand(1).getReg();
254 unsigned SPRReg = MI->getOperand(2).getReg();
256 if (TRI->isVirtualRegister(DPRReg) && TRI->isVirtualRegister(SPRReg)) {
257 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg());
258 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg());
260 if (DPRMI && SPRMI) {
261 // See if the first operand of this insert_subreg is IMPLICIT_DEF
262 MachineInstr *ECDef = elideCopies(DPRMI);
263 if (ECDef && ECDef->isImplicitDef()) {
264 // Another corner case - if we're inserting something that is purely
265 // a subreg copy of a DPR, just use that DPR.
267 MachineInstr *EC = elideCopies(SPRMI);
268 // Is it a subreg copy of ssub_0?
269 if (EC && EC->isCopy() &&
270 EC->getOperand(1).getSubReg() == ARM::ssub_0) {
271 DEBUG(dbgs() << "Found a subreg copy: " << *SPRMI);
273 // Find the thing we're subreg copying out of - is it of the same
274 // regclass as DPRMI? (i.e. a DPR or QPR).
275 unsigned FullReg = SPRMI->getOperand(1).getReg();
276 const TargetRegisterClass *TRC =
277 MRI->getRegClass(MI->getOperand(1).getReg());
278 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) {
279 DEBUG(dbgs() << "Subreg copy is compatible - returning ");
280 DEBUG(dbgs() << PrintReg(FullReg) << "\n");
281 eraseInstrWithNoUses(MI);
286 return optimizeAllLanesPattern(MI, MI->getOperand(2).getReg());
290 return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
293 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1),
294 &ARM::SPRRegClass)) {
295 // See if all bar one of the operands are IMPLICIT_DEF and insert the
296 // optimizer pattern accordingly.
297 unsigned NumImplicit = 0, NumTotal = 0;
298 unsigned NonImplicitReg = ~0U;
300 for (unsigned I = 1; I < MI->getNumExplicitOperands(); ++I) {
301 if (!MI->getOperand(I).isReg())
304 unsigned OpReg = MI->getOperand(I).getReg();
306 if (!TRI->isVirtualRegister(OpReg))
309 MachineInstr *Def = MRI->getVRegDef(OpReg);
312 if (Def->isImplicitDef())
315 NonImplicitReg = MI->getOperand(I).getReg();
318 if (NumImplicit == NumTotal - 1)
319 return optimizeAllLanesPattern(MI, NonImplicitReg);
321 return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
324 assert(0 && "Unhandled update pattern!");
328 // Return true if this MachineInstr inserts a scalar (SPR) value into
329 // a D or Q register.
330 bool A15SDOptimizer::hasPartialWrite(MachineInstr *MI) {
331 // The only way we can do a partial register update is through a COPY,
332 // INSERT_SUBREG or REG_SEQUENCE.
333 if (MI->isCopy() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
336 if (MI->isInsertSubreg() && usesRegClass(MI->getOperand(2),
340 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
346 // Looks through full copies to get the instruction that defines the input
348 MachineInstr *A15SDOptimizer::elideCopies(MachineInstr *MI) {
349 if (!MI->isFullCopy())
351 if (!TRI->isVirtualRegister(MI->getOperand(1).getReg()))
353 MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg());
356 return elideCopies(Def);
359 // Look through full copies and PHIs to get the set of non-copy MachineInstrs
360 // that can produce MI.
361 void A15SDOptimizer::elideCopiesAndPHIs(MachineInstr *MI,
362 SmallVectorImpl<MachineInstr*> &Outs) {
363 // Looking through PHIs may create loops so we need to track what
364 // instructions we have visited before.
365 std::set<MachineInstr *> Reached;
366 SmallVector<MachineInstr *, 8> Front;
368 while (Front.size() != 0) {
372 // If we have already explored this MachineInstr, ignore it.
373 if (Reached.find(MI) != Reached.end())
377 for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
378 unsigned Reg = MI->getOperand(I).getReg();
379 if (!TRI->isVirtualRegister(Reg)) {
382 MachineInstr *NewMI = MRI->getVRegDef(Reg);
385 Front.push_back(NewMI);
387 } else if (MI->isFullCopy()) {
388 if (!TRI->isVirtualRegister(MI->getOperand(1).getReg()))
390 MachineInstr *NewMI = MRI->getVRegDef(MI->getOperand(1).getReg());
393 Front.push_back(NewMI);
395 DEBUG(dbgs() << "Found partial copy" << *MI <<"\n");
401 // Return the DPR virtual registers that are read by this machine instruction
403 SmallVector<unsigned, 8> A15SDOptimizer::getReadDPRs(MachineInstr *MI) {
404 if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() ||
406 return SmallVector<unsigned, 8>();
408 SmallVector<unsigned, 8> Defs;
409 for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
410 MachineOperand &MO = MI->getOperand(i);
412 if (!MO.isReg() || !MO.isUse())
414 if (!usesRegClass(MO, &ARM::DPRRegClass) &&
415 !usesRegClass(MO, &ARM::QPRRegClass) &&
416 !usesRegClass(MO, &ARM::DPairRegClass)) // Treat DPair as QPR
419 Defs.push_back(MO.getReg());
424 // Creates a DPR register from an SPR one by using a VDUP.
426 A15SDOptimizer::createDupLane(MachineBasicBlock &MBB,
427 MachineBasicBlock::iterator InsertBefore,
429 unsigned Reg, unsigned Lane, bool QPR) {
430 unsigned Out = MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass :
432 AddDefaultPred(BuildMI(MBB,
435 TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d),
443 // Creates a SPR register from a DPR by copying the value in lane 0.
445 A15SDOptimizer::createExtractSubreg(MachineBasicBlock &MBB,
446 MachineBasicBlock::iterator InsertBefore,
448 unsigned DReg, unsigned Lane,
449 const TargetRegisterClass *TRC) {
450 unsigned Out = MRI->createVirtualRegister(TRC);
454 TII->get(TargetOpcode::COPY), Out)
455 .addReg(DReg, 0, Lane);
460 // Takes two SPR registers and creates a DPR by using a REG_SEQUENCE.
462 A15SDOptimizer::createRegSequence(MachineBasicBlock &MBB,
463 MachineBasicBlock::iterator InsertBefore,
465 unsigned Reg1, unsigned Reg2) {
466 unsigned Out = MRI->createVirtualRegister(&ARM::QPRRegClass);
470 TII->get(TargetOpcode::REG_SEQUENCE), Out)
474 .addImm(ARM::dsub_1);
478 // Takes two DPR registers that have previously been VDUPed (Ssub0 and Ssub1)
479 // and merges them into one DPR register.
481 A15SDOptimizer::createVExt(MachineBasicBlock &MBB,
482 MachineBasicBlock::iterator InsertBefore,
484 unsigned Ssub0, unsigned Ssub1) {
485 unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
486 AddDefaultPred(BuildMI(MBB,
489 TII->get(ARM::VEXTd32), Out)
497 A15SDOptimizer::createInsertSubreg(MachineBasicBlock &MBB,
498 MachineBasicBlock::iterator InsertBefore,
499 DebugLoc DL, unsigned DReg, unsigned Lane,
501 unsigned Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass);
505 TII->get(TargetOpcode::INSERT_SUBREG), Out)
514 A15SDOptimizer::createImplicitDef(MachineBasicBlock &MBB,
515 MachineBasicBlock::iterator InsertBefore,
517 unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
521 TII->get(TargetOpcode::IMPLICIT_DEF), Out);
525 // This function inserts instructions in order to optimize interactions between
526 // SPR registers and DPR/QPR registers. It does so by performing VDUPs on all
527 // lanes, and the using VEXT instructions to recompose the result.
529 A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg) {
530 MachineBasicBlock::iterator InsertPt(MI);
531 DebugLoc DL = MI->getDebugLoc();
532 MachineBasicBlock &MBB = *MI->getParent();
536 // DPair has the same length as QPR and also has two DPRs as subreg.
537 // Treat DPair as QPR.
538 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) ||
539 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) {
540 unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg,
541 ARM::dsub_0, &ARM::DPRRegClass);
542 unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg,
543 ARM::dsub_1, &ARM::DPRRegClass);
545 unsigned Out1 = createDupLane(MBB, InsertPt, DL, DSub0, 0);
546 unsigned Out2 = createDupLane(MBB, InsertPt, DL, DSub0, 1);
547 Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
549 unsigned Out3 = createDupLane(MBB, InsertPt, DL, DSub1, 0);
550 unsigned Out4 = createDupLane(MBB, InsertPt, DL, DSub1, 1);
551 Out2 = createVExt(MBB, InsertPt, DL, Out3, Out4);
553 Out = createRegSequence(MBB, InsertPt, DL, Out, Out2);
555 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) {
556 unsigned Out1 = createDupLane(MBB, InsertPt, DL, Reg, 0);
557 unsigned Out2 = createDupLane(MBB, InsertPt, DL, Reg, 1);
558 Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
561 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) &&
562 "Found unexpected regclass!");
564 unsigned PrefLane = getPrefSPRLane(Reg);
567 case ARM::ssub_0: Lane = 0; break;
568 case ARM::ssub_1: Lane = 1; break;
569 default: llvm_unreachable("Unknown preferred lane!");
572 // Treat DPair as QPR
573 bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass) ||
574 usesRegClass(MI->getOperand(0), &ARM::DPairRegClass);
576 Out = createImplicitDef(MBB, InsertPt, DL);
577 Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);
578 Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);
579 eraseInstrWithNoUses(MI);
584 bool A15SDOptimizer::runOnInstruction(MachineInstr *MI) {
585 // We look for instructions that write S registers that are then read as
586 // D/Q registers. These can only be caused by COPY, INSERT_SUBREG and
587 // REG_SEQUENCE pseudos that insert an SPR value into a DPR register or
588 // merge two SPR values to form a DPR register. In order avoid false
589 // positives we make sure that there is an SPR producer so we look past
590 // COPY and PHI nodes to find it.
592 // The best code pattern for when an SPR producer is going to be used by a
593 // DPR or QPR consumer depends on whether the other lanes of the
594 // corresponding DPR/QPR are currently defined.
596 // We can handle these efficiently, depending on the type of
597 // pseudo-instruction that is producing the pattern
599 // * COPY: * VDUP all lanes and merge the results together
602 // * INSERT_SUBREG: * If the SPR value was originally in another DPR/QPR
603 // lane, and the other lane(s) of the DPR/QPR register
604 // that we are inserting in are undefined, use the
605 // original DPR/QPR value.
606 // * Otherwise, fall back on the same stategy as COPY.
608 // * REG_SEQUENCE: * If all except one of the input operands are
609 // IMPLICIT_DEFs, insert the VDUP pattern for just the
610 // defined input operand
611 // * Otherwise, fall back on the same stategy as COPY.
614 // First, get all the reads of D-registers done by this instruction.
615 SmallVector<unsigned, 8> Defs = getReadDPRs(MI);
616 bool Modified = false;
618 for (SmallVectorImpl<unsigned>::iterator I = Defs.begin(), E = Defs.end();
620 // Follow the def-use chain for this DPR through COPYs, and also through
621 // PHIs (which are essentially multi-way COPYs). It is because of PHIs that
622 // we can end up with multiple defs of this DPR.
624 SmallVector<MachineInstr *, 8> DefSrcs;
625 if (!TRI->isVirtualRegister(*I))
627 MachineInstr *Def = MRI->getVRegDef(*I);
631 elideCopiesAndPHIs(Def, DefSrcs);
633 for (SmallVectorImpl<MachineInstr *>::iterator II = DefSrcs.begin(),
634 EE = DefSrcs.end(); II != EE; ++II) {
635 MachineInstr *MI = *II;
637 // If we've already analyzed and replaced this operand, don't do
639 if (Replacements.find(MI) != Replacements.end())
642 // Now, work out if the instruction causes a SPR->DPR dependency.
643 if (!hasPartialWrite(MI))
646 // Collect all the uses of this MI's DPR def for updating later.
647 SmallVector<MachineOperand*, 8> Uses;
648 unsigned DPRDefReg = MI->getOperand(0).getReg();
649 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DPRDefReg),
650 E = MRI->use_end(); I != E; ++I)
653 // We can optimize this.
654 unsigned NewReg = optimizeSDPattern(MI);
658 for (SmallVectorImpl<MachineOperand *>::const_iterator I = Uses.begin(),
659 E = Uses.end(); I != E; ++I) {
660 // Make sure to constrain the register class of the new register to
661 // match what we're replacing. Otherwise we can optimize a DPR_VFP2
662 // reference into a plain DPR, and that will end poorly. NewReg is
663 // always virtual here, so there will always be a matching subclass
665 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
667 DEBUG(dbgs() << "Replacing operand "
669 << PrintReg(NewReg) << "\n");
670 (*I)->substVirtReg(NewReg, 0, *TRI);
673 Replacements[MI] = NewReg;
679 bool A15SDOptimizer::runOnMachineFunction(MachineFunction &Fn) {
680 TII = static_cast<const ARMBaseInstrInfo*>(Fn.getTarget().getInstrInfo());
681 TRI = Fn.getTarget().getRegisterInfo();
682 MRI = &Fn.getRegInfo();
683 bool Modified = false;
685 DEBUG(dbgs() << "Running on function " << Fn.getName()<< "\n");
688 Replacements.clear();
690 for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
693 for (MachineBasicBlock::iterator MI = MFI->begin(), ME = MFI->end();
695 Modified |= runOnInstruction(MI++);
700 for (std::set<MachineInstr *>::iterator I = DeadInstr.begin(),
703 (*I)->eraseFromParent();
709 FunctionPass *llvm::createA15SDOptimizerPass() {
710 return new A15SDOptimizer();