1 //===-- ARM.h - Top-level interface for ARM representation---- --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the entry points for global functions defined in the LLVM
13 //===----------------------------------------------------------------------===//
18 #include "llvm/Support/ErrorHandling.h"
19 #include "llvm/Target/TargetMachine.h"
24 class ARMBaseTargetMachine;
27 class formatted_raw_ostream;
29 // Enums corresponding to ARM condition codes
31 // The CondCodes constants map directly to the 4-bit encoding of the
32 // condition field for predicated instructions.
33 enum CondCodes { // Meaning (integer) Meaning (floating-point)
35 NE, // Not equal Not equal, or unordered
36 HS, // Carry set >, ==, or unordered
37 LO, // Carry clear Less than
38 MI, // Minus, negative Less than
39 PL, // Plus, positive or zero >, ==, or unordered
40 VS, // Overflow Unordered
41 VC, // No overflow Not unordered
42 HI, // Unsigned higher Greater than, or unordered
43 LS, // Unsigned lower or same Less than or equal
44 GE, // Greater than or equal Greater than or equal
45 LT, // Less than Less than, or unordered
46 GT, // Greater than Greater than
47 LE, // Less than or equal <, ==, or unordered
48 AL // Always (unconditional) Always (unconditional)
51 inline static CondCodes getOppositeCondition(CondCodes CC) {
53 default: llvm_unreachable("Unknown condition code");
72 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
74 default: llvm_unreachable("Unknown condition code");
75 case ARMCC::EQ: return "eq";
76 case ARMCC::NE: return "ne";
77 case ARMCC::HS: return "hs";
78 case ARMCC::LO: return "lo";
79 case ARMCC::MI: return "mi";
80 case ARMCC::PL: return "pl";
81 case ARMCC::VS: return "vs";
82 case ARMCC::VC: return "vc";
83 case ARMCC::HI: return "hi";
84 case ARMCC::LS: return "ls";
85 case ARMCC::GE: return "ge";
86 case ARMCC::LT: return "lt";
87 case ARMCC::GT: return "gt";
88 case ARMCC::LE: return "le";
89 case ARMCC::AL: return "al";
94 // The Memory Barrier Option constants map directly to the 4-bit encoding of
95 // the option field for memory barrier operations.
106 inline static const char *MemBOptToString(unsigned val) {
108 default: llvm_unreachable("Unknown memory opetion");
109 case ST: return "st";
110 case ISH: return "ish";
111 case ISHST: return "ishst";
112 case NSH: return "nsh";
113 case NSHST: return "nshst";
114 case OSH: return "osh";
115 case OSHST: return "oshst";
118 } // namespace ARM_MB
120 FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
121 CodeGenOpt::Level OptLevel);
123 FunctionPass *createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
124 JITCodeEmitter &JCE);
126 FunctionPass *createARMLoadStoreOptimizationPass(bool PreAlloc = false);
127 FunctionPass *createARMExpandPseudoPass();
128 FunctionPass *createARMGlobalMergePass(const TargetLowering* tli);
129 FunctionPass *createARMConstantIslandPass();
130 FunctionPass *createNEONMoveFixPass();
131 FunctionPass *createThumb2ITBlockPass();
132 FunctionPass *createThumb2SizeReductionPass();
134 extern Target TheARMTarget, TheThumbTarget;
136 } // end namespace llvm;
138 // Defines symbolic names for ARM registers. This defines a mapping from
139 // register name to register number.
141 #include "ARMGenRegisterNames.inc"
143 // Defines symbolic names for the ARM instructions.
145 #include "ARMGenInstrNames.inc"