1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // ARM Subtarget state.
23 def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
26 //===----------------------------------------------------------------------===//
27 // ARM Subtarget features.
30 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
31 "Enable VFP2 instructions">;
32 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
33 "Enable VFP3 instructions",
35 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
36 "Enable NEON instructions",
38 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
39 "Enable Thumb2 instructions">;
40 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
41 "Does not support ARM mode execution",
43 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
44 "Enable half-precision floating point">;
45 def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
46 "Enable VFP4 instructions",
47 [FeatureVFP3, FeatureFP16]>;
48 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
49 "true", "Enable ARMv8 FP",
51 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
52 "Restrict VFP3 to 16 double registers">;
53 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
54 "Enable divide instructions">;
55 def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
56 "HasHardwareDivideInARM", "true",
57 "Enable divide instructions in ARM mode">;
58 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
59 "Enable Thumb2 extract and pack instructions">;
60 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
61 "Has data barrier (dmb / dsb) instructions">;
62 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
63 "FP compare + branch is slow">;
64 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
65 "Floating point unit supports single precision only">;
66 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
67 "Enable support for Performance Monitor extensions">;
68 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
69 "Enable support for TrustZone security extensions">;
70 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
71 "Enable support for Cryptography extensions",
73 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
74 "Enable support for CRC instructions">;
76 // Cyclone has preferred instructions for zeroing VFP registers, which can
77 // execute in 0 cycles.
78 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
79 "Has zero-cycle zeroing instructions">;
81 // Some processors have FP multiply-accumulate instructions that don't
82 // play nicely with other VFP / NEON instructions, and it's generally better
83 // to just not use them.
84 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
85 "Disable VFP / NEON MAC instructions">;
87 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
88 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
89 "HasVMLxForwarding", "true",
90 "Has multiplier accumulator forwarding">;
92 // Some processors benefit from using NEON instructions for scalar
93 // single-precision FP operations.
94 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
96 "Use NEON for single precision FP">;
98 // Disable 32-bit to 16-bit narrowing for experimentation.
99 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
100 "Prefer 32-bit Thumb instrs">;
102 /// Some instructions update CPSR partially, which can add false dependency for
103 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
104 /// mapped to a separate physical register. Avoid partial CPSR update for these
106 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
107 "AvoidCPSRPartialUpdate", "true",
108 "Avoid CPSR partial update for OOO execution">;
110 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
111 "AvoidMOVsShifterOperand", "true",
112 "Avoid movs instructions with shifter operand">;
114 // Some processors perform return stack prediction. CodeGen should avoid issue
115 // "normal" call instructions to callees which do not return.
116 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
117 "Has return address stack">;
119 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
120 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
121 "Supports v7 DSP instructions in Thumb2">;
123 // Multiprocessing extension.
124 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
125 "Supports Multiprocessing extension">;
127 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
128 def FeatureVirtualization : SubtargetFeature<"virtualization",
129 "HasVirtualization", "true",
130 "Supports Virtualization extension",
131 [FeatureHWDiv, FeatureHWDivARM]>;
134 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
135 "Is microcontroller profile ('M' series)">;
138 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
139 "Is realtime profile ('R' series)">;
142 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
143 "Is application profile ('A' series)">;
145 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
146 // See ARMInstrInfo.td for details.
147 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
151 def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
152 "Support ARM v4T instructions">;
153 def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
154 "Support ARM v5T instructions",
156 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
157 "Support ARM v5TE, v5TEj, and v5TExp instructions",
159 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
160 "Support ARM v6 instructions",
162 def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true",
163 "Support ARM v6M instructions",
165 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
166 "Support ARM v6t2 instructions",
167 [HasV6MOps, FeatureThumb2]>;
168 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
169 "Support ARM v7 instructions",
170 [HasV6T2Ops, FeaturePerfMon]>;
171 def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
172 "Support ARM v8 instructions",
173 [HasV7Ops, FeatureVirtualization,
176 //===----------------------------------------------------------------------===//
177 // ARM Processors supported.
180 include "ARMSchedule.td"
182 // ARM processor families.
183 def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
184 "Cortex-A5 ARM processors",
185 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
186 FeatureVMLxForwarding, FeatureT2XtPk,
187 FeatureTrustZone, FeatureMP]>;
188 def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
189 "Cortex-A7 ARM processors",
190 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
191 FeatureVMLxForwarding, FeatureT2XtPk,
192 FeatureVFP4, FeatureMP,
193 FeatureHWDiv, FeatureHWDivARM,
194 FeatureTrustZone, FeatureVirtualization]>;
195 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
196 "Cortex-A8 ARM processors",
197 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
198 FeatureVMLxForwarding, FeatureT2XtPk,
200 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
201 "Cortex-A9 ARM processors",
202 [FeatureVMLxForwarding,
203 FeatureT2XtPk, FeatureFP16,
204 FeatureAvoidPartialCPSR,
206 def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
207 "Swift ARM processors",
208 [FeatureNEONForFP, FeatureT2XtPk,
209 FeatureVFP4, FeatureMP, FeatureHWDiv,
210 FeatureHWDivARM, FeatureAvoidPartialCPSR,
211 FeatureAvoidMOVsShOp,
212 FeatureHasSlowFPVMLx, FeatureTrustZone]>;
213 def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
214 "Cortex-A12 ARM processors",
215 [FeatureVMLxForwarding,
216 FeatureT2XtPk, FeatureVFP4,
217 FeatureHWDiv, FeatureHWDivARM,
218 FeatureAvoidPartialCPSR,
219 FeatureVirtualization,
223 // FIXME: It has not been determined if A15 has these features.
224 def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
225 "Cortex-A15 ARM processors",
226 [FeatureT2XtPk, FeatureVFP4,
227 FeatureMP, FeatureHWDiv, FeatureHWDivARM,
228 FeatureAvoidPartialCPSR,
229 FeatureTrustZone, FeatureVirtualization]>;
231 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
232 "Cortex-A53 ARM processors",
233 [FeatureHWDiv, FeatureHWDivARM,
234 FeatureTrustZone, FeatureT2XtPk,
235 FeatureCrypto, FeatureCRC]>;
237 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
238 "Cortex-A57 ARM processors",
239 [FeatureHWDiv, FeatureHWDivARM,
240 FeatureTrustZone, FeatureT2XtPk,
241 FeatureCrypto, FeatureCRC]>;
243 def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
244 "Cortex-R5 ARM processors",
246 FeatureHWDiv, FeatureHWDivARM,
247 FeatureHasSlowFPVMLx,
248 FeatureAvoidPartialCPSR,
251 // FIXME: krait has currently the same features as A9
252 // plus VFP4 and hardware division features.
253 def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
254 "Qualcomm ARM processors",
255 [FeatureVMLxForwarding,
256 FeatureT2XtPk, FeatureFP16,
257 FeatureAvoidPartialCPSR,
264 def FeatureAPCS : SubtargetFeature<"apcs", "TargetABI", "ARM_ABI_APCS",
267 def FeatureAAPCS : SubtargetFeature<"aapcs", "TargetABI", "ARM_ABI_AAPCS",
268 "Use the AAPCS ABI">;
271 class ProcNoItin<string Name, list<SubtargetFeature> Features>
272 : Processor<Name, NoItineraries, Features>;
275 def : ProcNoItin<"generic", []>;
276 def : ProcNoItin<"arm8", []>;
277 def : ProcNoItin<"arm810", []>;
278 def : ProcNoItin<"strongarm", []>;
279 def : ProcNoItin<"strongarm110", []>;
280 def : ProcNoItin<"strongarm1100", []>;
281 def : ProcNoItin<"strongarm1110", []>;
284 def : ProcNoItin<"arm7tdmi", [HasV4TOps]>;
285 def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>;
286 def : ProcNoItin<"arm710t", [HasV4TOps]>;
287 def : ProcNoItin<"arm720t", [HasV4TOps]>;
288 def : ProcNoItin<"arm9", [HasV4TOps]>;
289 def : ProcNoItin<"arm9tdmi", [HasV4TOps]>;
290 def : ProcNoItin<"arm920", [HasV4TOps]>;
291 def : ProcNoItin<"arm920t", [HasV4TOps]>;
292 def : ProcNoItin<"arm922t", [HasV4TOps]>;
293 def : ProcNoItin<"arm940t", [HasV4TOps]>;
294 def : ProcNoItin<"ep9312", [HasV4TOps]>;
297 def : ProcNoItin<"arm10tdmi", [HasV5TOps]>;
298 def : ProcNoItin<"arm1020t", [HasV5TOps]>;
301 def : ProcNoItin<"arm9e", [HasV5TEOps]>;
302 def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>;
303 def : ProcNoItin<"arm946e-s", [HasV5TEOps]>;
304 def : ProcNoItin<"arm966e-s", [HasV5TEOps]>;
305 def : ProcNoItin<"arm968e-s", [HasV5TEOps]>;
306 def : ProcNoItin<"arm10e", [HasV5TEOps]>;
307 def : ProcNoItin<"arm1020e", [HasV5TEOps]>;
308 def : ProcNoItin<"arm1022e", [HasV5TEOps]>;
309 def : ProcNoItin<"xscale", [HasV5TEOps]>;
310 def : ProcNoItin<"iwmmxt", [HasV5TEOps]>;
313 def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>;
314 def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
315 FeatureHasSlowFPVMLx]>;
316 def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>;
317 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
318 FeatureHasSlowFPVMLx]>;
319 def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>;
320 def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
321 FeatureHasSlowFPVMLx]>;
324 def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
325 FeatureDB, FeatureMClass]>;
328 def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops,
330 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
331 FeatureHasSlowFPVMLx,
335 // FIXME: A5 has currently the same Schedule model as A8
336 def : ProcessorModel<"cortex-a5", CortexA8Model,
337 [ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
338 FeatureVFP4, FeatureDSPThumb2,
339 FeatureHasRAS, FeatureAClass]>;
340 def : ProcessorModel<"cortex-a7", CortexA8Model,
341 [ProcA7, HasV7Ops, FeatureNEON, FeatureDB,
342 FeatureDSPThumb2, FeatureHasRAS,
344 def : ProcessorModel<"cortex-a8", CortexA8Model,
345 [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
346 FeatureDSPThumb2, FeatureHasRAS,
348 def : ProcessorModel<"cortex-a9", CortexA9Model,
349 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
350 FeatureDSPThumb2, FeatureHasRAS,
352 def : ProcessorModel<"cortex-a9-mp", CortexA9Model,
353 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
354 FeatureDSPThumb2, FeatureMP,
355 FeatureHasRAS, FeatureAClass]>;
357 // FIXME: A12 has currently the same Schedule model as A9
358 def : ProcessorModel<"cortex-a12", CortexA9Model,
359 [ProcA12, HasV7Ops, FeatureNEON, FeatureDB,
360 FeatureDSPThumb2, FeatureMP,
361 FeatureHasRAS, FeatureAClass]>;
363 // FIXME: A15 has currently the same ProcessorModel as A9.
364 def : ProcessorModel<"cortex-a15", CortexA9Model,
365 [ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
366 FeatureDSPThumb2, FeatureHasRAS,
369 // FIXME: krait has currently the same Schedule model as A9
370 def : ProcessorModel<"krait", CortexA9Model,
371 [ProcKrait, HasV7Ops,
372 FeatureNEON, FeatureDB,
373 FeatureDSPThumb2, FeatureHasRAS,
376 // FIXME: R5 has currently the same ProcessorModel as A8.
377 def : ProcessorModel<"cortex-r5", CortexA8Model,
378 [ProcR5, HasV7Ops, FeatureDB,
379 FeatureVFP3, FeatureDSPThumb2,
380 FeatureHasRAS, FeatureVFPOnlySP,
381 FeatureD16, FeatureRClass]>;
384 def : ProcNoItin<"cortex-m3", [HasV7Ops,
385 FeatureThumb2, FeatureNoARM, FeatureDB,
386 FeatureHWDiv, FeatureMClass]>;
389 def : ProcNoItin<"cortex-m4", [HasV7Ops,
390 FeatureThumb2, FeatureNoARM, FeatureDB,
391 FeatureHWDiv, FeatureDSPThumb2,
392 FeatureT2XtPk, FeatureVFP4,
393 FeatureVFPOnlySP, FeatureD16,
396 // Swift uArch Processors.
397 def : ProcessorModel<"swift", SwiftModel,
398 [ProcSwift, HasV7Ops, FeatureNEON,
399 FeatureDB, FeatureDSPThumb2,
400 FeatureHasRAS, FeatureAClass]>;
403 def : ProcNoItin<"cortex-a53", [ProcA53, HasV8Ops, FeatureAClass,
404 FeatureDB, FeatureFPARMv8,
405 FeatureNEON, FeatureDSPThumb2]>;
406 def : ProcNoItin<"cortex-a57", [ProcA57, HasV8Ops, FeatureAClass,
407 FeatureDB, FeatureFPARMv8,
408 FeatureNEON, FeatureDSPThumb2]>;
410 // Cyclone is very similar to swift
411 def : ProcessorModel<"cyclone", SwiftModel,
412 [ProcSwift, HasV8Ops, HasV7Ops,
413 FeatureCrypto, FeatureFPARMv8,
414 FeatureDB,FeatureDSPThumb2,
415 FeatureHasRAS, FeatureZCZeroing]>;
417 //===----------------------------------------------------------------------===//
418 // Register File Description
419 //===----------------------------------------------------------------------===//
421 include "ARMRegisterInfo.td"
423 include "ARMCallingConv.td"
425 //===----------------------------------------------------------------------===//
426 // Instruction Descriptions
427 //===----------------------------------------------------------------------===//
429 include "ARMInstrInfo.td"
431 def ARMInstrInfo : InstrInfo;
433 //===----------------------------------------------------------------------===//
434 // Declare the target which we are implementing
435 //===----------------------------------------------------------------------===//
438 // Pull in Instruction Info:
439 let InstructionSet = ARMInstrInfo;