1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // ARM Subtarget state.
23 def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
26 //===----------------------------------------------------------------------===//
27 // ARM Subtarget features.
30 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
31 "Enable VFP2 instructions">;
32 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
33 "Enable VFP3 instructions",
35 def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
36 "Enable VFP4 instructions",
38 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
39 "Enable NEON instructions",
41 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
42 "Enable Thumb2 instructions">;
43 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
44 "Does not support ARM mode execution">;
45 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
46 "Enable half-precision floating point">;
47 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
48 "Restrict VFP3 to 16 double registers">;
49 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
50 "Enable divide instructions">;
51 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
52 "Enable Thumb2 extract and pack instructions">;
53 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
54 "Has data barrier (dmb / dsb) instructions">;
55 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
56 "FP compare + branch is slow">;
57 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
58 "Floating point unit supports single precision only">;
60 // Some processors have FP multiply-accumulate instructions that don't
61 // play nicely with other VFP / NEON instructions, and it's generally better
62 // to just not use them.
63 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
64 "Disable VFP / NEON MAC instructions">;
66 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
67 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
68 "HasVMLxForwarding", "true",
69 "Has multiplier accumulator forwarding">;
71 // Some processors benefit from using NEON instructions for scalar
72 // single-precision FP operations.
73 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
75 "Use NEON for single precision FP">;
77 // Disable 32-bit to 16-bit narrowing for experimentation.
78 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
79 "Prefer 32-bit Thumb instrs">;
81 /// Some instructions update CPSR partially, which can add false dependency for
82 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
83 /// mapped to a separate physical register. Avoid partial CPSR update for these
85 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
86 "AvoidCPSRPartialUpdate", "true",
87 "Avoid CPSR partial update for OOO execution">;
89 // Some processors perform return stack prediction. CodeGen should avoid issue
90 // "normal" call instructions to callees which do not return.
91 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
92 "Has return address stack">;
94 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
95 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
96 "Supports v7 DSP instructions in Thumb2">;
98 // Multiprocessing extension.
99 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
100 "Supports Multiprocessing extension">;
103 def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true",
104 "Is microcontroller profile ('M' series)">;
107 def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
108 "Support ARM v4T instructions">;
109 def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
110 "Support ARM v5T instructions",
112 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
113 "Support ARM v5TE, v5TEj, and v5TExp instructions",
115 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
116 "Support ARM v6 instructions",
118 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
119 "Support ARM v6t2 instructions",
120 [HasV6Ops, FeatureThumb2]>;
121 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
122 "Support ARM v7 instructions",
125 //===----------------------------------------------------------------------===//
126 // ARM Processors supported.
129 include "ARMSchedule.td"
131 // ARM processor families.
132 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
133 "Cortex-A8 ARM processors",
134 [FeatureSlowFPBrcc, FeatureNEONForFP,
135 FeatureHasSlowFPVMLx, FeatureVMLxForwarding,
137 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
138 "Cortex-A9 ARM processors",
139 [FeatureVMLxForwarding,
140 FeatureT2XtPk, FeatureFP16,
141 FeatureAvoidPartialCPSR]>;
143 class ProcNoItin<string Name, list<SubtargetFeature> Features>
144 : Processor<Name, GenericItineraries, Features>;
147 def : ProcNoItin<"generic", []>;
148 def : ProcNoItin<"arm8", []>;
149 def : ProcNoItin<"arm810", []>;
150 def : ProcNoItin<"strongarm", []>;
151 def : ProcNoItin<"strongarm110", []>;
152 def : ProcNoItin<"strongarm1100", []>;
153 def : ProcNoItin<"strongarm1110", []>;
156 def : ProcNoItin<"arm7tdmi", [HasV4TOps]>;
157 def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>;
158 def : ProcNoItin<"arm710t", [HasV4TOps]>;
159 def : ProcNoItin<"arm720t", [HasV4TOps]>;
160 def : ProcNoItin<"arm9", [HasV4TOps]>;
161 def : ProcNoItin<"arm9tdmi", [HasV4TOps]>;
162 def : ProcNoItin<"arm920", [HasV4TOps]>;
163 def : ProcNoItin<"arm920t", [HasV4TOps]>;
164 def : ProcNoItin<"arm922t", [HasV4TOps]>;
165 def : ProcNoItin<"arm940t", [HasV4TOps]>;
166 def : ProcNoItin<"ep9312", [HasV4TOps]>;
169 def : ProcNoItin<"arm10tdmi", [HasV5TOps]>;
170 def : ProcNoItin<"arm1020t", [HasV5TOps]>;
173 def : ProcNoItin<"arm9e", [HasV5TEOps]>;
174 def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>;
175 def : ProcNoItin<"arm946e-s", [HasV5TEOps]>;
176 def : ProcNoItin<"arm966e-s", [HasV5TEOps]>;
177 def : ProcNoItin<"arm968e-s", [HasV5TEOps]>;
178 def : ProcNoItin<"arm10e", [HasV5TEOps]>;
179 def : ProcNoItin<"arm1020e", [HasV5TEOps]>;
180 def : ProcNoItin<"arm1022e", [HasV5TEOps]>;
181 def : ProcNoItin<"xscale", [HasV5TEOps]>;
182 def : ProcNoItin<"iwmmxt", [HasV5TEOps]>;
185 def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>;
186 def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
187 FeatureHasSlowFPVMLx]>;
188 def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>;
189 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
190 FeatureHasSlowFPVMLx]>;
191 def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>;
192 def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
193 FeatureHasSlowFPVMLx]>;
196 def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
197 FeatureDB, FeatureMClass]>;
200 def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops,
202 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
203 FeatureHasSlowFPVMLx,
207 def : Processor<"cortex-a8", CortexA8Itineraries,
208 [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
209 FeatureDSPThumb2, FeatureHasRAS]>;
210 def : Processor<"cortex-a9", CortexA9Itineraries,
211 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
212 FeatureDSPThumb2, FeatureHasRAS]>;
213 def : Processor<"cortex-a9-mp", CortexA9Itineraries,
214 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
215 FeatureDSPThumb2, FeatureMP,
219 def : ProcNoItin<"cortex-m3", [HasV7Ops,
220 FeatureThumb2, FeatureNoARM, FeatureDB,
221 FeatureHWDiv, FeatureMClass]>;
224 def : ProcNoItin<"cortex-m4", [HasV7Ops,
225 FeatureThumb2, FeatureNoARM, FeatureDB,
226 FeatureHWDiv, FeatureDSPThumb2,
227 FeatureT2XtPk, FeatureVFP2,
228 FeatureVFPOnlySP, FeatureMClass]>;
230 //===----------------------------------------------------------------------===//
231 // Register File Description
232 //===----------------------------------------------------------------------===//
234 include "ARMRegisterInfo.td"
236 include "ARMCallingConv.td"
238 //===----------------------------------------------------------------------===//
239 // Instruction Descriptions
240 //===----------------------------------------------------------------------===//
242 include "ARMInstrInfo.td"
244 def ARMInstrInfo : InstrInfo;
247 //===----------------------------------------------------------------------===//
249 //===----------------------------------------------------------------------===//
250 // ARM Uses the MC printer for asm output, so make sure the TableGen
251 // AsmWriter bits get associated with the correct class.
252 def ARMAsmWriter : AsmWriter {
253 string AsmWriterClassName = "InstPrinter";
254 bit isMCAsmWriter = 1;
257 //===----------------------------------------------------------------------===//
258 // Declare the target which we are implementing
259 //===----------------------------------------------------------------------===//
262 // Pull in Instruction Info:
263 let InstructionSet = ARMInstrInfo;
265 let AssemblyWriters = [ARMAsmWriter];