lib/Target/ARM/ARM.td

   1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // ARM Subtarget state.
  21 //
  22
  23 def ModeThumb  : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
  24                                   "Thumb mode">;
  25
  26 //===----------------------------------------------------------------------===//
  27 // ARM Subtarget features.
  28 //
  29
  30 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
  31                                    "Enable VFP2 instructions">;
  32 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
  33                                    "Enable VFP3 instructions",
  34                                    [FeatureVFP2]>;
  35 def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
  36                                    "Enable VFP4 instructions",
  37                                    [FeatureVFP3]>;
  38 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  39                                    "Enable NEON instructions",
  40                                    [FeatureVFP3]>;
  41 def FeatureNEON2 : SubtargetFeature<"neon2", "HasNEON2", "true",
  42                                    "Enable Advanced SIMD2 instructions",
  43                                    [FeatureNEON]>;
  44 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
  45                                      "Enable Thumb2 instructions">;
  46 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
  47                                      "Does not support ARM mode execution">;
  48 def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
  49                                      "Enable half-precision floating point">;
  50 def FeatureD16    : SubtargetFeature<"d16", "HasD16", "true",
  51                                      "Restrict VFP3 to 16 double registers">;
  52 def FeatureHWDiv  : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
  53                                      "Enable divide instructions">;
  54 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
  55                                  "Enable Thumb2 extract and pack instructions">;
  56 def FeatureDB     : SubtargetFeature<"db", "HasDataBarrier", "true",
  57                                    "Has data barrier (dmb / dsb) instructions">;
  58 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
  59                                          "FP compare + branch is slow">;
  60 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
  61                           "Floating point unit supports single precision only">;
  62
  63 // Some processors have FP multiply-accumulate instructions that don't
  64 // play nicely with other VFP / NEON instructions, and it's generally better
  65 // to just not use them.
  66 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
  67                                          "Disable VFP / NEON MAC instructions">;
  68
  69 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
  70 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
  71                                        "HasVMLxForwarding", "true",
  72                                        "Has multiplier accumulator forwarding">;
  73
  74 // Some processors benefit from using NEON instructions for scalar
  75 // single-precision FP operations.
  76 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
  77                                         "true",
  78                                         "Use NEON for single precision FP">;
  79 // Allow more precision in FP computation
  80 def FPContractions : Predicate<"!TM.Options.NoExcessFPPrecision">;
  81
  82 // Disable 32-bit to 16-bit narrowing for experimentation.
  83 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
  84                                              "Prefer 32-bit Thumb instrs">;
  85
  86 /// Some instructions update CPSR partially, which can add false dependency for
  87 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
  88 /// mapped to a separate physical register. Avoid partial CPSR update for these
  89 /// processors.
  90 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
  91                                                "AvoidCPSRPartialUpdate", "true",
  92                                  "Avoid CPSR partial update for OOO execution">;
  93
  94 // Some processors perform return stack prediction. CodeGen should avoid issue
  95 // "normal" call instructions to callees which do not return.
  96 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
  97                                      "Has return address stack">;
  98
  99 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
 100 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
 101                                  "Supports v7 DSP instructions in Thumb2">;
 102
 103 // Multiprocessing extension.
 104 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
 105                                  "Supports Multiprocessing extension">;
 106
 107 // M-series ISA?
 108 def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true",
 109                                      "Is microcontroller profile ('M' series)">;
 110
 111 // ARM ISAs.
 112 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
 113                                    "Support ARM v4T instructions">;
 114 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
 115                                    "Support ARM v5T instructions",
 116                                    [HasV4TOps]>;
 117 def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
 118                              "Support ARM v5TE, v5TEj, and v5TExp instructions",
 119                                    [HasV5TOps]>;
 120 def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
 121                                    "Support ARM v6 instructions",
 122                                    [HasV5TEOps]>;
 123 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
 124                                    "Support ARM v6t2 instructions",
 125                                    [HasV6Ops, FeatureThumb2]>;
 126 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
 127                                    "Support ARM v7 instructions",
 128                                    [HasV6T2Ops]>;
 129
 130 //===----------------------------------------------------------------------===//
 131 // ARM Processors supported.
 132 //
 133
 134 include "ARMSchedule.td"
 135
 136 // ARM processor families.
 137 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
 138                                    "Cortex-A8 ARM processors",
 139                                    [FeatureSlowFPBrcc, FeatureNEONForFP,
 140                                     FeatureHasSlowFPVMLx, FeatureVMLxForwarding,
 141                                     FeatureT2XtPk]>;
 142 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 143                                    "Cortex-A9 ARM processors",
 144                                    [FeatureVMLxForwarding,
 145                                     FeatureT2XtPk, FeatureFP16,
 146                                     FeatureAvoidPartialCPSR]>;
 147
 148 class ProcNoItin<string Name, list<SubtargetFeature> Features>
 149  : Processor<Name, GenericItineraries, Features>;
 150
 151 // V4 Processors.
 152 def : ProcNoItin<"generic",         []>;
 153 def : ProcNoItin<"arm8",            []>;
 154 def : ProcNoItin<"arm810",          []>;
 155 def : ProcNoItin<"strongarm",       []>;
 156 def : ProcNoItin<"strongarm110",    []>;
 157 def : ProcNoItin<"strongarm1100",   []>;
 158 def : ProcNoItin<"strongarm1110",   []>;
 159
 160 // V4T Processors.
 161 def : ProcNoItin<"arm7tdmi",        [HasV4TOps]>;
 162 def : ProcNoItin<"arm7tdmi-s",      [HasV4TOps]>;
 163 def : ProcNoItin<"arm710t",         [HasV4TOps]>;
 164 def : ProcNoItin<"arm720t",         [HasV4TOps]>;
 165 def : ProcNoItin<"arm9",            [HasV4TOps]>;
 166 def : ProcNoItin<"arm9tdmi",        [HasV4TOps]>;
 167 def : ProcNoItin<"arm920",          [HasV4TOps]>;
 168 def : ProcNoItin<"arm920t",         [HasV4TOps]>;
 169 def : ProcNoItin<"arm922t",         [HasV4TOps]>;
 170 def : ProcNoItin<"arm940t",         [HasV4TOps]>;
 171 def : ProcNoItin<"ep9312",          [HasV4TOps]>;
 172
 173 // V5T Processors.
 174 def : ProcNoItin<"arm10tdmi",       [HasV5TOps]>;
 175 def : ProcNoItin<"arm1020t",        [HasV5TOps]>;
 176
 177 // V5TE Processors.
 178 def : ProcNoItin<"arm9e",           [HasV5TEOps]>;
 179 def : ProcNoItin<"arm926ej-s",      [HasV5TEOps]>;
 180 def : ProcNoItin<"arm946e-s",       [HasV5TEOps]>;
 181 def : ProcNoItin<"arm966e-s",       [HasV5TEOps]>;
 182 def : ProcNoItin<"arm968e-s",       [HasV5TEOps]>;
 183 def : ProcNoItin<"arm10e",          [HasV5TEOps]>;
 184 def : ProcNoItin<"arm1020e",        [HasV5TEOps]>;
 185 def : ProcNoItin<"arm1022e",        [HasV5TEOps]>;
 186 def : ProcNoItin<"xscale",          [HasV5TEOps]>;
 187 def : ProcNoItin<"iwmmxt",          [HasV5TEOps]>;
 188
 189 // V6 Processors.
 190 def : Processor<"arm1136j-s",       ARMV6Itineraries, [HasV6Ops]>;
 191 def : Processor<"arm1136jf-s",      ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 192                                                        FeatureHasSlowFPVMLx]>;
 193 def : Processor<"arm1176jz-s",      ARMV6Itineraries, [HasV6Ops]>;
 194 def : Processor<"arm1176jzf-s",     ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 195                                                        FeatureHasSlowFPVMLx]>;
 196 def : Processor<"mpcorenovfp",      ARMV6Itineraries, [HasV6Ops]>;
 197 def : Processor<"mpcore",           ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
 198                                                        FeatureHasSlowFPVMLx]>;
 199
 200 // V6M Processors.
 201 def : Processor<"cortex-m0",        ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
 202                                                        FeatureDB, FeatureMClass]>;
 203
 204 // V6T2 Processors.
 205 def : Processor<"arm1156t2-s",      ARMV6Itineraries, [HasV6T2Ops,
 206                                                        FeatureDSPThumb2]>;
 207 def : Processor<"arm1156t2f-s",     ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
 208                                                        FeatureHasSlowFPVMLx,
 209                                                        FeatureDSPThumb2]>;
 210
 211 // V7a Processors.
 212 def : Processor<"cortex-a8",        CortexA8Itineraries,
 213                                     [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
 214                                      FeatureDSPThumb2, FeatureHasRAS]>;
 215 def : Processor<"cortex-a9",        CortexA9Itineraries,
 216                                     [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
 217                                      FeatureDSPThumb2, FeatureHasRAS]>;
 218 def : Processor<"cortex-a9-mp",     CortexA9Itineraries,
 219                                     [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
 220                                      FeatureDSPThumb2, FeatureMP,
 221                                      FeatureHasRAS]>;
 222
 223 // V7M Processors.
 224 def : ProcNoItin<"cortex-m3",       [HasV7Ops,
 225                                      FeatureThumb2, FeatureNoARM, FeatureDB,
 226                                      FeatureHWDiv, FeatureMClass]>;
 227
 228 // V7EM Processors.
 229 def : ProcNoItin<"cortex-m4",       [HasV7Ops,
 230                                      FeatureThumb2, FeatureNoARM, FeatureDB,
 231                                      FeatureHWDiv, FeatureDSPThumb2,
 232                                      FeatureT2XtPk, FeatureVFP2,
 233                                      FeatureVFPOnlySP, FeatureMClass]>;
 234
 235 //===----------------------------------------------------------------------===//
 236 // Register File Description
 237 //===----------------------------------------------------------------------===//
 238
 239 include "ARMRegisterInfo.td"
 240
 241 include "ARMCallingConv.td"
 242
 243 //===----------------------------------------------------------------------===//
 244 // Instruction Descriptions
 245 //===----------------------------------------------------------------------===//
 246
 247 include "ARMInstrInfo.td"
 248
 249 def ARMInstrInfo : InstrInfo;
 250
 251
 252 //===----------------------------------------------------------------------===//
 253 // Assembly printer
 254 //===----------------------------------------------------------------------===//
 255 // ARM Uses the MC printer for asm output, so make sure the TableGen
 256 // AsmWriter bits get associated with the correct class.
 257 def ARMAsmWriter : AsmWriter {
 258   string AsmWriterClassName  = "InstPrinter";
 259   bit isMCAsmWriter = 1;
 260 }
 261
 262 //===----------------------------------------------------------------------===//
 263 // Declare the target which we are implementing
 264 //===----------------------------------------------------------------------===//
 265
 266 def ARM : Target {
 267   // Pull in Instruction Info:
 268   let InstructionSet = ARMInstrInfo;
 269
 270   let AssemblyWriters = [ARMAsmWriter];
 271 }