1 //===- ARM.td - Describe the ARM Target Machine -----------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // ARM Subtarget features.
23 def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
25 def ArchV5T : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
27 def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
28 "ARM v5TE, v5TEj, v5TExp">;
29 def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6",
31 def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
33 def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
35 def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
36 "Enable VFP2 instructions">;
37 def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
38 "Enable VFP3 instructions">;
39 def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
40 "Enable NEON instructions">;
41 def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
42 "Enable Thumb2 instructions">;
43 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
44 "Enable half-precision floating point">;
46 // Some processors have multiply-accumulate instructions that don't
47 // play nicely with other VFP instructions, and it's generally better
48 // to just not use them.
49 // FIXME: Currently, this is only flagged for Cortex-A8. It may be true for
50 // others as well. We should do more benchmarking and confirm one way or
52 def FeatureHasSlowVMLx : SubtargetFeature<"vmlx", "SlowVMLx", "true",
53 "Disable VFP MAC instructions">;
54 // Some processors benefit from using NEON instructions for scalar
55 // single-precision FP operations.
56 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
58 "Use NEON for single precision FP">;
61 //===----------------------------------------------------------------------===//
62 // ARM Processors supported.
65 include "ARMSchedule.td"
67 class ProcNoItin<string Name, list<SubtargetFeature> Features>
68 : Processor<Name, GenericItineraries, Features>;
71 def : ProcNoItin<"generic", []>;
72 def : ProcNoItin<"arm8", []>;
73 def : ProcNoItin<"arm810", []>;
74 def : ProcNoItin<"strongarm", []>;
75 def : ProcNoItin<"strongarm110", []>;
76 def : ProcNoItin<"strongarm1100", []>;
77 def : ProcNoItin<"strongarm1110", []>;
80 def : ProcNoItin<"arm7tdmi", [ArchV4T]>;
81 def : ProcNoItin<"arm7tdmi-s", [ArchV4T]>;
82 def : ProcNoItin<"arm710t", [ArchV4T]>;
83 def : ProcNoItin<"arm720t", [ArchV4T]>;
84 def : ProcNoItin<"arm9", [ArchV4T]>;
85 def : ProcNoItin<"arm9tdmi", [ArchV4T]>;
86 def : ProcNoItin<"arm920", [ArchV4T]>;
87 def : ProcNoItin<"arm920t", [ArchV4T]>;
88 def : ProcNoItin<"arm922t", [ArchV4T]>;
89 def : ProcNoItin<"arm940t", [ArchV4T]>;
90 def : ProcNoItin<"ep9312", [ArchV4T]>;
93 def : ProcNoItin<"arm10tdmi", [ArchV5T]>;
94 def : ProcNoItin<"arm1020t", [ArchV5T]>;
97 def : ProcNoItin<"arm9e", [ArchV5TE]>;
98 def : ProcNoItin<"arm926ej-s", [ArchV5TE]>;
99 def : ProcNoItin<"arm946e-s", [ArchV5TE]>;
100 def : ProcNoItin<"arm966e-s", [ArchV5TE]>;
101 def : ProcNoItin<"arm968e-s", [ArchV5TE]>;
102 def : ProcNoItin<"arm10e", [ArchV5TE]>;
103 def : ProcNoItin<"arm1020e", [ArchV5TE]>;
104 def : ProcNoItin<"arm1022e", [ArchV5TE]>;
105 def : ProcNoItin<"xscale", [ArchV5TE]>;
106 def : ProcNoItin<"iwmmxt", [ArchV5TE]>;
109 def : Processor<"arm1136j-s", ARMV6Itineraries, [ArchV6]>;
110 def : Processor<"arm1136jf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2,
111 FeatureHasSlowVMLx]>;
112 def : Processor<"arm1176jz-s", ARMV6Itineraries, [ArchV6]>;
113 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
114 def : Processor<"mpcorenovfp", ARMV6Itineraries, [ArchV6]>;
115 def : Processor<"mpcore", ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
118 def : Processor<"arm1156t2-s", ARMV6Itineraries,
119 [ArchV6T2, FeatureThumb2]>;
120 def : Processor<"arm1156t2f-s", ARMV6Itineraries,
121 [ArchV6T2, FeatureThumb2, FeatureVFP2]>;
124 def : Processor<"cortex-a8", CortexA8Itineraries,
125 [ArchV7A, FeatureThumb2, FeatureNEON, FeatureHasSlowVMLx,
127 def : Processor<"cortex-a9", CortexA9Itineraries,
128 [ArchV7A, FeatureThumb2, FeatureNEON]>;
130 //===----------------------------------------------------------------------===//
131 // Register File Description
132 //===----------------------------------------------------------------------===//
134 include "ARMRegisterInfo.td"
136 include "ARMCallingConv.td"
138 //===----------------------------------------------------------------------===//
139 // Instruction Descriptions
140 //===----------------------------------------------------------------------===//
142 include "ARMInstrInfo.td"
144 def ARMInstrInfo : InstrInfo;
146 //===----------------------------------------------------------------------===//
147 // Declare the target which we are implementing
148 //===----------------------------------------------------------------------===//
151 // Pull in Instruction Info:
152 let InstructionSet = ARMInstrInfo;