1 //===- ARM.td - Describe the ARM Target Machine ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // ARM Subtarget state.
23 def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
26 def ModeNaCl : SubtargetFeature<"nacl-mode", "InNaClMode", "true",
27 "Native client mode">;
29 //===----------------------------------------------------------------------===//
30 // ARM Subtarget features.
33 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
34 "Enable VFP2 instructions">;
35 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
36 "Enable VFP3 instructions",
38 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
39 "Enable NEON instructions",
41 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
42 "Enable Thumb2 instructions">;
43 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
44 "Does not support ARM mode execution">;
45 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
46 "Enable half-precision floating point">;
47 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
48 "Restrict VFP3 to 16 double registers">;
49 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
50 "Enable divide instructions">;
51 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
52 "Enable Thumb2 extract and pack instructions">;
53 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
54 "Has data barrier (dmb / dsb) instructions">;
55 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
56 "FP compare + branch is slow">;
57 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
58 "Floating point unit supports single precision only">;
60 // Some processors have FP multiply-accumulate instructions that don't
61 // play nicely with other VFP / NEON instructions, and it's generally better
62 // to just not use them.
63 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
64 "Disable VFP / NEON MAC instructions">;
66 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
67 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
68 "HasVMLxForwarding", "true",
69 "Has multiplier accumulator forwarding">;
71 // Some processors benefit from using NEON instructions for scalar
72 // single-precision FP operations.
73 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
75 "Use NEON for single precision FP">;
77 // Disable 32-bit to 16-bit narrowing for experimentation.
78 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
79 "Prefer 32-bit Thumb instrs">;
81 /// Some instructions update CPSR partially, which can add false dependency for
82 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
83 /// mapped to a separate physical register. Avoid partial CPSR update for these
85 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
86 "AvoidCPSRPartialUpdate", "true",
87 "Avoid CPSR partial update for OOO execution">;
89 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
90 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
91 "Supports v7 DSP instructions in Thumb2">;
93 // Multiprocessing extension.
94 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
95 "Supports Multiprocessing extension">;
98 def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
99 "Support ARM v4T instructions">;
100 def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
101 "Support ARM v5T instructions",
103 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
104 "Support ARM v5TE, v5TEj, and v5TExp instructions",
106 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
107 "Support ARM v6 instructions",
109 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
110 "Support ARM v6t2 instructions",
111 [HasV6Ops, FeatureThumb2, FeatureDSPThumb2]>;
112 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
113 "Support ARM v7 instructions",
116 //===----------------------------------------------------------------------===//
117 // ARM Processors supported.
120 include "ARMSchedule.td"
122 // ARM processor families.
123 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
124 "Cortex-A8 ARM processors",
125 [FeatureSlowFPBrcc, FeatureNEONForFP,
126 FeatureHasSlowFPVMLx, FeatureVMLxForwarding,
128 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
129 "Cortex-A9 ARM processors",
130 [FeatureVMLxForwarding,
131 FeatureT2XtPk, FeatureFP16,
132 FeatureAvoidPartialCPSR]>;
134 class ProcNoItin<string Name, list<SubtargetFeature> Features>
135 : Processor<Name, GenericItineraries, Features>;
138 def : ProcNoItin<"generic", []>;
139 def : ProcNoItin<"arm8", []>;
140 def : ProcNoItin<"arm810", []>;
141 def : ProcNoItin<"strongarm", []>;
142 def : ProcNoItin<"strongarm110", []>;
143 def : ProcNoItin<"strongarm1100", []>;
144 def : ProcNoItin<"strongarm1110", []>;
147 def : ProcNoItin<"arm7tdmi", [HasV4TOps]>;
148 def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>;
149 def : ProcNoItin<"arm710t", [HasV4TOps]>;
150 def : ProcNoItin<"arm720t", [HasV4TOps]>;
151 def : ProcNoItin<"arm9", [HasV4TOps]>;
152 def : ProcNoItin<"arm9tdmi", [HasV4TOps]>;
153 def : ProcNoItin<"arm920", [HasV4TOps]>;
154 def : ProcNoItin<"arm920t", [HasV4TOps]>;
155 def : ProcNoItin<"arm922t", [HasV4TOps]>;
156 def : ProcNoItin<"arm940t", [HasV4TOps]>;
157 def : ProcNoItin<"ep9312", [HasV4TOps]>;
160 def : ProcNoItin<"arm10tdmi", [HasV5TOps]>;
161 def : ProcNoItin<"arm1020t", [HasV5TOps]>;
164 def : ProcNoItin<"arm9e", [HasV5TEOps]>;
165 def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>;
166 def : ProcNoItin<"arm946e-s", [HasV5TEOps]>;
167 def : ProcNoItin<"arm966e-s", [HasV5TEOps]>;
168 def : ProcNoItin<"arm968e-s", [HasV5TEOps]>;
169 def : ProcNoItin<"arm10e", [HasV5TEOps]>;
170 def : ProcNoItin<"arm1020e", [HasV5TEOps]>;
171 def : ProcNoItin<"arm1022e", [HasV5TEOps]>;
172 def : ProcNoItin<"xscale", [HasV5TEOps]>;
173 def : ProcNoItin<"iwmmxt", [HasV5TEOps]>;
176 def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>;
177 def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
178 FeatureHasSlowFPVMLx]>;
179 def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>;
180 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
181 FeatureHasSlowFPVMLx]>;
182 def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>;
183 def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
184 FeatureHasSlowFPVMLx]>;
187 def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
191 def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops]>;
192 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
193 FeatureHasSlowFPVMLx]>;
196 def : Processor<"cortex-a8", CortexA8Itineraries,
197 [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
199 def : Processor<"cortex-a9", CortexA9Itineraries,
200 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
202 def : Processor<"cortex-a9-mp", CortexA9Itineraries,
203 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
204 FeatureDSPThumb2, FeatureMP]>;
207 def : ProcNoItin<"cortex-m3", [HasV7Ops,
208 FeatureThumb2, FeatureNoARM, FeatureDB,
212 def : ProcNoItin<"cortex-m4", [HasV7Ops,
213 FeatureThumb2, FeatureNoARM, FeatureDB,
214 FeatureHWDiv, FeatureDSPThumb2,
215 FeatureT2XtPk, FeatureVFP2,
218 //===----------------------------------------------------------------------===//
219 // Register File Description
220 //===----------------------------------------------------------------------===//
222 include "ARMRegisterInfo.td"
224 include "ARMCallingConv.td"
226 //===----------------------------------------------------------------------===//
227 // Instruction Descriptions
228 //===----------------------------------------------------------------------===//
230 include "ARMInstrInfo.td"
232 def ARMInstrInfo : InstrInfo;
235 //===----------------------------------------------------------------------===//
237 //===----------------------------------------------------------------------===//
238 // ARM Uses the MC printer for asm output, so make sure the TableGen
239 // AsmWriter bits get associated with the correct class.
240 def ARMAsmWriter : AsmWriter {
241 string AsmWriterClassName = "InstPrinter";
242 bit isMCAsmWriter = 1;
245 //===----------------------------------------------------------------------===//
246 // Declare the target which we are implementing
247 //===----------------------------------------------------------------------===//
250 // Pull in Instruction Info:
251 let InstructionSet = ARMInstrInfo;
253 let AssemblyWriters = [ARMAsmWriter];