1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // ARM Subtarget state.
23 def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
26 def ModeSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
27 "Use software floating point features.">;
29 //===----------------------------------------------------------------------===//
30 // ARM Subtarget features.
33 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
34 "Enable VFP2 instructions">;
35 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
36 "Enable VFP3 instructions",
38 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
39 "Enable NEON instructions",
41 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
42 "Enable Thumb2 instructions">;
43 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
44 "Does not support ARM mode execution",
46 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
47 "Enable half-precision floating point">;
48 def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
49 "Enable VFP4 instructions",
50 [FeatureVFP3, FeatureFP16]>;
51 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
52 "true", "Enable ARMv8 FP",
54 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
55 "Restrict VFP3 to 16 double registers">;
56 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
57 "Enable divide instructions">;
58 def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
59 "HasHardwareDivideInARM", "true",
60 "Enable divide instructions in ARM mode">;
61 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
62 "Enable Thumb2 extract and pack instructions">;
63 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
64 "Has data barrier (dmb / dsb) instructions">;
65 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
66 "FP compare + branch is slow">;
67 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
68 "Floating point unit supports single precision only">;
69 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
70 "Enable support for Performance Monitor extensions">;
71 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
72 "Enable support for TrustZone security extensions">;
73 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
74 "Enable support for Cryptography extensions",
76 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
77 "Enable support for CRC instructions">;
79 // Cyclone has preferred instructions for zeroing VFP registers, which can
80 // execute in 0 cycles.
81 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
82 "Has zero-cycle zeroing instructions">;
84 // Some processors have FP multiply-accumulate instructions that don't
85 // play nicely with other VFP / NEON instructions, and it's generally better
86 // to just not use them.
87 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
88 "Disable VFP / NEON MAC instructions">;
90 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
91 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
92 "HasVMLxForwarding", "true",
93 "Has multiplier accumulator forwarding">;
95 // Some processors benefit from using NEON instructions for scalar
96 // single-precision FP operations.
97 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
99 "Use NEON for single precision FP">;
101 // Disable 32-bit to 16-bit narrowing for experimentation.
102 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
103 "Prefer 32-bit Thumb instrs">;
105 /// Some instructions update CPSR partially, which can add false dependency for
106 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
107 /// mapped to a separate physical register. Avoid partial CPSR update for these
109 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
110 "AvoidCPSRPartialUpdate", "true",
111 "Avoid CPSR partial update for OOO execution">;
113 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
114 "AvoidMOVsShifterOperand", "true",
115 "Avoid movs instructions with shifter operand">;
117 // Some processors perform return stack prediction. CodeGen should avoid issue
118 // "normal" call instructions to callees which do not return.
119 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
120 "Has return address stack">;
122 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
123 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
124 "Supports v7 DSP instructions in Thumb2">;
126 // Multiprocessing extension.
127 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
128 "Supports Multiprocessing extension">;
130 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
131 def FeatureVirtualization : SubtargetFeature<"virtualization",
132 "HasVirtualization", "true",
133 "Supports Virtualization extension",
134 [FeatureHWDiv, FeatureHWDivARM]>;
137 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
138 "Is microcontroller profile ('M' series)">;
141 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
142 "Is realtime profile ('R' series)">;
145 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
146 "Is application profile ('A' series)">;
148 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
149 // See ARMInstrInfo.td for details.
150 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
154 def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
155 "Support ARM v4T instructions">;
156 def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
157 "Support ARM v5T instructions",
159 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
160 "Support ARM v5TE, v5TEj, and v5TExp instructions",
162 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
163 "Support ARM v6 instructions",
165 def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true",
166 "Support ARM v6M instructions",
168 def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true",
169 "Support ARM v6k instructions",
171 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
172 "Support ARM v6t2 instructions",
173 [HasV6MOps, HasV6KOps, FeatureThumb2]>;
174 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
175 "Support ARM v7 instructions",
176 [HasV6T2Ops, FeaturePerfMon]>;
177 def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
178 "Support ARM v8 instructions",
179 [HasV7Ops, FeatureVirtualization,
181 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
182 "Support ARM v8.1a instructions",
183 [HasV8Ops, FeatureAClass, FeatureCRC]>;
185 //===----------------------------------------------------------------------===//
186 // ARM Processors supported.
189 include "ARMSchedule.td"
191 // ARM processor families.
192 def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
193 "Cortex-A5 ARM processors",
194 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
195 FeatureVMLxForwarding, FeatureT2XtPk,
196 FeatureTrustZone, FeatureMP]>;
197 def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
198 "Cortex-A7 ARM processors",
199 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
200 FeatureVMLxForwarding, FeatureT2XtPk,
201 FeatureVFP4, FeatureMP,
202 FeatureHWDiv, FeatureHWDivARM,
203 FeatureTrustZone, FeatureVirtualization]>;
204 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
205 "Cortex-A8 ARM processors",
206 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
207 FeatureVMLxForwarding, FeatureT2XtPk,
209 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
210 "Cortex-A9 ARM processors",
211 [FeatureVMLxForwarding,
212 FeatureT2XtPk, FeatureFP16,
213 FeatureAvoidPartialCPSR,
215 def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
216 "Swift ARM processors",
217 [FeatureNEONForFP, FeatureT2XtPk,
218 FeatureVFP4, FeatureMP, FeatureHWDiv,
219 FeatureHWDivARM, FeatureAvoidPartialCPSR,
220 FeatureAvoidMOVsShOp,
221 FeatureHasSlowFPVMLx, FeatureTrustZone]>;
222 def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
223 "Cortex-A12 ARM processors",
224 [FeatureVMLxForwarding,
225 FeatureT2XtPk, FeatureVFP4,
226 FeatureHWDiv, FeatureHWDivARM,
227 FeatureAvoidPartialCPSR,
228 FeatureVirtualization,
232 // FIXME: It has not been determined if A15 has these features.
233 def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
234 "Cortex-A15 ARM processors",
235 [FeatureT2XtPk, FeatureVFP4,
236 FeatureMP, FeatureHWDiv, FeatureHWDivARM,
237 FeatureAvoidPartialCPSR,
238 FeatureTrustZone, FeatureVirtualization]>;
240 def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
241 "Cortex-A17 ARM processors",
242 [FeatureVMLxForwarding,
243 FeatureT2XtPk, FeatureVFP4,
244 FeatureHWDiv, FeatureHWDivARM,
245 FeatureAvoidPartialCPSR,
246 FeatureVirtualization,
249 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
250 "Cortex-A53 ARM processors",
251 [FeatureHWDiv, FeatureHWDivARM,
252 FeatureTrustZone, FeatureT2XtPk,
253 FeatureCrypto, FeatureCRC]>;
255 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
256 "Cortex-A57 ARM processors",
257 [FeatureHWDiv, FeatureHWDivARM,
258 FeatureTrustZone, FeatureT2XtPk,
259 FeatureCrypto, FeatureCRC]>;
261 def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
262 "Cortex-R4 ARM processors",
264 FeatureAvoidPartialCPSR,
265 FeatureDSPThumb2, FeatureT2XtPk,
266 HasV7Ops, FeatureDB, FeatureHasRAS,
269 def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
270 "Cortex-R5 ARM processors",
272 FeatureHWDiv, FeatureHWDivARM,
273 FeatureHasSlowFPVMLx,
274 FeatureAvoidPartialCPSR,
277 // FIXME: krait has currently the same features as A9
278 // plus VFP4 and hardware division features.
279 def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
280 "Qualcomm ARM processors",
281 [FeatureVMLxForwarding,
282 FeatureT2XtPk, FeatureFP16,
283 FeatureAvoidPartialCPSR,
290 class ProcNoItin<string Name, list<SubtargetFeature> Features>
291 : Processor<Name, NoItineraries, Features>;
294 def : ProcNoItin<"generic", []>;
295 def : ProcNoItin<"arm8", []>;
296 def : ProcNoItin<"arm810", []>;
297 def : ProcNoItin<"strongarm", []>;
298 def : ProcNoItin<"strongarm110", []>;
299 def : ProcNoItin<"strongarm1100", []>;
300 def : ProcNoItin<"strongarm1110", []>;
303 def : ProcNoItin<"arm7tdmi", [HasV4TOps]>;
304 def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>;
305 def : ProcNoItin<"arm710t", [HasV4TOps]>;
306 def : ProcNoItin<"arm720t", [HasV4TOps]>;
307 def : ProcNoItin<"arm9", [HasV4TOps]>;
308 def : ProcNoItin<"arm9tdmi", [HasV4TOps]>;
309 def : ProcNoItin<"arm920", [HasV4TOps]>;
310 def : ProcNoItin<"arm920t", [HasV4TOps]>;
311 def : ProcNoItin<"arm922t", [HasV4TOps]>;
312 def : ProcNoItin<"arm940t", [HasV4TOps]>;
313 def : ProcNoItin<"ep9312", [HasV4TOps]>;
316 def : ProcNoItin<"arm10tdmi", [HasV5TOps]>;
317 def : ProcNoItin<"arm1020t", [HasV5TOps]>;
320 def : ProcNoItin<"arm9e", [HasV5TEOps]>;
321 def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>;
322 def : ProcNoItin<"arm946e-s", [HasV5TEOps]>;
323 def : ProcNoItin<"arm966e-s", [HasV5TEOps]>;
324 def : ProcNoItin<"arm968e-s", [HasV5TEOps]>;
325 def : ProcNoItin<"arm10e", [HasV5TEOps]>;
326 def : ProcNoItin<"arm1020e", [HasV5TEOps]>;
327 def : ProcNoItin<"arm1022e", [HasV5TEOps]>;
328 def : ProcNoItin<"xscale", [HasV5TEOps]>;
329 def : ProcNoItin<"iwmmxt", [HasV5TEOps]>;
332 def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>;
333 def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
334 FeatureHasSlowFPVMLx]>;
337 def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
338 FeatureDB, FeatureMClass]>;
339 def : Processor<"cortex-m0plus", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
340 FeatureDB, FeatureMClass]>;
341 def : Processor<"cortex-m1", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
342 FeatureDB, FeatureMClass]>;
343 def : Processor<"sc000", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
344 FeatureDB, FeatureMClass]>;
347 def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6KOps]>;
348 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6KOps, FeatureVFP2,
349 FeatureHasSlowFPVMLx]>;
350 def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6KOps]>;
351 def : Processor<"mpcore", ARMV6Itineraries, [HasV6KOps, FeatureVFP2,
352 FeatureHasSlowFPVMLx]>;
355 def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops,
357 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
358 FeatureHasSlowFPVMLx,
362 // FIXME: A5 has currently the same Schedule model as A8
363 def : ProcessorModel<"cortex-a5", CortexA8Model,
364 [ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
365 FeatureVFP4, FeatureDSPThumb2,
366 FeatureHasRAS, FeatureAClass]>;
367 def : ProcessorModel<"cortex-a7", CortexA8Model,
368 [ProcA7, HasV7Ops, FeatureNEON, FeatureDB,
369 FeatureDSPThumb2, FeatureHasRAS,
371 def : ProcessorModel<"cortex-a8", CortexA8Model,
372 [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
373 FeatureDSPThumb2, FeatureHasRAS,
375 def : ProcessorModel<"cortex-a9", CortexA9Model,
376 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
377 FeatureDSPThumb2, FeatureHasRAS, FeatureMP,
380 // FIXME: A12 has currently the same Schedule model as A9
381 def : ProcessorModel<"cortex-a12", CortexA9Model,
382 [ProcA12, HasV7Ops, FeatureNEON, FeatureDB,
383 FeatureDSPThumb2, FeatureMP,
384 FeatureHasRAS, FeatureAClass]>;
386 // FIXME: A15 has currently the same ProcessorModel as A9.
387 def : ProcessorModel<"cortex-a15", CortexA9Model,
388 [ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
389 FeatureDSPThumb2, FeatureHasRAS,
392 // FIXME: A17 has currently the same Schedule model as A9
393 def : ProcessorModel<"cortex-a17", CortexA9Model,
394 [ProcA17, HasV7Ops, FeatureNEON, FeatureDB,
395 FeatureDSPThumb2, FeatureMP,
396 FeatureHasRAS, FeatureAClass]>;
398 // FIXME: krait has currently the same Schedule model as A9
399 def : ProcessorModel<"krait", CortexA9Model,
400 [ProcKrait, HasV7Ops,
401 FeatureNEON, FeatureDB,
402 FeatureDSPThumb2, FeatureHasRAS,
405 // FIXME: R4 has currently the same ProcessorModel as A8.
406 def : ProcessorModel<"cortex-r4", CortexA8Model,
409 // FIXME: R4F has currently the same ProcessorModel as A8.
410 def : ProcessorModel<"cortex-r4f", CortexA8Model,
412 FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
413 FeatureVFP3, FeatureVFPOnlySP, FeatureD16]>;
415 // FIXME: R5 has currently the same ProcessorModel as A8.
416 def : ProcessorModel<"cortex-r5", CortexA8Model,
417 [ProcR5, HasV7Ops, FeatureDB,
418 FeatureVFP3, FeatureDSPThumb2,
419 FeatureHasRAS, FeatureVFPOnlySP,
420 FeatureD16, FeatureRClass]>;
422 // FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
423 def : ProcessorModel<"cortex-r7", CortexA8Model,
424 [ProcR5, HasV7Ops, FeatureDB,
425 FeatureVFP3, FeatureDSPThumb2,
426 FeatureHasRAS, FeatureVFPOnlySP,
427 FeatureD16, FeatureMP, FeatureRClass]>;
430 def : ProcNoItin<"cortex-m3", [HasV7Ops,
431 FeatureThumb2, FeatureNoARM, FeatureDB,
432 FeatureHWDiv, FeatureMClass]>;
433 def : ProcNoItin<"sc300", [HasV7Ops,
434 FeatureThumb2, FeatureNoARM, FeatureDB,
435 FeatureHWDiv, FeatureMClass]>;
438 def : ProcNoItin<"cortex-m4", [HasV7Ops,
439 FeatureThumb2, FeatureNoARM, FeatureDB,
440 FeatureHWDiv, FeatureDSPThumb2,
441 FeatureT2XtPk, FeatureVFP4,
442 FeatureVFPOnlySP, FeatureD16,
444 def : ProcNoItin<"cortex-m7", [HasV7Ops,
445 FeatureThumb2, FeatureNoARM, FeatureDB,
446 FeatureHWDiv, FeatureDSPThumb2,
447 FeatureT2XtPk, FeatureFPARMv8,
448 FeatureD16, FeatureMClass]>;
451 // Swift uArch Processors.
452 def : ProcessorModel<"swift", SwiftModel,
453 [ProcSwift, HasV7Ops, FeatureNEON,
454 FeatureDB, FeatureDSPThumb2,
455 FeatureHasRAS, FeatureAClass]>;
458 def : ProcNoItin<"cortex-a53", [ProcA53, HasV8Ops, FeatureAClass,
459 FeatureDB, FeatureFPARMv8,
460 FeatureNEON, FeatureDSPThumb2]>;
461 def : ProcNoItin<"cortex-a57", [ProcA57, HasV8Ops, FeatureAClass,
462 FeatureDB, FeatureFPARMv8,
463 FeatureNEON, FeatureDSPThumb2]>;
464 // FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
465 def : ProcNoItin<"cortex-a72", [ProcA57, HasV8Ops, FeatureAClass,
466 FeatureDB, FeatureFPARMv8,
467 FeatureNEON, FeatureDSPThumb2]>;
469 // Cyclone is very similar to swift
470 def : ProcessorModel<"cyclone", SwiftModel,
471 [ProcSwift, HasV8Ops, HasV7Ops,
472 FeatureCrypto, FeatureFPARMv8,
473 FeatureDB,FeatureDSPThumb2,
474 FeatureHasRAS, FeatureZCZeroing]>;
476 //===----------------------------------------------------------------------===//
477 // Register File Description
478 //===----------------------------------------------------------------------===//
480 include "ARMRegisterInfo.td"
482 include "ARMCallingConv.td"
484 //===----------------------------------------------------------------------===//
485 // Instruction Descriptions
486 //===----------------------------------------------------------------------===//
488 include "ARMInstrInfo.td"
490 def ARMInstrInfo : InstrInfo;
492 //===----------------------------------------------------------------------===//
493 // Declare the target which we are implementing
494 //===----------------------------------------------------------------------===//
496 def ARMAsmWriter : AsmWriter {
497 string AsmWriterClassName = "InstPrinter";
498 int PassSubtarget = 1;
500 bit isMCAsmWriter = 1;
504 // Pull in Instruction Info:
505 let InstructionSet = ARMInstrInfo;
506 let AssemblyWriters = [ARMAsmWriter];