1 //===- ARM.td - Describe the ARM Target Machine -----------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // ARM Subtarget features.
23 def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
25 def ArchV5T : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
27 def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
28 "ARM v5TE, v5TEj, v5TExp">;
29 def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6",
31 def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
33 def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
35 def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
36 "Enable VFP2 instructions">;
37 def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
38 "Enable VFP3 instructions">;
39 def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
40 "Enable NEON instructions">;
41 def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
42 "Enable Thumb2 instructions">;
43 def FeatureNEONFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
45 "Use NEON for single-precision FP">;
47 //===----------------------------------------------------------------------===//
48 // ARM Processors supported.
51 include "ARMSchedule.td"
53 class ProcNoItin<string Name, list<SubtargetFeature> Features>
54 : Processor<Name, GenericItineraries, Features>;
57 def : ProcNoItin<"generic", []>;
58 def : ProcNoItin<"arm8", []>;
59 def : ProcNoItin<"arm810", []>;
60 def : ProcNoItin<"strongarm", []>;
61 def : ProcNoItin<"strongarm110", []>;
62 def : ProcNoItin<"strongarm1100", []>;
63 def : ProcNoItin<"strongarm1110", []>;
66 def : ProcNoItin<"arm7tdmi", [ArchV4T]>;
67 def : ProcNoItin<"arm7tdmi-s", [ArchV4T]>;
68 def : ProcNoItin<"arm710t", [ArchV4T]>;
69 def : ProcNoItin<"arm720t", [ArchV4T]>;
70 def : ProcNoItin<"arm9", [ArchV4T]>;
71 def : ProcNoItin<"arm9tdmi", [ArchV4T]>;
72 def : ProcNoItin<"arm920", [ArchV4T]>;
73 def : ProcNoItin<"arm920t", [ArchV4T]>;
74 def : ProcNoItin<"arm922t", [ArchV4T]>;
75 def : ProcNoItin<"arm940t", [ArchV4T]>;
76 def : ProcNoItin<"ep9312", [ArchV4T]>;
79 def : ProcNoItin<"arm10tdmi", [ArchV5T]>;
80 def : ProcNoItin<"arm1020t", [ArchV5T]>;
83 def : ProcNoItin<"arm9e", [ArchV5TE]>;
84 def : ProcNoItin<"arm926ej-s", [ArchV5TE]>;
85 def : ProcNoItin<"arm946e-s", [ArchV5TE]>;
86 def : ProcNoItin<"arm966e-s", [ArchV5TE]>;
87 def : ProcNoItin<"arm968e-s", [ArchV5TE]>;
88 def : ProcNoItin<"arm10e", [ArchV5TE]>;
89 def : ProcNoItin<"arm1020e", [ArchV5TE]>;
90 def : ProcNoItin<"arm1022e", [ArchV5TE]>;
91 def : ProcNoItin<"xscale", [ArchV5TE]>;
92 def : ProcNoItin<"iwmmxt", [ArchV5TE]>;
95 def : Processor<"arm1136j-s", V6Itineraries,
97 def : Processor<"arm1136jf-s", V6Itineraries,
98 [ArchV6, FeatureVFP2]>;
99 def : Processor<"arm1176jz-s", V6Itineraries,
101 def : Processor<"arm1176jzf-s", V6Itineraries,
102 [ArchV6, FeatureVFP2]>;
103 def : Processor<"mpcorenovfp", V6Itineraries,
105 def : Processor<"mpcore", V6Itineraries,
106 [ArchV6, FeatureVFP2]>;
109 def : Processor<"arm1156t2-s", V6Itineraries,
110 [ArchV6T2, FeatureThumb2]>;
111 def : Processor<"arm1156t2f-s", V6Itineraries,
112 [ArchV6T2, FeatureThumb2, FeatureVFP2]>;
115 def : Processor<"cortex-a8", CortexA8Itineraries,
116 [ArchV7A, FeatureThumb2, FeatureNEON, FeatureNEONFP]>;
117 def : Processor<"cortex-a9", V7Itineraries,
118 [ArchV7A, FeatureThumb2, FeatureNEON]>;
120 //===----------------------------------------------------------------------===//
121 // Register File Description
122 //===----------------------------------------------------------------------===//
124 include "ARMRegisterInfo.td"
126 include "ARMCallingConv.td"
128 //===----------------------------------------------------------------------===//
129 // Instruction Descriptions
130 //===----------------------------------------------------------------------===//
132 include "ARMInstrInfo.td"
134 def ARMInstrInfo : InstrInfo {
135 // Define how we want to layout our target-specific information field.
136 let TSFlagsFields = ["AddrModeBits",
141 let TSFlagsShifts = [0,
148 //===----------------------------------------------------------------------===//
149 // Declare the target which we are implementing
150 //===----------------------------------------------------------------------===//
153 // Pull in Instruction Info:
154 let InstructionSet = ARMInstrInfo;