1 //===- ARM.td - Describe the ARM Target Machine ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // ARM Subtarget features.
23 def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
24 "Enable VFP2 instructions">;
25 def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
26 "Enable VFP3 instructions">;
27 def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
28 "Enable NEON instructions">;
29 def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
30 "Enable Thumb2 instructions">;
31 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
32 "Does not support ARM mode execution">;
33 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
34 "Enable half-precision floating point">;
35 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
36 "Enable divide instructions">;
37 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
38 "Enable Thumb2 extract and pack instructions">;
39 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
40 "Has data barrier (dmb / dsb) instructions">;
41 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
42 "FP compare + branch is slow">;
43 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
44 "Floating point unit supports single precision only">;
46 // Some processors have multiply-accumulate instructions that don't
47 // play nicely with other VFP instructions, and it's generally better
48 // to just not use them.
49 // FIXME: Currently, this is only flagged for Cortex-A8. It may be true for
50 // others as well. We should do more benchmarking and confirm one way or
52 def FeatureHasSlowVMLx : SubtargetFeature<"vmlx", "SlowVMLx", "true",
53 "Disable VFP MAC instructions">;
54 // Some processors benefit from using NEON instructions for scalar
55 // single-precision FP operations.
56 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
58 "Use NEON for single precision FP">;
60 // Disable 32-bit to 16-bit narrowing for experimentation.
61 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
62 "Prefer 32-bit Thumb instrs">;
66 def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
68 def ArchV5T : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
70 def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
71 "ARM v5TE, v5TEj, v5TExp">;
72 def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6",
74 def ArchV6M : SubtargetFeature<"v6m", "ARMArchVersion", "V6M",
76 [FeatureNoARM, FeatureDB]>;
77 def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
80 def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
82 [FeatureThumb2, FeatureNEON, FeatureDB]>;
83 def ArchV7M : SubtargetFeature<"v7m", "ARMArchVersion", "V7M",
85 [FeatureThumb2, FeatureNoARM, FeatureDB,
88 //===----------------------------------------------------------------------===//
89 // ARM Processors supported.
92 include "ARMSchedule.td"
94 class ProcNoItin<string Name, list<SubtargetFeature> Features>
95 : Processor<Name, GenericItineraries, Features>;
98 def : ProcNoItin<"generic", []>;
99 def : ProcNoItin<"arm8", []>;
100 def : ProcNoItin<"arm810", []>;
101 def : ProcNoItin<"strongarm", []>;
102 def : ProcNoItin<"strongarm110", []>;
103 def : ProcNoItin<"strongarm1100", []>;
104 def : ProcNoItin<"strongarm1110", []>;
107 def : ProcNoItin<"arm7tdmi", [ArchV4T]>;
108 def : ProcNoItin<"arm7tdmi-s", [ArchV4T]>;
109 def : ProcNoItin<"arm710t", [ArchV4T]>;
110 def : ProcNoItin<"arm720t", [ArchV4T]>;
111 def : ProcNoItin<"arm9", [ArchV4T]>;
112 def : ProcNoItin<"arm9tdmi", [ArchV4T]>;
113 def : ProcNoItin<"arm920", [ArchV4T]>;
114 def : ProcNoItin<"arm920t", [ArchV4T]>;
115 def : ProcNoItin<"arm922t", [ArchV4T]>;
116 def : ProcNoItin<"arm940t", [ArchV4T]>;
117 def : ProcNoItin<"ep9312", [ArchV4T]>;
120 def : ProcNoItin<"arm10tdmi", [ArchV5T]>;
121 def : ProcNoItin<"arm1020t", [ArchV5T]>;
124 def : ProcNoItin<"arm9e", [ArchV5TE]>;
125 def : ProcNoItin<"arm926ej-s", [ArchV5TE]>;
126 def : ProcNoItin<"arm946e-s", [ArchV5TE]>;
127 def : ProcNoItin<"arm966e-s", [ArchV5TE]>;
128 def : ProcNoItin<"arm968e-s", [ArchV5TE]>;
129 def : ProcNoItin<"arm10e", [ArchV5TE]>;
130 def : ProcNoItin<"arm1020e", [ArchV5TE]>;
131 def : ProcNoItin<"arm1022e", [ArchV5TE]>;
132 def : ProcNoItin<"xscale", [ArchV5TE]>;
133 def : ProcNoItin<"iwmmxt", [ArchV5TE]>;
136 def : Processor<"arm1136j-s", ARMV6Itineraries, [ArchV6]>;
137 def : Processor<"arm1136jf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2,
138 FeatureHasSlowVMLx]>;
139 def : Processor<"arm1176jz-s", ARMV6Itineraries, [ArchV6]>;
140 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
141 def : Processor<"mpcorenovfp", ARMV6Itineraries, [ArchV6]>;
142 def : Processor<"mpcore", ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
145 def : Processor<"cortex-m0", ARMV6Itineraries, [ArchV6M]>;
148 def : Processor<"arm1156t2-s", ARMV6Itineraries, [ArchV6T2]>;
149 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ArchV6T2, FeatureVFP2]>;
152 def : Processor<"cortex-a8", CortexA8Itineraries,
153 [ArchV7A, FeatureHasSlowVMLx,
154 FeatureSlowFPBrcc, FeatureNEONForFP, FeatureT2XtPk]>;
155 def : Processor<"cortex-a9", CortexA9Itineraries,
156 [ArchV7A, FeatureT2XtPk]>;
159 def : ProcNoItin<"cortex-m3", [ArchV7M]>;
160 def : ProcNoItin<"cortex-m4", [ArchV7M, FeatureVFP2, FeatureVFPOnlySP]>;
162 //===----------------------------------------------------------------------===//
163 // Register File Description
164 //===----------------------------------------------------------------------===//
166 include "ARMRegisterInfo.td"
168 include "ARMCallingConv.td"
170 //===----------------------------------------------------------------------===//
171 // Instruction Descriptions
172 //===----------------------------------------------------------------------===//
174 include "ARMInstrInfo.td"
176 def ARMInstrInfo : InstrInfo;
178 //===----------------------------------------------------------------------===//
179 // Declare the target which we are implementing
180 //===----------------------------------------------------------------------===//
183 // Pull in Instruction Info:
184 let InstructionSet = ARMInstrInfo;