1 //===- ARM.td - Describe the ARM Target Machine ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // ARM Subtarget state.
23 def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
26 //===----------------------------------------------------------------------===//
27 // ARM Subtarget features.
30 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
31 "Enable VFP2 instructions">;
32 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
33 "Enable VFP3 instructions",
35 def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
36 "Enable VFP4 instructions",
38 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
39 "Enable NEON instructions",
41 def FeatureNEONVFP4 : SubtargetFeature<"neon-vfpv4", "HasNEONVFPv4", "true",
42 "Enable NEON-VFP4 instructions",
43 [FeatureVFP4, FeatureNEON]>;
44 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
45 "Enable Thumb2 instructions">;
46 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
47 "Does not support ARM mode execution">;
48 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
49 "Enable half-precision floating point">;
50 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
51 "Restrict VFP3 to 16 double registers">;
52 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
53 "Enable divide instructions">;
54 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
55 "Enable Thumb2 extract and pack instructions">;
56 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
57 "Has data barrier (dmb / dsb) instructions">;
58 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
59 "FP compare + branch is slow">;
60 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
61 "Floating point unit supports single precision only">;
63 // Some processors have FP multiply-accumulate instructions that don't
64 // play nicely with other VFP / NEON instructions, and it's generally better
65 // to just not use them.
66 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
67 "Disable VFP / NEON MAC instructions">;
69 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
70 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
71 "HasVMLxForwarding", "true",
72 "Has multiplier accumulator forwarding">;
74 // Some processors benefit from using NEON instructions for scalar
75 // single-precision FP operations.
76 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
78 "Use NEON for single precision FP">;
80 // Disable 32-bit to 16-bit narrowing for experimentation.
81 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
82 "Prefer 32-bit Thumb instrs">;
84 /// Some instructions update CPSR partially, which can add false dependency for
85 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
86 /// mapped to a separate physical register. Avoid partial CPSR update for these
88 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
89 "AvoidCPSRPartialUpdate", "true",
90 "Avoid CPSR partial update for OOO execution">;
92 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
93 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
94 "Supports v7 DSP instructions in Thumb2">;
96 // Multiprocessing extension.
97 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
98 "Supports Multiprocessing extension">;
101 def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true",
102 "Is microcontroller profile ('M' series)">;
105 def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
106 "Support ARM v4T instructions">;
107 def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
108 "Support ARM v5T instructions",
110 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
111 "Support ARM v5TE, v5TEj, and v5TExp instructions",
113 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
114 "Support ARM v6 instructions",
116 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
117 "Support ARM v6t2 instructions",
118 [HasV6Ops, FeatureThumb2]>;
119 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
120 "Support ARM v7 instructions",
123 //===----------------------------------------------------------------------===//
124 // ARM Processors supported.
127 include "ARMSchedule.td"
129 // ARM processor families.
130 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
131 "Cortex-A8 ARM processors",
132 [FeatureSlowFPBrcc, FeatureNEONForFP,
133 FeatureHasSlowFPVMLx, FeatureVMLxForwarding,
135 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
136 "Cortex-A9 ARM processors",
137 [FeatureVMLxForwarding,
138 FeatureT2XtPk, FeatureFP16,
139 FeatureAvoidPartialCPSR]>;
141 class ProcNoItin<string Name, list<SubtargetFeature> Features>
142 : Processor<Name, GenericItineraries, Features>;
145 def : ProcNoItin<"generic", []>;
146 def : ProcNoItin<"arm8", []>;
147 def : ProcNoItin<"arm810", []>;
148 def : ProcNoItin<"strongarm", []>;
149 def : ProcNoItin<"strongarm110", []>;
150 def : ProcNoItin<"strongarm1100", []>;
151 def : ProcNoItin<"strongarm1110", []>;
154 def : ProcNoItin<"arm7tdmi", [HasV4TOps]>;
155 def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>;
156 def : ProcNoItin<"arm710t", [HasV4TOps]>;
157 def : ProcNoItin<"arm720t", [HasV4TOps]>;
158 def : ProcNoItin<"arm9", [HasV4TOps]>;
159 def : ProcNoItin<"arm9tdmi", [HasV4TOps]>;
160 def : ProcNoItin<"arm920", [HasV4TOps]>;
161 def : ProcNoItin<"arm920t", [HasV4TOps]>;
162 def : ProcNoItin<"arm922t", [HasV4TOps]>;
163 def : ProcNoItin<"arm940t", [HasV4TOps]>;
164 def : ProcNoItin<"ep9312", [HasV4TOps]>;
167 def : ProcNoItin<"arm10tdmi", [HasV5TOps]>;
168 def : ProcNoItin<"arm1020t", [HasV5TOps]>;
171 def : ProcNoItin<"arm9e", [HasV5TEOps]>;
172 def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>;
173 def : ProcNoItin<"arm946e-s", [HasV5TEOps]>;
174 def : ProcNoItin<"arm966e-s", [HasV5TEOps]>;
175 def : ProcNoItin<"arm968e-s", [HasV5TEOps]>;
176 def : ProcNoItin<"arm10e", [HasV5TEOps]>;
177 def : ProcNoItin<"arm1020e", [HasV5TEOps]>;
178 def : ProcNoItin<"arm1022e", [HasV5TEOps]>;
179 def : ProcNoItin<"xscale", [HasV5TEOps]>;
180 def : ProcNoItin<"iwmmxt", [HasV5TEOps]>;
183 def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>;
184 def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
185 FeatureHasSlowFPVMLx]>;
186 def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>;
187 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
188 FeatureHasSlowFPVMLx]>;
189 def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>;
190 def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
191 FeatureHasSlowFPVMLx]>;
194 def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
195 FeatureDB, FeatureMClass]>;
198 def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops,
200 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
201 FeatureHasSlowFPVMLx,
205 def : Processor<"cortex-a8", CortexA8Itineraries,
206 [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
208 def : Processor<"cortex-a9", CortexA9Itineraries,
209 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
211 def : Processor<"cortex-a9-mp", CortexA9Itineraries,
212 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
213 FeatureDSPThumb2, FeatureMP]>;
216 def : ProcNoItin<"cortex-m3", [HasV7Ops,
217 FeatureThumb2, FeatureNoARM, FeatureDB,
218 FeatureHWDiv, FeatureMClass]>;
221 def : ProcNoItin<"cortex-m4", [HasV7Ops,
222 FeatureThumb2, FeatureNoARM, FeatureDB,
223 FeatureHWDiv, FeatureDSPThumb2,
224 FeatureT2XtPk, FeatureVFP2,
225 FeatureVFPOnlySP, FeatureMClass]>;
227 //===----------------------------------------------------------------------===//
228 // Register File Description
229 //===----------------------------------------------------------------------===//
231 include "ARMRegisterInfo.td"
233 include "ARMCallingConv.td"
235 //===----------------------------------------------------------------------===//
236 // Instruction Descriptions
237 //===----------------------------------------------------------------------===//
239 include "ARMInstrInfo.td"
241 def ARMInstrInfo : InstrInfo;
244 //===----------------------------------------------------------------------===//
246 //===----------------------------------------------------------------------===//
247 // ARM Uses the MC printer for asm output, so make sure the TableGen
248 // AsmWriter bits get associated with the correct class.
249 def ARMAsmWriter : AsmWriter {
250 string AsmWriterClassName = "InstPrinter";
251 bit isMCAsmWriter = 1;
254 //===----------------------------------------------------------------------===//
255 // Declare the target which we are implementing
256 //===----------------------------------------------------------------------===//
259 // Pull in Instruction Info:
260 let InstructionSet = ARMInstrInfo;
262 let AssemblyWriters = [ARMAsmWriter];