1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // ARM Subtarget state.
23 def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
26 //===----------------------------------------------------------------------===//
27 // ARM Subtarget features.
30 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
31 "Enable VFP2 instructions">;
32 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
33 "Enable VFP3 instructions",
35 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
36 "Enable NEON instructions",
38 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
39 "Enable Thumb2 instructions">;
40 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
41 "Does not support ARM mode execution",
43 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
44 "Enable half-precision floating point">;
45 def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
46 "Enable VFP4 instructions",
47 [FeatureVFP3, FeatureFP16]>;
48 def FeatureV8FP : SubtargetFeature<"v8fp", "HasV8FP",
49 "true", "Enable ARMv8 FP",
51 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
52 "Restrict VFP3 to 16 double registers">;
53 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
54 "Enable divide instructions">;
55 def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
56 "HasHardwareDivideInARM", "true",
57 "Enable divide instructions in ARM mode">;
58 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
59 "Enable Thumb2 extract and pack instructions">;
60 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
61 "Has data barrier (dmb / dsb) instructions">;
62 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
63 "FP compare + branch is slow">;
64 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
65 "Floating point unit supports single precision only">;
66 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
67 "Enable support for Performance Monitor extensions">;
68 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
69 "Enable support for TrustZone security extensions">;
71 // Some processors have FP multiply-accumulate instructions that don't
72 // play nicely with other VFP / NEON instructions, and it's generally better
73 // to just not use them.
74 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
75 "Disable VFP / NEON MAC instructions">;
77 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
78 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
79 "HasVMLxForwarding", "true",
80 "Has multiplier accumulator forwarding">;
82 // Some processors benefit from using NEON instructions for scalar
83 // single-precision FP operations.
84 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
86 "Use NEON for single precision FP">;
88 // Disable 32-bit to 16-bit narrowing for experimentation.
89 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
90 "Prefer 32-bit Thumb instrs">;
92 /// Some instructions update CPSR partially, which can add false dependency for
93 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
94 /// mapped to a separate physical register. Avoid partial CPSR update for these
96 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
97 "AvoidCPSRPartialUpdate", "true",
98 "Avoid CPSR partial update for OOO execution">;
100 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
101 "AvoidMOVsShifterOperand", "true",
102 "Avoid movs instructions with shifter operand">;
104 // Some processors perform return stack prediction. CodeGen should avoid issue
105 // "normal" call instructions to callees which do not return.
106 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
107 "Has return address stack">;
109 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
110 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
111 "Supports v7 DSP instructions in Thumb2">;
113 // Multiprocessing extension.
114 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
115 "Supports Multiprocessing extension">;
118 def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true",
119 "Is microcontroller profile ('M' series)">;
121 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
122 // See ARMInstrInfo.td for details.
123 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
127 def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
128 "Support ARM v4T instructions">;
129 def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
130 "Support ARM v5T instructions",
132 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
133 "Support ARM v5TE, v5TEj, and v5TExp instructions",
135 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
136 "Support ARM v6 instructions",
138 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
139 "Support ARM v6t2 instructions",
140 [HasV6Ops, FeatureThumb2]>;
141 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
142 "Support ARM v7 instructions",
143 [HasV6T2Ops, FeaturePerfMon]>;
144 def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
145 "Support ARM v8 instructions",
148 //===----------------------------------------------------------------------===//
149 // ARM Processors supported.
152 include "ARMSchedule.td"
154 // ARM processor families.
155 def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
156 "Cortex-A5 ARM processors",
157 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
158 FeatureVMLxForwarding, FeatureT2XtPk,
160 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
161 "Cortex-A8 ARM processors",
162 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
163 FeatureVMLxForwarding, FeatureT2XtPk,
165 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
166 "Cortex-A9 ARM processors",
167 [FeatureVMLxForwarding,
168 FeatureT2XtPk, FeatureFP16,
169 FeatureAvoidPartialCPSR,
171 def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
172 "Swift ARM processors",
173 [FeatureNEONForFP, FeatureT2XtPk,
174 FeatureVFP4, FeatureMP, FeatureHWDiv,
175 FeatureHWDivARM, FeatureAvoidPartialCPSR,
176 FeatureAvoidMOVsShOp,
177 FeatureHasSlowFPVMLx, FeatureTrustZone]>;
179 // FIXME: It has not been determined if A15 has these features.
180 def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
181 "Cortex-A15 ARM processors",
182 [FeatureT2XtPk, FeatureFP16,
183 FeatureAvoidPartialCPSR,
185 def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
186 "Cortex-R5 ARM processors",
188 FeatureHWDiv, FeatureHWDivARM,
189 FeatureHasSlowFPVMLx,
190 FeatureAvoidPartialCPSR,
193 class ProcNoItin<string Name, list<SubtargetFeature> Features>
194 : Processor<Name, NoItineraries, Features>;
197 def : ProcNoItin<"generic", []>;
198 def : ProcNoItin<"arm8", []>;
199 def : ProcNoItin<"arm810", []>;
200 def : ProcNoItin<"strongarm", []>;
201 def : ProcNoItin<"strongarm110", []>;
202 def : ProcNoItin<"strongarm1100", []>;
203 def : ProcNoItin<"strongarm1110", []>;
206 def : ProcNoItin<"arm7tdmi", [HasV4TOps]>;
207 def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>;
208 def : ProcNoItin<"arm710t", [HasV4TOps]>;
209 def : ProcNoItin<"arm720t", [HasV4TOps]>;
210 def : ProcNoItin<"arm9", [HasV4TOps]>;
211 def : ProcNoItin<"arm9tdmi", [HasV4TOps]>;
212 def : ProcNoItin<"arm920", [HasV4TOps]>;
213 def : ProcNoItin<"arm920t", [HasV4TOps]>;
214 def : ProcNoItin<"arm922t", [HasV4TOps]>;
215 def : ProcNoItin<"arm940t", [HasV4TOps]>;
216 def : ProcNoItin<"ep9312", [HasV4TOps]>;
219 def : ProcNoItin<"arm10tdmi", [HasV5TOps]>;
220 def : ProcNoItin<"arm1020t", [HasV5TOps]>;
223 def : ProcNoItin<"arm9e", [HasV5TEOps]>;
224 def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>;
225 def : ProcNoItin<"arm946e-s", [HasV5TEOps]>;
226 def : ProcNoItin<"arm966e-s", [HasV5TEOps]>;
227 def : ProcNoItin<"arm968e-s", [HasV5TEOps]>;
228 def : ProcNoItin<"arm10e", [HasV5TEOps]>;
229 def : ProcNoItin<"arm1020e", [HasV5TEOps]>;
230 def : ProcNoItin<"arm1022e", [HasV5TEOps]>;
231 def : ProcNoItin<"xscale", [HasV5TEOps]>;
232 def : ProcNoItin<"iwmmxt", [HasV5TEOps]>;
235 def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>;
236 def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
237 FeatureHasSlowFPVMLx]>;
238 def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>;
239 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
240 FeatureHasSlowFPVMLx]>;
241 def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>;
242 def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
243 FeatureHasSlowFPVMLx]>;
246 def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
247 FeatureDB, FeatureMClass]>;
250 def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops,
252 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
253 FeatureHasSlowFPVMLx,
257 // FIXME: A5 has currently the same Schedule model as A8
258 def : ProcessorModel<"cortex-a5", CortexA8Model,
259 [ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
260 FeatureVFP4, FeatureDSPThumb2,
262 def : ProcessorModel<"cortex-a8", CortexA8Model,
263 [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
264 FeatureDSPThumb2, FeatureHasRAS]>;
265 def : ProcessorModel<"cortex-a9", CortexA9Model,
266 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
267 FeatureDSPThumb2, FeatureHasRAS]>;
268 def : ProcessorModel<"cortex-a9-mp", CortexA9Model,
269 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
270 FeatureDSPThumb2, FeatureMP,
272 // FIXME: A15 has currently the same ProcessorModel as A9.
273 def : ProcessorModel<"cortex-a15", CortexA9Model,
274 [ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
275 FeatureDSPThumb2, FeatureHasRAS]>;
276 // FIXME: R5 has currently the same ProcessorModel as A8.
277 def : ProcessorModel<"cortex-r5", CortexA8Model,
278 [ProcR5, HasV7Ops, FeatureDB,
279 FeatureVFP3, FeatureDSPThumb2,
283 def : ProcNoItin<"cortex-m3", [HasV7Ops,
284 FeatureThumb2, FeatureNoARM, FeatureDB,
285 FeatureHWDiv, FeatureMClass]>;
288 def : ProcNoItin<"cortex-m4", [HasV7Ops,
289 FeatureThumb2, FeatureNoARM, FeatureDB,
290 FeatureHWDiv, FeatureDSPThumb2,
291 FeatureT2XtPk, FeatureVFP4,
292 FeatureVFPOnlySP, FeatureMClass]>;
294 // Swift uArch Processors.
295 def : ProcessorModel<"swift", SwiftModel,
296 [ProcSwift, HasV7Ops, FeatureNEON,
297 FeatureDB, FeatureDSPThumb2,
301 def : ProcNoItin<"cortex-a53", [HasV8Ops]>;
303 //===----------------------------------------------------------------------===//
304 // Register File Description
305 //===----------------------------------------------------------------------===//
307 include "ARMRegisterInfo.td"
309 include "ARMCallingConv.td"
311 //===----------------------------------------------------------------------===//
312 // Instruction Descriptions
313 //===----------------------------------------------------------------------===//
315 include "ARMInstrInfo.td"
317 def ARMInstrInfo : InstrInfo;
320 //===----------------------------------------------------------------------===//
322 //===----------------------------------------------------------------------===//
323 // ARM Uses the MC printer for asm output, so make sure the TableGen
324 // AsmWriter bits get associated with the correct class.
325 def ARMAsmWriter : AsmWriter {
326 string AsmWriterClassName = "InstPrinter";
327 bit isMCAsmWriter = 1;
330 //===----------------------------------------------------------------------===//
331 // Declare the target which we are implementing
332 //===----------------------------------------------------------------------===//
335 // Pull in Instruction Info:
336 let InstructionSet = ARMInstrInfo;
338 let AssemblyWriters = [ARMAsmWriter];