1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // ARM Subtarget state.
23 def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
26 //===----------------------------------------------------------------------===//
27 // ARM Subtarget features.
30 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
31 "Enable VFP2 instructions">;
32 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
33 "Enable VFP3 instructions",
35 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
36 "Enable NEON instructions",
38 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
39 "Enable Thumb2 instructions">;
40 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
41 "Does not support ARM mode execution",
43 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
44 "Enable half-precision floating point">;
45 def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
46 "Enable VFP4 instructions",
47 [FeatureVFP3, FeatureFP16]>;
48 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
49 "true", "Enable ARMv8 FP",
51 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
52 "Restrict VFP3 to 16 double registers">;
53 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
54 "Enable divide instructions">;
55 def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
56 "HasHardwareDivideInARM", "true",
57 "Enable divide instructions in ARM mode">;
58 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
59 "Enable Thumb2 extract and pack instructions">;
60 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
61 "Has data barrier (dmb / dsb) instructions">;
62 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
63 "FP compare + branch is slow">;
64 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
65 "Floating point unit supports single precision only">;
66 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
67 "Enable support for Performance Monitor extensions">;
68 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
69 "Enable support for TrustZone security extensions">;
70 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
71 "Enable support for Cryptography extensions",
73 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
74 "Enable support for CRC instructions">;
76 // Some processors have FP multiply-accumulate instructions that don't
77 // play nicely with other VFP / NEON instructions, and it's generally better
78 // to just not use them.
79 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
80 "Disable VFP / NEON MAC instructions">;
82 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
83 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
84 "HasVMLxForwarding", "true",
85 "Has multiplier accumulator forwarding">;
87 // Some processors benefit from using NEON instructions for scalar
88 // single-precision FP operations.
89 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
91 "Use NEON for single precision FP">;
93 // Disable 32-bit to 16-bit narrowing for experimentation.
94 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
95 "Prefer 32-bit Thumb instrs">;
97 /// Some instructions update CPSR partially, which can add false dependency for
98 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
99 /// mapped to a separate physical register. Avoid partial CPSR update for these
101 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
102 "AvoidCPSRPartialUpdate", "true",
103 "Avoid CPSR partial update for OOO execution">;
105 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
106 "AvoidMOVsShifterOperand", "true",
107 "Avoid movs instructions with shifter operand">;
109 // Some processors perform return stack prediction. CodeGen should avoid issue
110 // "normal" call instructions to callees which do not return.
111 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
112 "Has return address stack">;
114 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
115 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
116 "Supports v7 DSP instructions in Thumb2">;
118 // Multiprocessing extension.
119 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
120 "Supports Multiprocessing extension">;
122 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
123 def FeatureVirtualization : SubtargetFeature<"virtualization",
124 "HasVirtualization", "true",
125 "Supports Virtualization extension",
126 [FeatureHWDiv, FeatureHWDivARM]>;
129 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
130 "Is microcontroller profile ('M' series)">;
133 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
134 "Is realtime profile ('R' series)">;
137 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
138 "Is application profile ('A' series)">;
140 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
141 // See ARMInstrInfo.td for details.
142 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
146 def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
147 "Support ARM v4T instructions">;
148 def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
149 "Support ARM v5T instructions",
151 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
152 "Support ARM v5TE, v5TEj, and v5TExp instructions",
154 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
155 "Support ARM v6 instructions",
157 def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true",
158 "Support ARM v6M instructions",
160 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
161 "Support ARM v6t2 instructions",
162 [HasV6MOps, FeatureThumb2]>;
163 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
164 "Support ARM v7 instructions",
165 [HasV6T2Ops, FeaturePerfMon]>;
166 def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
167 "Support ARM v8 instructions",
168 [HasV7Ops, FeatureVirtualization,
171 //===----------------------------------------------------------------------===//
172 // ARM Processors supported.
175 include "ARMSchedule.td"
177 // ARM processor families.
178 def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
179 "Cortex-A5 ARM processors",
180 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
181 FeatureVMLxForwarding, FeatureT2XtPk,
182 FeatureTrustZone, FeatureMP]>;
183 def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
184 "Cortex-A7 ARM processors",
185 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
186 FeatureVMLxForwarding, FeatureT2XtPk,
187 FeatureVFP4, FeatureMP,
188 FeatureHWDiv, FeatureHWDivARM,
189 FeatureTrustZone, FeatureVirtualization]>;
190 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
191 "Cortex-A8 ARM processors",
192 [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
193 FeatureVMLxForwarding, FeatureT2XtPk,
195 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
196 "Cortex-A9 ARM processors",
197 [FeatureVMLxForwarding,
198 FeatureT2XtPk, FeatureFP16,
199 FeatureAvoidPartialCPSR,
201 def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
202 "Swift ARM processors",
203 [FeatureNEONForFP, FeatureT2XtPk,
204 FeatureVFP4, FeatureMP, FeatureHWDiv,
205 FeatureHWDivARM, FeatureAvoidPartialCPSR,
206 FeatureAvoidMOVsShOp,
207 FeatureHasSlowFPVMLx, FeatureTrustZone]>;
208 def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
209 "Cortex-A12 ARM processors",
210 [FeatureVMLxForwarding,
211 FeatureT2XtPk, FeatureVFP4,
212 FeatureHWDiv, FeatureHWDivARM,
213 FeatureAvoidPartialCPSR,
214 FeatureVirtualization,
218 // FIXME: It has not been determined if A15 has these features.
219 def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
220 "Cortex-A15 ARM processors",
221 [FeatureT2XtPk, FeatureVFP4,
222 FeatureMP, FeatureHWDiv, FeatureHWDivARM,
223 FeatureAvoidPartialCPSR,
224 FeatureTrustZone, FeatureVirtualization]>;
226 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
227 "Cortex-A53 ARM processors",
228 [FeatureHWDiv, FeatureHWDivARM,
229 FeatureTrustZone, FeatureT2XtPk,
230 FeatureCrypto, FeatureCRC]>;
232 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
233 "Cortex-A57 ARM processors",
234 [FeatureHWDiv, FeatureHWDivARM,
235 FeatureTrustZone, FeatureT2XtPk,
236 FeatureCrypto, FeatureCRC]>;
238 def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
239 "Cortex-R5 ARM processors",
241 FeatureHWDiv, FeatureHWDivARM,
242 FeatureHasSlowFPVMLx,
243 FeatureAvoidPartialCPSR,
246 class ProcNoItin<string Name, list<SubtargetFeature> Features>
247 : Processor<Name, NoItineraries, Features>;
250 def : ProcNoItin<"generic", []>;
251 def : ProcNoItin<"arm8", []>;
252 def : ProcNoItin<"arm810", []>;
253 def : ProcNoItin<"strongarm", []>;
254 def : ProcNoItin<"strongarm110", []>;
255 def : ProcNoItin<"strongarm1100", []>;
256 def : ProcNoItin<"strongarm1110", []>;
259 def : ProcNoItin<"arm7tdmi", [HasV4TOps]>;
260 def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>;
261 def : ProcNoItin<"arm710t", [HasV4TOps]>;
262 def : ProcNoItin<"arm720t", [HasV4TOps]>;
263 def : ProcNoItin<"arm9", [HasV4TOps]>;
264 def : ProcNoItin<"arm9tdmi", [HasV4TOps]>;
265 def : ProcNoItin<"arm920", [HasV4TOps]>;
266 def : ProcNoItin<"arm920t", [HasV4TOps]>;
267 def : ProcNoItin<"arm922t", [HasV4TOps]>;
268 def : ProcNoItin<"arm940t", [HasV4TOps]>;
269 def : ProcNoItin<"ep9312", [HasV4TOps]>;
272 def : ProcNoItin<"arm10tdmi", [HasV5TOps]>;
273 def : ProcNoItin<"arm1020t", [HasV5TOps]>;
276 def : ProcNoItin<"arm9e", [HasV5TEOps]>;
277 def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>;
278 def : ProcNoItin<"arm946e-s", [HasV5TEOps]>;
279 def : ProcNoItin<"arm966e-s", [HasV5TEOps]>;
280 def : ProcNoItin<"arm968e-s", [HasV5TEOps]>;
281 def : ProcNoItin<"arm10e", [HasV5TEOps]>;
282 def : ProcNoItin<"arm1020e", [HasV5TEOps]>;
283 def : ProcNoItin<"arm1022e", [HasV5TEOps]>;
284 def : ProcNoItin<"xscale", [HasV5TEOps]>;
285 def : ProcNoItin<"iwmmxt", [HasV5TEOps]>;
288 def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>;
289 def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
290 FeatureHasSlowFPVMLx]>;
291 def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>;
292 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
293 FeatureHasSlowFPVMLx]>;
294 def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>;
295 def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
296 FeatureHasSlowFPVMLx]>;
299 def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6MOps, FeatureNoARM,
300 FeatureDB, FeatureMClass]>;
303 def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops,
305 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
306 FeatureHasSlowFPVMLx,
310 // FIXME: A5 has currently the same Schedule model as A8
311 def : ProcessorModel<"cortex-a5", CortexA8Model,
312 [ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
313 FeatureVFP4, FeatureDSPThumb2,
314 FeatureHasRAS, FeatureAClass]>;
315 def : ProcessorModel<"cortex-a7", CortexA8Model,
316 [ProcA7, HasV7Ops, FeatureNEON, FeatureDB,
317 FeatureDSPThumb2, FeatureHasRAS,
319 def : ProcessorModel<"cortex-a8", CortexA8Model,
320 [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
321 FeatureDSPThumb2, FeatureHasRAS,
323 def : ProcessorModel<"cortex-a9", CortexA9Model,
324 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
325 FeatureDSPThumb2, FeatureHasRAS,
327 def : ProcessorModel<"cortex-a9-mp", CortexA9Model,
328 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
329 FeatureDSPThumb2, FeatureMP,
330 FeatureHasRAS, FeatureAClass]>;
332 // FIXME: A12 has currently the same Schedule model as A9
333 def : ProcessorModel<"cortex-a12", CortexA9Model,
334 [ProcA12, HasV7Ops, FeatureNEON, FeatureDB,
335 FeatureDSPThumb2, FeatureMP,
336 FeatureHasRAS, FeatureAClass]>;
338 // FIXME: A15 has currently the same ProcessorModel as A9.
339 def : ProcessorModel<"cortex-a15", CortexA9Model,
340 [ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
341 FeatureDSPThumb2, FeatureHasRAS,
344 // FIXME: R5 has currently the same ProcessorModel as A8.
345 def : ProcessorModel<"cortex-r5", CortexA8Model,
346 [ProcR5, HasV7Ops, FeatureDB,
347 FeatureVFP3, FeatureDSPThumb2,
348 FeatureHasRAS, FeatureVFPOnlySP,
349 FeatureD16, FeatureRClass]>;
352 def : ProcNoItin<"cortex-m3", [HasV7Ops,
353 FeatureThumb2, FeatureNoARM, FeatureDB,
354 FeatureHWDiv, FeatureMClass]>;
357 def : ProcNoItin<"cortex-m4", [HasV7Ops,
358 FeatureThumb2, FeatureNoARM, FeatureDB,
359 FeatureHWDiv, FeatureDSPThumb2,
360 FeatureT2XtPk, FeatureVFP4,
361 FeatureVFPOnlySP, FeatureD16,
364 // Swift uArch Processors.
365 def : ProcessorModel<"swift", SwiftModel,
366 [ProcSwift, HasV7Ops, FeatureNEON,
367 FeatureDB, FeatureDSPThumb2,
368 FeatureHasRAS, FeatureAClass]>;
371 def : ProcNoItin<"cortex-a53", [ProcA53, HasV8Ops, FeatureAClass,
372 FeatureDB, FeatureFPARMv8,
373 FeatureNEON, FeatureDSPThumb2]>;
374 def : ProcNoItin<"cortex-a57", [ProcA57, HasV8Ops, FeatureAClass,
375 FeatureDB, FeatureFPARMv8,
376 FeatureNEON, FeatureDSPThumb2]>;
378 //===----------------------------------------------------------------------===//
379 // Register File Description
380 //===----------------------------------------------------------------------===//
382 include "ARMRegisterInfo.td"
384 include "ARMCallingConv.td"
386 //===----------------------------------------------------------------------===//
387 // Instruction Descriptions
388 //===----------------------------------------------------------------------===//
390 include "ARMInstrInfo.td"
392 def ARMInstrInfo : InstrInfo;
394 //===----------------------------------------------------------------------===//
395 // Declare the target which we are implementing
396 //===----------------------------------------------------------------------===//
399 // Pull in Instruction Info:
400 let InstructionSet = ARMInstrInfo;