lib/Target/ARM/ARM.td

   1 //===- ARM.td - Describe the ARM Target Machine -----------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // ARM Subtarget features.
  21 //
  22
  23 def ArchV4T     : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
  24                                    "ARM v4T">;
  25 def ArchV5T     : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
  26                                    "ARM v5T">;
  27 def ArchV5TE    : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
  28                                    "ARM v5TE, v5TEj, v5TExp">;
  29 def ArchV6      : SubtargetFeature<"v6", "ARMArchVersion", "V6",
  30                                    "ARM v6">;
  31 def ArchV7A     : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
  32                                    "ARM v7A">;
  33 def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
  34                                    "Enable VFP2 instructions ">;
  35 def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
  36                                    "Enable VFP3 instructions ">;
  37 def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
  38                                    "Enable NEON instructions ">;
  39
  40 //===----------------------------------------------------------------------===//
  41 // ARM Processors supported.
  42 //
  43
  44 class Proc<string Name, list<SubtargetFeature> Features>
  45  : Processor<Name, NoItineraries, Features>;
  46
  47 // V4 Processors.
  48 def : Proc<"generic",         []>;
  49 def : Proc<"arm8",            []>;
  50 def : Proc<"arm810",          []>;
  51 def : Proc<"strongarm",       []>;
  52 def : Proc<"strongarm110",    []>;
  53 def : Proc<"strongarm1100",   []>;
  54 def : Proc<"strongarm1110",   []>;
  55
  56 // V4T Processors.
  57 def : Proc<"arm7tdmi",        [ArchV4T]>;
  58 def : Proc<"arm7tdmi-s",      [ArchV4T]>;
  59 def : Proc<"arm710t",         [ArchV4T]>;
  60 def : Proc<"arm720t",         [ArchV4T]>;
  61 def : Proc<"arm9",            [ArchV4T]>;
  62 def : Proc<"arm9tdmi",        [ArchV4T]>;
  63 def : Proc<"arm920",          [ArchV4T]>;
  64 def : Proc<"arm920t",         [ArchV4T]>;
  65 def : Proc<"arm922t",         [ArchV4T]>;
  66 def : Proc<"arm940t",         [ArchV4T]>;
  67 def : Proc<"ep9312",          [ArchV4T]>;
  68
  69 // V5T Processors.
  70 def : Proc<"arm10tdmi",       [ArchV5T]>;
  71 def : Proc<"arm1020t",        [ArchV5T]>;
  72
  73 // V5TE Processors.
  74 def : Proc<"arm9e",           [ArchV5TE]>;
  75 def : Proc<"arm926ej-s",      [ArchV5TE]>;
  76 def : Proc<"arm946e-s",       [ArchV5TE]>;
  77 def : Proc<"arm966e-s",       [ArchV5TE]>;
  78 def : Proc<"arm968e-s",       [ArchV5TE]>;
  79 def : Proc<"arm10e",          [ArchV5TE]>;
  80 def : Proc<"arm1020e",        [ArchV5TE]>;
  81 def : Proc<"arm1022e",        [ArchV5TE]>;
  82 def : Proc<"xscale",          [ArchV5TE]>;
  83 def : Proc<"iwmmxt",          [ArchV5TE]>;
  84
  85 // V6 Processors.
  86 def : Proc<"arm1136j-s",      [ArchV6]>;
  87 def : Proc<"arm1136jf-s",     [ArchV6, FeatureVFP2]>;
  88 def : Proc<"arm1176jz-s",     [ArchV6]>;
  89 def : Proc<"arm1176jzf-s",    [ArchV6, FeatureVFP2]>;
  90 def : Proc<"mpcorenovfp",     [ArchV6]>;
  91 def : Proc<"mpcore",          [ArchV6, FeatureVFP2]>;
  92
  93 def : Proc<"cortex-a8",       [ArchV7A, FeatureNEON]>;
  94 def : Proc<"cortex-a9",       [ArchV7A, FeatureNEON]>;
  95
  96 //===----------------------------------------------------------------------===//
  97 // Register File Description
  98 //===----------------------------------------------------------------------===//
  99
 100 include "ARMRegisterInfo.td"
 101
 102 include "ARMCallingConv.td"
 103
 104 //===----------------------------------------------------------------------===//
 105 // Instruction Descriptions
 106 //===----------------------------------------------------------------------===//
 107
 108 include "ARMInstrInfo.td"
 109
 110 def ARMInstrInfo : InstrInfo {
 111   // Define how we want to layout our target-specific information field.
 112   let TSFlagsFields = ["AddrModeBits",
 113                        "SizeFlag",
 114                        "IndexModeBits",
 115                        "isUnaryDataProc",
 116                        "Form"];
 117   let TSFlagsShifts = [0,
 118                        4,
 119                        7,
 120                        9,
 121                        10];
 122 }
 123
 124 //===----------------------------------------------------------------------===//
 125 // Declare the target which we are implementing
 126 //===----------------------------------------------------------------------===//
 127
 128 def ARM : Target {
 129   // Pull in Instruction Info:
 130   let InstructionSet = ARMInstrInfo;
 131 }