1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // ARM Subtarget state.
23 def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
26 //===----------------------------------------------------------------------===//
27 // ARM Subtarget features.
30 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
31 "Enable VFP2 instructions">;
32 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
33 "Enable VFP3 instructions",
35 def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
36 "Enable VFP4 instructions",
38 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
39 "Enable NEON instructions",
41 def FeatureNEON2 : SubtargetFeature<"neon2", "HasNEON2", "true",
42 "Enable Advanced SIMD2 instructions",
44 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
45 "Enable Thumb2 instructions">;
46 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
47 "Does not support ARM mode execution">;
48 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
49 "Enable half-precision floating point">;
50 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
51 "Restrict VFP3 to 16 double registers">;
52 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
53 "Enable divide instructions">;
54 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
55 "Enable Thumb2 extract and pack instructions">;
56 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
57 "Has data barrier (dmb / dsb) instructions">;
58 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
59 "FP compare + branch is slow">;
60 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
61 "Floating point unit supports single precision only">;
63 // Some processors have FP multiply-accumulate instructions that don't
64 // play nicely with other VFP / NEON instructions, and it's generally better
65 // to just not use them.
66 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
67 "Disable VFP / NEON MAC instructions">;
69 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
70 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
71 "HasVMLxForwarding", "true",
72 "Has multiplier accumulator forwarding">;
74 // Some processors benefit from using NEON instructions for scalar
75 // single-precision FP operations.
76 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
78 "Use NEON for single precision FP">;
80 // Disable 32-bit to 16-bit narrowing for experimentation.
81 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
82 "Prefer 32-bit Thumb instrs">;
84 /// Some instructions update CPSR partially, which can add false dependency for
85 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
86 /// mapped to a separate physical register. Avoid partial CPSR update for these
88 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
89 "AvoidCPSRPartialUpdate", "true",
90 "Avoid CPSR partial update for OOO execution">;
92 // Some processors perform return stack prediction. CodeGen should avoid issue
93 // "normal" call instructions to callees which do not return.
94 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
95 "Has return address stack">;
97 /// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
98 def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
99 "Supports v7 DSP instructions in Thumb2">;
101 // Multiprocessing extension.
102 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
103 "Supports Multiprocessing extension">;
106 def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true",
107 "Is microcontroller profile ('M' series)">;
110 def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
111 "Support ARM v4T instructions">;
112 def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
113 "Support ARM v5T instructions",
115 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
116 "Support ARM v5TE, v5TEj, and v5TExp instructions",
118 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
119 "Support ARM v6 instructions",
121 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
122 "Support ARM v6t2 instructions",
123 [HasV6Ops, FeatureThumb2]>;
124 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
125 "Support ARM v7 instructions",
128 //===----------------------------------------------------------------------===//
129 // ARM Processors supported.
132 include "ARMSchedule.td"
134 // ARM processor families.
135 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
136 "Cortex-A8 ARM processors",
137 [FeatureSlowFPBrcc, FeatureNEONForFP,
138 FeatureHasSlowFPVMLx, FeatureVMLxForwarding,
140 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
141 "Cortex-A9 ARM processors",
142 [FeatureVMLxForwarding,
143 FeatureT2XtPk, FeatureFP16,
144 FeatureAvoidPartialCPSR]>;
146 class ProcNoItin<string Name, list<SubtargetFeature> Features>
147 : Processor<Name, GenericItineraries, Features>;
150 def : ProcNoItin<"generic", []>;
151 def : ProcNoItin<"arm8", []>;
152 def : ProcNoItin<"arm810", []>;
153 def : ProcNoItin<"strongarm", []>;
154 def : ProcNoItin<"strongarm110", []>;
155 def : ProcNoItin<"strongarm1100", []>;
156 def : ProcNoItin<"strongarm1110", []>;
159 def : ProcNoItin<"arm7tdmi", [HasV4TOps]>;
160 def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>;
161 def : ProcNoItin<"arm710t", [HasV4TOps]>;
162 def : ProcNoItin<"arm720t", [HasV4TOps]>;
163 def : ProcNoItin<"arm9", [HasV4TOps]>;
164 def : ProcNoItin<"arm9tdmi", [HasV4TOps]>;
165 def : ProcNoItin<"arm920", [HasV4TOps]>;
166 def : ProcNoItin<"arm920t", [HasV4TOps]>;
167 def : ProcNoItin<"arm922t", [HasV4TOps]>;
168 def : ProcNoItin<"arm940t", [HasV4TOps]>;
169 def : ProcNoItin<"ep9312", [HasV4TOps]>;
172 def : ProcNoItin<"arm10tdmi", [HasV5TOps]>;
173 def : ProcNoItin<"arm1020t", [HasV5TOps]>;
176 def : ProcNoItin<"arm9e", [HasV5TEOps]>;
177 def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>;
178 def : ProcNoItin<"arm946e-s", [HasV5TEOps]>;
179 def : ProcNoItin<"arm966e-s", [HasV5TEOps]>;
180 def : ProcNoItin<"arm968e-s", [HasV5TEOps]>;
181 def : ProcNoItin<"arm10e", [HasV5TEOps]>;
182 def : ProcNoItin<"arm1020e", [HasV5TEOps]>;
183 def : ProcNoItin<"arm1022e", [HasV5TEOps]>;
184 def : ProcNoItin<"xscale", [HasV5TEOps]>;
185 def : ProcNoItin<"iwmmxt", [HasV5TEOps]>;
188 def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>;
189 def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
190 FeatureHasSlowFPVMLx]>;
191 def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>;
192 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
193 FeatureHasSlowFPVMLx]>;
194 def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>;
195 def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
196 FeatureHasSlowFPVMLx]>;
199 def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
200 FeatureDB, FeatureMClass]>;
203 def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops,
205 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
206 FeatureHasSlowFPVMLx,
210 def : Processor<"cortex-a8", CortexA8Itineraries,
211 [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
212 FeatureDSPThumb2, FeatureHasRAS]>;
213 def : Processor<"cortex-a9", CortexA9Itineraries,
214 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
215 FeatureDSPThumb2, FeatureHasRAS]>;
216 def : Processor<"cortex-a9-mp", CortexA9Itineraries,
217 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
218 FeatureDSPThumb2, FeatureMP,
222 def : ProcNoItin<"cortex-m3", [HasV7Ops,
223 FeatureThumb2, FeatureNoARM, FeatureDB,
224 FeatureHWDiv, FeatureMClass]>;
227 def : ProcNoItin<"cortex-m4", [HasV7Ops,
228 FeatureThumb2, FeatureNoARM, FeatureDB,
229 FeatureHWDiv, FeatureDSPThumb2,
230 FeatureT2XtPk, FeatureVFP2,
231 FeatureVFPOnlySP, FeatureMClass]>;
233 //===----------------------------------------------------------------------===//
234 // Register File Description
235 //===----------------------------------------------------------------------===//
237 include "ARMRegisterInfo.td"
239 include "ARMCallingConv.td"
241 //===----------------------------------------------------------------------===//
242 // Instruction Descriptions
243 //===----------------------------------------------------------------------===//
245 include "ARMInstrInfo.td"
247 def ARMInstrInfo : InstrInfo;
250 //===----------------------------------------------------------------------===//
252 //===----------------------------------------------------------------------===//
253 // ARM Uses the MC printer for asm output, so make sure the TableGen
254 // AsmWriter bits get associated with the correct class.
255 def ARMAsmWriter : AsmWriter {
256 string AsmWriterClassName = "InstPrinter";
257 bit isMCAsmWriter = 1;
260 //===----------------------------------------------------------------------===//
261 // Declare the target which we are implementing
262 //===----------------------------------------------------------------------===//
265 // Pull in Instruction Info:
266 let InstructionSet = ARMInstrInfo;
268 let AssemblyWriters = [ARMAsmWriter];