1 //===- ARM.td - Describe the ARM Target Machine -----------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // ARM Subtarget features.
23 def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
24 "Enable VFP2 instructions">;
25 def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
26 "Enable VFP3 instructions">;
27 def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
28 "Enable NEON instructions">;
29 def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
30 "Enable Thumb2 instructions">;
31 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
32 "Enable half-precision floating point">;
33 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
34 "Enable divide instructions">;
35 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
36 "Enable Thumb2 extract and pack instructions">;
37 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
38 "Has data barrier (dmb / dsb) instructions">;
39 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
40 "FP compare + branch is slow">;
42 // Some processors have multiply-accumulate instructions that don't
43 // play nicely with other VFP instructions, and it's generally better
44 // to just not use them.
45 // FIXME: Currently, this is only flagged for Cortex-A8. It may be true for
46 // others as well. We should do more benchmarking and confirm one way or
48 def FeatureHasSlowVMLx : SubtargetFeature<"vmlx", "SlowVMLx", "true",
49 "Disable VFP MAC instructions">;
50 // Some processors benefit from using NEON instructions for scalar
51 // single-precision FP operations.
52 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
54 "Use NEON for single precision FP">;
56 // Disable 32-bit to 16-bit narrowing for experimentation.
57 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
58 "Prefer 32-bit Thumb instrs">;
62 def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
64 def ArchV5T : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
66 def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
67 "ARM v5TE, v5TEj, v5TExp">;
68 def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6",
70 def ArchV6M : SubtargetFeature<"v6m", "ARMArchVersion", "V6M",
73 def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
75 def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
78 def ArchV7M : SubtargetFeature<"v7m", "ARMArchVersion", "V7M",
82 //===----------------------------------------------------------------------===//
83 // ARM Processors supported.
86 include "ARMSchedule.td"
88 class ProcNoItin<string Name, list<SubtargetFeature> Features>
89 : Processor<Name, GenericItineraries, Features>;
92 def : ProcNoItin<"generic", []>;
93 def : ProcNoItin<"arm8", []>;
94 def : ProcNoItin<"arm810", []>;
95 def : ProcNoItin<"strongarm", []>;
96 def : ProcNoItin<"strongarm110", []>;
97 def : ProcNoItin<"strongarm1100", []>;
98 def : ProcNoItin<"strongarm1110", []>;
101 def : ProcNoItin<"arm7tdmi", [ArchV4T]>;
102 def : ProcNoItin<"arm7tdmi-s", [ArchV4T]>;
103 def : ProcNoItin<"arm710t", [ArchV4T]>;
104 def : ProcNoItin<"arm720t", [ArchV4T]>;
105 def : ProcNoItin<"arm9", [ArchV4T]>;
106 def : ProcNoItin<"arm9tdmi", [ArchV4T]>;
107 def : ProcNoItin<"arm920", [ArchV4T]>;
108 def : ProcNoItin<"arm920t", [ArchV4T]>;
109 def : ProcNoItin<"arm922t", [ArchV4T]>;
110 def : ProcNoItin<"arm940t", [ArchV4T]>;
111 def : ProcNoItin<"ep9312", [ArchV4T]>;
114 def : ProcNoItin<"arm10tdmi", [ArchV5T]>;
115 def : ProcNoItin<"arm1020t", [ArchV5T]>;
118 def : ProcNoItin<"arm9e", [ArchV5TE]>;
119 def : ProcNoItin<"arm926ej-s", [ArchV5TE]>;
120 def : ProcNoItin<"arm946e-s", [ArchV5TE]>;
121 def : ProcNoItin<"arm966e-s", [ArchV5TE]>;
122 def : ProcNoItin<"arm968e-s", [ArchV5TE]>;
123 def : ProcNoItin<"arm10e", [ArchV5TE]>;
124 def : ProcNoItin<"arm1020e", [ArchV5TE]>;
125 def : ProcNoItin<"arm1022e", [ArchV5TE]>;
126 def : ProcNoItin<"xscale", [ArchV5TE]>;
127 def : ProcNoItin<"iwmmxt", [ArchV5TE]>;
130 def : Processor<"arm1136j-s", ARMV6Itineraries, [ArchV6]>;
131 def : Processor<"arm1136jf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2,
132 FeatureHasSlowVMLx]>;
133 def : Processor<"arm1176jz-s", ARMV6Itineraries, [ArchV6]>;
134 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
135 def : Processor<"mpcorenovfp", ARMV6Itineraries, [ArchV6]>;
136 def : Processor<"mpcore", ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
139 def : Processor<"cortex-m0", ARMV6Itineraries, [ArchV6M]>;
142 def : Processor<"arm1156t2-s", ARMV6Itineraries,
143 [ArchV6T2, FeatureThumb2]>;
144 def : Processor<"arm1156t2f-s", ARMV6Itineraries,
145 [ArchV6T2, FeatureThumb2, FeatureVFP2]>;
148 def : Processor<"cortex-a8", CortexA8Itineraries,
149 [ArchV7A, FeatureThumb2, FeatureNEON, FeatureHasSlowVMLx,
150 FeatureSlowFPBrcc, FeatureNEONForFP, FeatureT2XtPk]>;
151 def : Processor<"cortex-a9", CortexA9Itineraries,
152 [ArchV7A, FeatureThumb2, FeatureNEON, FeatureT2XtPk]>;
155 def : ProcNoItin<"cortex-m3", [ArchV7M, FeatureThumb2, FeatureHWDiv]>;
156 def : ProcNoItin<"cortex-m4", [ArchV7M, FeatureThumb2, FeatureHWDiv]>;
158 //===----------------------------------------------------------------------===//
159 // Register File Description
160 //===----------------------------------------------------------------------===//
162 include "ARMRegisterInfo.td"
164 include "ARMCallingConv.td"
166 //===----------------------------------------------------------------------===//
167 // Instruction Descriptions
168 //===----------------------------------------------------------------------===//
170 include "ARMInstrInfo.td"
172 def ARMInstrInfo : InstrInfo;
174 //===----------------------------------------------------------------------===//
175 // Declare the target which we are implementing
176 //===----------------------------------------------------------------------===//
179 // Pull in Instruction Info:
180 let InstructionSet = ARMInstrInfo;