1 //===- ARMAddressingModes.h - ARM Addressing Modes --------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM addressing mode implementation stuff.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
15 #define LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
17 #include "llvm/CodeGen/SelectionDAGNodes.h"
18 #include "llvm/Support/MathExtras.h"
23 /// ARM_AM - ARM Addressing Mode Stuff
38 static inline const char *getShiftOpcStr(ShiftOpc Op) {
40 default: assert(0 && "Unknown shift opc!");
41 case ARM_AM::asr: return "asr";
42 case ARM_AM::lsl: return "lsl";
43 case ARM_AM::lsr: return "lsr";
44 case ARM_AM::ror: return "ror";
45 case ARM_AM::rrx: return "rrx";
49 static inline ShiftOpc getShiftOpcForNode(SDValue N) {
50 switch (N.getOpcode()) {
51 default: return ARM_AM::no_shift;
52 case ISD::SHL: return ARM_AM::lsl;
53 case ISD::SRL: return ARM_AM::lsr;
54 case ISD::SRA: return ARM_AM::asr;
55 case ISD::ROTR: return ARM_AM::ror;
56 //case ISD::ROTL: // Only if imm -> turn into ROTR.
57 // Can't handle RRX here, because it would require folding a flag into
58 // the addressing mode. :( This causes us to miss certain things.
59 //case ARMISD::RRX: return ARM_AM::rrx;
71 static inline const char *getAMSubModeStr(AMSubMode Mode) {
73 default: assert(0 && "Unknown addressing sub-mode!");
74 case ARM_AM::ia: return "ia";
75 case ARM_AM::ib: return "ib";
76 case ARM_AM::da: return "da";
77 case ARM_AM::db: return "db";
81 static inline const char *getAMSubModeAltStr(AMSubMode Mode, bool isLD) {
83 default: assert(0 && "Unknown addressing sub-mode!");
84 case ARM_AM::ia: return isLD ? "fd" : "ea";
85 case ARM_AM::ib: return isLD ? "ed" : "fa";
86 case ARM_AM::da: return isLD ? "fa" : "ed";
87 case ARM_AM::db: return isLD ? "ea" : "fd";
91 /// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
93 static inline unsigned rotr32(unsigned Val, unsigned Amt) {
94 assert(Amt < 32 && "Invalid rotate amount");
95 return (Val >> Amt) | (Val << ((32-Amt)&31));
98 /// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits.
100 static inline unsigned rotl32(unsigned Val, unsigned Amt) {
101 assert(Amt < 32 && "Invalid rotate amount");
102 return (Val << Amt) | (Val >> ((32-Amt)&31));
105 //===--------------------------------------------------------------------===//
106 // Addressing Mode #1: shift_operand with registers
107 //===--------------------------------------------------------------------===//
109 // This 'addressing mode' is used for arithmetic instructions. It can
110 // represent things like:
112 // reg [asr|lsl|lsr|ror|rrx] reg
113 // reg [asr|lsl|lsr|ror|rrx] imm
115 // This is stored three operands [rega, regb, opc]. The first is the base
116 // reg, the second is the shift amount (or reg0 if not present or imm). The
117 // third operand encodes the shift opcode and the imm if a reg isn't present.
119 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
120 return ShOp | (Imm << 3);
122 static inline unsigned getSORegOffset(unsigned Op) {
125 static inline ShiftOpc getSORegShOp(unsigned Op) {
126 return (ShiftOpc)(Op & 7);
129 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
130 /// the 8-bit imm value.
131 static inline unsigned getSOImmValImm(unsigned Imm) {
134 /// getSOImmValRot - Given an encoded imm field for the reg/imm form, return
135 /// the rotate amount.
136 static inline unsigned getSOImmValRot(unsigned Imm) {
137 return (Imm >> 8) * 2;
140 /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand,
141 /// computing the rotate amount to use. If this immediate value cannot be
142 /// handled with a single shifter-op, determine a good rotate amount that will
143 /// take a maximal chunk of bits out of the immediate.
144 static inline unsigned getSOImmValRotate(unsigned Imm) {
145 // 8-bit (or less) immediates are trivially shifter_operands with a rotate
147 if ((Imm & ~255U) == 0) return 0;
149 // Use CTZ to compute the rotate amount.
150 unsigned TZ = CountTrailingZeros_32(Imm);
152 // Rotate amount must be even. Something like 0x200 must be rotated 8 bits,
154 unsigned RotAmt = TZ & ~1;
156 // If we can handle this spread, return it.
157 if ((rotr32(Imm, RotAmt) & ~255U) == 0)
158 return (32-RotAmt)&31; // HW rotates right, not left.
160 // For values like 0xF000000F, we should skip the first run of ones, then
163 unsigned TrailingOnes = CountTrailingZeros_32(~Imm);
164 if (TrailingOnes != 32) { // Avoid overflow on 0xFFFFFFFF
165 // Restart the search for a high-order bit after the initial seconds of
167 unsigned TZ2 = CountTrailingZeros_32(Imm & ~((1 << TrailingOnes)-1));
169 // Rotate amount must be even.
170 unsigned RotAmt2 = TZ2 & ~1;
172 // If this fits, use it.
173 if (RotAmt2 != 32 && (rotr32(Imm, RotAmt2) & ~255U) == 0)
174 return (32-RotAmt2)&31; // HW rotates right, not left.
178 // Otherwise, we have no way to cover this span of bits with a single
179 // shifter_op immediate. Return a chunk of bits that will be useful to
181 return (32-RotAmt)&31; // HW rotates right, not left.
184 /// getSOImmVal - Given a 32-bit immediate, if it is something that can fit
185 /// into an shifter_operand immediate operand, return the 12-bit encoding for
186 /// it. If not, return -1.
187 static inline int getSOImmVal(unsigned Arg) {
188 // 8-bit (or less) immediates are trivially shifter_operands with a rotate
190 if ((Arg & ~255U) == 0) return Arg;
192 unsigned RotAmt = getSOImmValRotate(Arg);
194 // If this cannot be handled with a single shifter_op, bail out.
195 if (rotr32(~255U, RotAmt) & Arg)
198 // Encode this correctly.
199 return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8);
202 /// isSOImmTwoPartVal - Return true if the specified value can be obtained by
203 /// or'ing together two SOImmVal's.
204 static inline bool isSOImmTwoPartVal(unsigned V) {
205 // If this can be handled with a single shifter_op, bail out.
206 V = rotr32(~255U, getSOImmValRotate(V)) & V;
210 // If this can be handled with two shifter_op's, accept.
211 V = rotr32(~255U, getSOImmValRotate(V)) & V;
215 /// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal,
216 /// return the first chunk of it.
217 static inline unsigned getSOImmTwoPartFirst(unsigned V) {
218 return rotr32(255U, getSOImmValRotate(V)) & V;
221 /// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal,
222 /// return the second chunk of it.
223 static inline unsigned getSOImmTwoPartSecond(unsigned V) {
224 // Mask out the first hunk.
225 V = rotr32(~255U, getSOImmValRotate(V)) & V;
228 assert(V == (rotr32(255U, getSOImmValRotate(V)) & V));
232 /// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed
233 /// by a left shift. Returns the shift amount to use.
234 static inline unsigned getThumbImmValShift(unsigned Imm) {
235 // 8-bit (or less) immediates are trivially immediate operand with a shift
237 if ((Imm & ~255U) == 0) return 0;
239 // Use CTZ to compute the shift amount.
240 return CountTrailingZeros_32(Imm);
243 /// isThumbImmShiftedVal - Return true if the specified value can be obtained
244 /// by left shifting a 8-bit immediate.
245 static inline bool isThumbImmShiftedVal(unsigned V) {
246 // If this can be handled with
247 V = (~255U << getThumbImmValShift(V)) & V;
251 /// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed
252 /// by a left shift. Returns the shift amount to use.
253 static inline unsigned getThumbImm16ValShift(unsigned Imm) {
254 // 16-bit (or less) immediates are trivially immediate operand with a shift
256 if ((Imm & ~65535U) == 0) return 0;
258 // Use CTZ to compute the shift amount.
259 return CountTrailingZeros_32(Imm);
262 /// isThumbImm16ShiftedVal - Return true if the specified value can be
263 /// obtained by left shifting a 16-bit immediate.
264 static inline bool isThumbImm16ShiftedVal(unsigned V) {
265 // If this can be handled with
266 V = (~65535U << getThumbImm16ValShift(V)) & V;
270 /// getThumbImmNonShiftedVal - If V is a value that satisfies
271 /// isThumbImmShiftedVal, return the non-shiftd value.
272 static inline unsigned getThumbImmNonShiftedVal(unsigned V) {
273 return V >> getThumbImmValShift(V);
277 /// getT2SOImmValSplat - Return the 12-bit encoded representation
278 /// if the specified value can be obtained by splatting the low 8 bits
279 /// into every other byte or every byte of a 32-bit value. i.e.,
280 /// 00000000 00000000 00000000 abcdefgh control = 0
281 /// 00000000 abcdefgh 00000000 abcdefgh control = 1
282 /// abcdefgh 00000000 abcdefgh 00000000 control = 2
283 /// abcdefgh abcdefgh abcdefgh abcdefgh control = 3
284 /// Return -1 if none of the above apply.
285 /// See ARM Reference Manual A6.3.2.
286 static inline int getT2SOImmValSplatVal(unsigned V) {
289 if ((V & 0xffffff00) == 0)
292 // If the value is zeroes in the first byte, just shift those off
293 Vs = ((V & 0xff) == 0) ? V >> 8 : V;
294 // Any passing value only has 8 bits of payload, splatted across the word
296 // Likewise, any passing values have the payload splatted into the 3rd byte
297 u = Imm | (Imm << 16);
301 return (((Vs == V) ? 1 : 2) << 8) | Imm;
304 if (Vs == (u | (u << 8)))
305 return (3 << 8) | Imm;
310 /// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the
311 /// specified value is a rotated 8-bit value. Return -1 if no rotation
312 /// encoding is possible.
313 /// See ARM Reference Manual A6.3.2.
314 static inline int getT2SOImmValRotateVal(unsigned V) {
315 unsigned RotAmt = CountLeadingZeros_32(V);
319 // If 'Arg' can be handled with a single shifter_op return the value.
320 if ((rotr32(0xff000000U, RotAmt) & V) == V)
321 return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7);
326 /// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit
327 /// into a Thumb-2 shifter_operand immediate operand, return the 12-bit
328 /// encoding for it. If not, return -1.
329 /// See ARM Reference Manual A6.3.2.
330 static inline int getT2SOImmVal(unsigned Arg) {
331 // If 'Arg' is an 8-bit splat, then get the encoded value.
332 int Splat = getT2SOImmValSplatVal(Arg);
336 // If 'Arg' can be handled with a single shifter_op return the value.
337 int Rot = getT2SOImmValRotateVal(Arg);
344 static inline unsigned getT2SOImmValRotate(unsigned V) {
345 if ((V & ~255U) == 0) return 0;
346 // Use CTZ to compute the rotate amount.
347 unsigned RotAmt = CountTrailingZeros_32(V);
348 return (32 - RotAmt) & 31;
351 static inline bool isT2SOImmTwoPartVal (unsigned Imm) {
353 // Passing values can be any combination of splat values and shifter
354 // values. If this can be handled with a single shifter or splat, bail
355 // out. Those should be handled directly, not with a two-part val.
356 if (getT2SOImmValSplatVal(V) != -1)
358 V = rotr32 (~255U, getT2SOImmValRotate(V)) & V;
362 // If this can be handled as an immediate, accept.
363 if (getT2SOImmVal(V) != -1) return true;
365 // Likewise, try masking out a splat value first.
367 if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
369 else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
371 // If what's left can be handled as an immediate, accept.
372 if (getT2SOImmVal(V) != -1) return true;
374 // Otherwise, do not accept.
378 static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm) {
379 assert (isT2SOImmTwoPartVal(Imm) &&
380 "Immedate cannot be encoded as two part immediate!");
381 // Try a shifter operand as one part
382 unsigned V = rotr32 (~255, getT2SOImmValRotate(Imm)) & Imm;
383 // If the rest is encodable as an immediate, then return it.
384 if (getT2SOImmVal(V) != -1) return V;
386 // Try masking out a splat value first.
387 if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
388 return Imm & 0xff00ff00U;
390 // The other splat is all that's left as an option.
391 assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1);
392 return Imm & 0x00ff00ffU;
395 static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) {
396 // Mask out the first hunk
397 Imm ^= getT2SOImmTwoPartFirst(Imm);
398 // Return what's left
399 assert (getT2SOImmVal(Imm) != -1 &&
400 "Unable to encode second part of T2 two part SO immediate");
405 //===--------------------------------------------------------------------===//
406 // Addressing Mode #2
407 //===--------------------------------------------------------------------===//
409 // This is used for most simple load/store instructions.
411 // addrmode2 := reg +/- reg shop imm
412 // addrmode2 := reg +/- imm12
414 // The first operand is always a Reg. The second operand is a reg if in
415 // reg/reg form, otherwise it's reg#0. The third field encodes the operation
416 // in bit 12, the immediate in bits 0-11, and the shift op in 13-15.
418 // If this addressing mode is a frame index (before prolog/epilog insertion
419 // and code rewriting), this operand will have the form: FI#, reg0, <offs>
420 // with no shift amount for the frame offset.
422 static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO) {
423 assert(Imm12 < (1 << 12) && "Imm too large!");
424 bool isSub = Opc == sub;
425 return Imm12 | ((int)isSub << 12) | (SO << 13);
427 static inline unsigned getAM2Offset(unsigned AM2Opc) {
428 return AM2Opc & ((1 << 12)-1);
430 static inline AddrOpc getAM2Op(unsigned AM2Opc) {
431 return ((AM2Opc >> 12) & 1) ? sub : add;
433 static inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) {
434 return (ShiftOpc)(AM2Opc >> 13);
438 //===--------------------------------------------------------------------===//
439 // Addressing Mode #3
440 //===--------------------------------------------------------------------===//
442 // This is used for sign-extending loads, and load/store-pair instructions.
444 // addrmode3 := reg +/- reg
445 // addrmode3 := reg +/- imm8
447 // The first operand is always a Reg. The second operand is a reg if in
448 // reg/reg form, otherwise it's reg#0. The third field encodes the operation
449 // in bit 8, the immediate in bits 0-7.
451 /// getAM3Opc - This function encodes the addrmode3 opc field.
452 static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset) {
453 bool isSub = Opc == sub;
454 return ((int)isSub << 8) | Offset;
456 static inline unsigned char getAM3Offset(unsigned AM3Opc) {
457 return AM3Opc & 0xFF;
459 static inline AddrOpc getAM3Op(unsigned AM3Opc) {
460 return ((AM3Opc >> 8) & 1) ? sub : add;
463 //===--------------------------------------------------------------------===//
464 // Addressing Mode #4
465 //===--------------------------------------------------------------------===//
467 // This is used for load / store multiple instructions.
469 // addrmode4 := reg, <mode>
471 // The four modes are:
472 // IA - Increment after
473 // IB - Increment before
474 // DA - Decrement after
475 // DB - Decrement before
477 // If the 4th bit (writeback)is set, then the base register is updated after
478 // the memory transfer.
480 static inline AMSubMode getAM4SubMode(unsigned Mode) {
481 return (AMSubMode)(Mode & 0x7);
484 static inline unsigned getAM4ModeImm(AMSubMode SubMode, bool WB = false) {
485 return (int)SubMode | ((int)WB << 3);
488 static inline bool getAM4WBFlag(unsigned Mode) {
489 return (Mode >> 3) & 1;
492 //===--------------------------------------------------------------------===//
493 // Addressing Mode #5
494 //===--------------------------------------------------------------------===//
496 // This is used for coprocessor instructions, such as FP load/stores.
498 // addrmode5 := reg +/- imm8*4
500 // The first operand is always a Reg. The second operand encodes the
501 // operation in bit 8 and the immediate in bits 0-7.
503 // This is also used for FP load/store multiple ops. The second operand
504 // encodes the writeback mode in bit 8 and the number of registers (or 2
505 // times the number of registers for DPR ops) in bits 0-7. In addition,
506 // bits 9-11 encode one of the following two sub-modes:
508 // IA - Increment after
509 // DB - Decrement before
511 /// getAM5Opc - This function encodes the addrmode5 opc field.
512 static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) {
513 bool isSub = Opc == sub;
514 return ((int)isSub << 8) | Offset;
516 static inline unsigned char getAM5Offset(unsigned AM5Opc) {
517 return AM5Opc & 0xFF;
519 static inline AddrOpc getAM5Op(unsigned AM5Opc) {
520 return ((AM5Opc >> 8) & 1) ? sub : add;
523 /// getAM5Opc - This function encodes the addrmode5 opc field for FLDM and
524 /// FSTM instructions.
525 static inline unsigned getAM5Opc(AMSubMode SubMode, bool WB,
526 unsigned char Offset) {
527 assert((SubMode == ia || SubMode == db) &&
528 "Illegal addressing mode 5 sub-mode!");
529 return ((int)SubMode << 9) | ((int)WB << 8) | Offset;
531 static inline AMSubMode getAM5SubMode(unsigned AM5Opc) {
532 return (AMSubMode)((AM5Opc >> 9) & 0x7);
534 static inline bool getAM5WBFlag(unsigned AM5Opc) {
535 return ((AM5Opc >> 8) & 1);
538 //===--------------------------------------------------------------------===//
539 // Addressing Mode #6
540 //===--------------------------------------------------------------------===//
542 // This is used for NEON load / store instructions.
544 // addrmode6 := reg with optional writeback and alignment
546 // This is stored in four operands [regaddr, regupdate, opc, align]. The
547 // first is the address register. The second register holds the value of
548 // a post-access increment for writeback or reg0 if no writeback or if the
549 // writeback increment is the size of the memory access. The third
550 // operand encodes whether there is writeback to the address register. The
551 // fourth operand is the value of the alignment specifier to use or zero if
552 // no explicit alignment.
554 static inline unsigned getAM6Opc(bool WB = false) {
558 static inline bool getAM6WBFlag(unsigned Mode) {
562 } // end namespace ARM_AM
563 } // end namespace llvm