1 //===- ARMAddressingModes.h - ARM Addressing Modes --------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM addressing mode implementation stuff.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
15 #define LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
17 #include "llvm/CodeGen/SelectionDAGNodes.h"
18 #include "llvm/Support/MathExtras.h"
23 /// ARM_AM - ARM Addressing Mode Stuff
38 static inline const char *getAddrOpcStr(AddrOpc Op) {
39 return Op == sub ? "-" : "";
42 static inline const char *getShiftOpcStr(ShiftOpc Op) {
44 default: assert(0 && "Unknown shift opc!");
45 case ARM_AM::asr: return "asr";
46 case ARM_AM::lsl: return "lsl";
47 case ARM_AM::lsr: return "lsr";
48 case ARM_AM::ror: return "ror";
49 case ARM_AM::rrx: return "rrx";
53 static inline ShiftOpc getShiftOpcForNode(SDValue N) {
54 switch (N.getOpcode()) {
55 default: return ARM_AM::no_shift;
56 case ISD::SHL: return ARM_AM::lsl;
57 case ISD::SRL: return ARM_AM::lsr;
58 case ISD::SRA: return ARM_AM::asr;
59 case ISD::ROTR: return ARM_AM::ror;
60 //case ISD::ROTL: // Only if imm -> turn into ROTR.
61 // Can't handle RRX here, because it would require folding a flag into
62 // the addressing mode. :( This causes us to miss certain things.
63 //case ARMISD::RRX: return ARM_AM::rrx;
75 static inline const char *getAMSubModeStr(AMSubMode Mode) {
77 default: assert(0 && "Unknown addressing sub-mode!");
78 case ARM_AM::ia: return "ia";
79 case ARM_AM::ib: return "ib";
80 case ARM_AM::da: return "da";
81 case ARM_AM::db: return "db";
85 /// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
87 static inline unsigned rotr32(unsigned Val, unsigned Amt) {
88 assert(Amt < 32 && "Invalid rotate amount");
89 return (Val >> Amt) | (Val << ((32-Amt)&31));
92 /// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits.
94 static inline unsigned rotl32(unsigned Val, unsigned Amt) {
95 assert(Amt < 32 && "Invalid rotate amount");
96 return (Val << Amt) | (Val >> ((32-Amt)&31));
99 //===--------------------------------------------------------------------===//
100 // Addressing Mode #1: shift_operand with registers
101 //===--------------------------------------------------------------------===//
103 // This 'addressing mode' is used for arithmetic instructions. It can
104 // represent things like:
106 // reg [asr|lsl|lsr|ror|rrx] reg
107 // reg [asr|lsl|lsr|ror|rrx] imm
109 // This is stored three operands [rega, regb, opc]. The first is the base
110 // reg, the second is the shift amount (or reg0 if not present or imm). The
111 // third operand encodes the shift opcode and the imm if a reg isn't present.
113 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
114 return ShOp | (Imm << 3);
116 static inline unsigned getSORegOffset(unsigned Op) {
119 static inline ShiftOpc getSORegShOp(unsigned Op) {
120 return (ShiftOpc)(Op & 7);
123 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
124 /// the 8-bit imm value.
125 static inline unsigned getSOImmValImm(unsigned Imm) {
128 /// getSOImmValRot - Given an encoded imm field for the reg/imm form, return
129 /// the rotate amount.
130 static inline unsigned getSOImmValRot(unsigned Imm) {
131 return (Imm >> 8) * 2;
134 /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand,
135 /// computing the rotate amount to use. If this immediate value cannot be
136 /// handled with a single shifter-op, determine a good rotate amount that will
137 /// take a maximal chunk of bits out of the immediate.
138 static inline unsigned getSOImmValRotate(unsigned Imm) {
139 // 8-bit (or less) immediates are trivially shifter_operands with a rotate
141 if ((Imm & ~255U) == 0) return 0;
143 // Use CTZ to compute the rotate amount.
144 unsigned TZ = CountTrailingZeros_32(Imm);
146 // Rotate amount must be even. Something like 0x200 must be rotated 8 bits,
148 unsigned RotAmt = TZ & ~1;
150 // If we can handle this spread, return it.
151 if ((rotr32(Imm, RotAmt) & ~255U) == 0)
152 return (32-RotAmt)&31; // HW rotates right, not left.
154 // For values like 0xF000000F, we should ignore the low 6 bits, then
157 unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U);
158 unsigned RotAmt2 = TZ2 & ~1;
159 if ((rotr32(Imm, RotAmt2) & ~255U) == 0)
160 return (32-RotAmt2)&31; // HW rotates right, not left.
163 // Otherwise, we have no way to cover this span of bits with a single
164 // shifter_op immediate. Return a chunk of bits that will be useful to
166 return (32-RotAmt)&31; // HW rotates right, not left.
169 /// getSOImmVal - Given a 32-bit immediate, if it is something that can fit
170 /// into an shifter_operand immediate operand, return the 12-bit encoding for
171 /// it. If not, return -1.
172 static inline int getSOImmVal(unsigned Arg) {
173 // 8-bit (or less) immediates are trivially shifter_operands with a rotate
175 if ((Arg & ~255U) == 0) return Arg;
177 unsigned RotAmt = getSOImmValRotate(Arg);
179 // If this cannot be handled with a single shifter_op, bail out.
180 if (rotr32(~255U, RotAmt) & Arg)
183 // Encode this correctly.
184 return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8);
187 /// isSOImmTwoPartVal - Return true if the specified value can be obtained by
188 /// or'ing together two SOImmVal's.
189 static inline bool isSOImmTwoPartVal(unsigned V) {
190 // If this can be handled with a single shifter_op, bail out.
191 V = rotr32(~255U, getSOImmValRotate(V)) & V;
195 // If this can be handled with two shifter_op's, accept.
196 V = rotr32(~255U, getSOImmValRotate(V)) & V;
200 /// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal,
201 /// return the first chunk of it.
202 static inline unsigned getSOImmTwoPartFirst(unsigned V) {
203 return rotr32(255U, getSOImmValRotate(V)) & V;
206 /// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal,
207 /// return the second chunk of it.
208 static inline unsigned getSOImmTwoPartSecond(unsigned V) {
209 // Mask out the first hunk.
210 V = rotr32(~255U, getSOImmValRotate(V)) & V;
213 assert(V == (rotr32(255U, getSOImmValRotate(V)) & V));
217 /// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed
218 /// by a left shift. Returns the shift amount to use.
219 static inline unsigned getThumbImmValShift(unsigned Imm) {
220 // 8-bit (or less) immediates are trivially immediate operand with a shift
222 if ((Imm & ~255U) == 0) return 0;
224 // Use CTZ to compute the shift amount.
225 return CountTrailingZeros_32(Imm);
228 /// isThumbImmShiftedVal - Return true if the specified value can be obtained
229 /// by left shifting a 8-bit immediate.
230 static inline bool isThumbImmShiftedVal(unsigned V) {
231 // If this can be handled with
232 V = (~255U << getThumbImmValShift(V)) & V;
236 /// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed
237 /// by a left shift. Returns the shift amount to use.
238 static inline unsigned getThumbImm16ValShift(unsigned Imm) {
239 // 16-bit (or less) immediates are trivially immediate operand with a shift
241 if ((Imm & ~65535U) == 0) return 0;
243 // Use CTZ to compute the shift amount.
244 return CountTrailingZeros_32(Imm);
247 /// isThumbImm16ShiftedVal - Return true if the specified value can be
248 /// obtained by left shifting a 16-bit immediate.
249 static inline bool isThumbImm16ShiftedVal(unsigned V) {
250 // If this can be handled with
251 V = (~65535U << getThumbImm16ValShift(V)) & V;
255 /// getThumbImmNonShiftedVal - If V is a value that satisfies
256 /// isThumbImmShiftedVal, return the non-shiftd value.
257 static inline unsigned getThumbImmNonShiftedVal(unsigned V) {
258 return V >> getThumbImmValShift(V);
262 /// getT2SOImmValSplat - Return the 12-bit encoded representation
263 /// if the specified value can be obtained by splatting the low 8 bits
264 /// into every other byte or every byte of a 32-bit value. i.e.,
265 /// 00000000 00000000 00000000 abcdefgh control = 0
266 /// 00000000 abcdefgh 00000000 abcdefgh control = 1
267 /// abcdefgh 00000000 abcdefgh 00000000 control = 2
268 /// abcdefgh abcdefgh abcdefgh abcdefgh control = 3
269 /// Return -1 if none of the above apply.
270 /// See ARM Reference Manual A6.3.2.
271 static inline int getT2SOImmValSplatVal(unsigned V) {
274 if ((V & 0xffffff00) == 0)
277 // If the value is zeroes in the first byte, just shift those off
278 Vs = ((V & 0xff) == 0) ? V >> 8 : V;
279 // Any passing value only has 8 bits of payload, splatted across the word
281 // Likewise, any passing values have the payload splatted into the 3rd byte
282 u = Imm | (Imm << 16);
286 return (((Vs == V) ? 1 : 2) << 8) | Imm;
289 if (Vs == (u | (u << 8)))
290 return (3 << 8) | Imm;
295 /// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the
296 /// specified value is a rotated 8-bit value. Return -1 if no rotation
297 /// encoding is possible.
298 /// See ARM Reference Manual A6.3.2.
299 static inline int getT2SOImmValRotateVal(unsigned V) {
300 unsigned RotAmt = CountLeadingZeros_32(V);
304 // If 'Arg' can be handled with a single shifter_op return the value.
305 if ((rotr32(0xff000000U, RotAmt) & V) == V)
306 return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7);
311 /// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit
312 /// into a Thumb-2 shifter_operand immediate operand, return the 12-bit
313 /// encoding for it. If not, return -1.
314 /// See ARM Reference Manual A6.3.2.
315 static inline int getT2SOImmVal(unsigned Arg) {
316 // If 'Arg' is an 8-bit splat, then get the encoded value.
317 int Splat = getT2SOImmValSplatVal(Arg);
321 // If 'Arg' can be handled with a single shifter_op return the value.
322 int Rot = getT2SOImmValRotateVal(Arg);
329 static inline unsigned getT2SOImmValRotate(unsigned V) {
330 if ((V & ~255U) == 0) return 0;
331 // Use CTZ to compute the rotate amount.
332 unsigned RotAmt = CountTrailingZeros_32(V);
333 return (32 - RotAmt) & 31;
336 static inline bool isT2SOImmTwoPartVal (unsigned Imm) {
338 // Passing values can be any combination of splat values and shifter
339 // values. If this can be handled with a single shifter or splat, bail
340 // out. Those should be handled directly, not with a two-part val.
341 if (getT2SOImmValSplatVal(V) != -1)
343 V = rotr32 (~255U, getT2SOImmValRotate(V)) & V;
347 // If this can be handled as an immediate, accept.
348 if (getT2SOImmVal(V) != -1) return true;
350 // Likewise, try masking out a splat value first.
352 if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
354 else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
356 // If what's left can be handled as an immediate, accept.
357 if (getT2SOImmVal(V) != -1) return true;
359 // Otherwise, do not accept.
363 static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm) {
364 assert (isT2SOImmTwoPartVal(Imm) &&
365 "Immedate cannot be encoded as two part immediate!");
366 // Try a shifter operand as one part
367 unsigned V = rotr32 (~255, getT2SOImmValRotate(Imm)) & Imm;
368 // If the rest is encodable as an immediate, then return it.
369 if (getT2SOImmVal(V) != -1) return V;
371 // Try masking out a splat value first.
372 if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
373 return Imm & 0xff00ff00U;
375 // The other splat is all that's left as an option.
376 assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1);
377 return Imm & 0x00ff00ffU;
380 static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) {
381 // Mask out the first hunk
382 Imm ^= getT2SOImmTwoPartFirst(Imm);
383 // Return what's left
384 assert (getT2SOImmVal(Imm) != -1 &&
385 "Unable to encode second part of T2 two part SO immediate");
390 //===--------------------------------------------------------------------===//
391 // Addressing Mode #2
392 //===--------------------------------------------------------------------===//
394 // This is used for most simple load/store instructions.
396 // addrmode2 := reg +/- reg shop imm
397 // addrmode2 := reg +/- imm12
399 // The first operand is always a Reg. The second operand is a reg if in
400 // reg/reg form, otherwise it's reg#0. The third field encodes the operation
401 // in bit 12, the immediate in bits 0-11, and the shift op in 13-15.
403 // If this addressing mode is a frame index (before prolog/epilog insertion
404 // and code rewriting), this operand will have the form: FI#, reg0, <offs>
405 // with no shift amount for the frame offset.
407 static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO) {
408 assert(Imm12 < (1 << 12) && "Imm too large!");
409 bool isSub = Opc == sub;
410 return Imm12 | ((int)isSub << 12) | (SO << 13);
412 static inline unsigned getAM2Offset(unsigned AM2Opc) {
413 return AM2Opc & ((1 << 12)-1);
415 static inline AddrOpc getAM2Op(unsigned AM2Opc) {
416 return ((AM2Opc >> 12) & 1) ? sub : add;
418 static inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) {
419 return (ShiftOpc)(AM2Opc >> 13);
423 //===--------------------------------------------------------------------===//
424 // Addressing Mode #3
425 //===--------------------------------------------------------------------===//
427 // This is used for sign-extending loads, and load/store-pair instructions.
429 // addrmode3 := reg +/- reg
430 // addrmode3 := reg +/- imm8
432 // The first operand is always a Reg. The second operand is a reg if in
433 // reg/reg form, otherwise it's reg#0. The third field encodes the operation
434 // in bit 8, the immediate in bits 0-7.
436 /// getAM3Opc - This function encodes the addrmode3 opc field.
437 static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset) {
438 bool isSub = Opc == sub;
439 return ((int)isSub << 8) | Offset;
441 static inline unsigned char getAM3Offset(unsigned AM3Opc) {
442 return AM3Opc & 0xFF;
444 static inline AddrOpc getAM3Op(unsigned AM3Opc) {
445 return ((AM3Opc >> 8) & 1) ? sub : add;
448 //===--------------------------------------------------------------------===//
449 // Addressing Mode #4
450 //===--------------------------------------------------------------------===//
452 // This is used for load / store multiple instructions.
454 // addrmode4 := reg, <mode>
456 // The four modes are:
457 // IA - Increment after
458 // IB - Increment before
459 // DA - Decrement after
460 // DB - Decrement before
461 // For VFP instructions, only the IA and DB modes are valid.
463 static inline AMSubMode getAM4SubMode(unsigned Mode) {
464 return (AMSubMode)(Mode & 0x7);
467 static inline unsigned getAM4ModeImm(AMSubMode SubMode) {
471 //===--------------------------------------------------------------------===//
472 // Addressing Mode #5
473 //===--------------------------------------------------------------------===//
475 // This is used for coprocessor instructions, such as FP load/stores.
477 // addrmode5 := reg +/- imm8*4
479 // The first operand is always a Reg. The second operand encodes the
480 // operation in bit 8 and the immediate in bits 0-7.
482 /// getAM5Opc - This function encodes the addrmode5 opc field.
483 static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) {
484 bool isSub = Opc == sub;
485 return ((int)isSub << 8) | Offset;
487 static inline unsigned char getAM5Offset(unsigned AM5Opc) {
488 return AM5Opc & 0xFF;
490 static inline AddrOpc getAM5Op(unsigned AM5Opc) {
491 return ((AM5Opc >> 8) & 1) ? sub : add;
494 //===--------------------------------------------------------------------===//
495 // Addressing Mode #6
496 //===--------------------------------------------------------------------===//
498 // This is used for NEON load / store instructions.
500 // addrmode6 := reg with optional alignment
502 // This is stored in two operands [regaddr, align]. The first is the
503 // address register. The second operand is the value of the alignment
504 // specifier in bytes or zero if no explicit alignment.
505 // Valid alignments depend on the specific instruction.
507 //===--------------------------------------------------------------------===//
508 // NEON Modified Immediates
509 //===--------------------------------------------------------------------===//
511 // Several NEON instructions (e.g., VMOV) take a "modified immediate"
512 // vector operand, where a small immediate encoded in the instruction
513 // specifies a full NEON vector value. These modified immediates are
514 // represented here as encoded integers. The low 8 bits hold the immediate
515 // value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold
516 // the "Cmode" field of the instruction. The interfaces below treat the
517 // Op and Cmode values as a single 5-bit value.
519 static inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val) {
520 return (OpCmode << 8) | Val;
522 static inline unsigned getNEONModImmOpCmode(unsigned ModImm) {
523 return (ModImm >> 8) & 0x1f;
525 static inline unsigned getNEONModImmVal(unsigned ModImm) {
526 return ModImm & 0xff;
529 /// decodeNEONModImm - Decode a NEON modified immediate value into the
530 /// element value and the element size in bits. (If the element size is
531 /// smaller than the vector, it is splatted into all the elements.)
532 static inline uint64_t decodeNEONModImm(unsigned ModImm, unsigned &EltBits) {
533 unsigned OpCmode = getNEONModImmOpCmode(ModImm);
534 unsigned Imm8 = getNEONModImmVal(ModImm);
537 if (OpCmode == 0xe) {
538 // 8-bit vector elements
541 } else if ((OpCmode & 0xc) == 0x8) {
542 // 16-bit vector elements
543 unsigned ByteNum = (OpCmode & 0x6) >> 1;
544 Val = Imm8 << (8 * ByteNum);
546 } else if ((OpCmode & 0x8) == 0) {
547 // 32-bit vector elements, zero with one byte set
548 unsigned ByteNum = (OpCmode & 0x6) >> 1;
549 Val = Imm8 << (8 * ByteNum);
551 } else if ((OpCmode & 0xe) == 0xc) {
552 // 32-bit vector elements, one byte with low bits set
553 unsigned ByteNum = 1 + (OpCmode & 0x1);
554 Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
556 } else if (OpCmode == 0x1e) {
557 // 64-bit vector elements
558 for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {
559 if ((ModImm >> ByteNum) & 1)
560 Val |= (uint64_t)0xff << (8 * ByteNum);
564 assert(false && "Unsupported NEON immediate");
569 } // end namespace ARM_AM
570 } // end namespace llvm