1 //===- ARMAddressingModes.h - ARM Addressing Modes --------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM addressing mode implementation stuff.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
15 #define LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
17 #include "llvm/CodeGen/SelectionDAGNodes.h"
18 #include "llvm/Support/MathExtras.h"
23 /// ARM_AM - ARM Addressing Mode Stuff
38 static inline const char *getShiftOpcStr(ShiftOpc Op) {
40 default: assert(0 && "Unknown shift opc!");
41 case ARM_AM::asr: return "asr";
42 case ARM_AM::lsl: return "lsl";
43 case ARM_AM::lsr: return "lsr";
44 case ARM_AM::ror: return "ror";
45 case ARM_AM::rrx: return "rrx";
49 static inline ShiftOpc getShiftOpcForNode(SDValue N) {
50 switch (N.getOpcode()) {
51 default: return ARM_AM::no_shift;
52 case ISD::SHL: return ARM_AM::lsl;
53 case ISD::SRL: return ARM_AM::lsr;
54 case ISD::SRA: return ARM_AM::asr;
55 case ISD::ROTR: return ARM_AM::ror;
56 //case ISD::ROTL: // Only if imm -> turn into ROTR.
57 // Can't handle RRX here, because it would require folding a flag into
58 // the addressing mode. :( This causes us to miss certain things.
59 //case ARMISD::RRX: return ARM_AM::rrx;
71 static inline const char *getAMSubModeStr(AMSubMode Mode) {
73 default: assert(0 && "Unknown addressing sub-mode!");
74 case ARM_AM::ia: return "ia";
75 case ARM_AM::ib: return "ib";
76 case ARM_AM::da: return "da";
77 case ARM_AM::db: return "db";
81 /// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
83 static inline unsigned rotr32(unsigned Val, unsigned Amt) {
84 assert(Amt < 32 && "Invalid rotate amount");
85 return (Val >> Amt) | (Val << ((32-Amt)&31));
88 /// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits.
90 static inline unsigned rotl32(unsigned Val, unsigned Amt) {
91 assert(Amt < 32 && "Invalid rotate amount");
92 return (Val << Amt) | (Val >> ((32-Amt)&31));
95 //===--------------------------------------------------------------------===//
96 // Addressing Mode #1: shift_operand with registers
97 //===--------------------------------------------------------------------===//
99 // This 'addressing mode' is used for arithmetic instructions. It can
100 // represent things like:
102 // reg [asr|lsl|lsr|ror|rrx] reg
103 // reg [asr|lsl|lsr|ror|rrx] imm
105 // This is stored three operands [rega, regb, opc]. The first is the base
106 // reg, the second is the shift amount (or reg0 if not present or imm). The
107 // third operand encodes the shift opcode and the imm if a reg isn't present.
109 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
110 return ShOp | (Imm << 3);
112 static inline unsigned getSORegOffset(unsigned Op) {
115 static inline ShiftOpc getSORegShOp(unsigned Op) {
116 return (ShiftOpc)(Op & 7);
119 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
120 /// the 8-bit imm value.
121 static inline unsigned getSOImmValImm(unsigned Imm) {
124 /// getSOImmValRot - Given an encoded imm field for the reg/imm form, return
125 /// the rotate amount.
126 static inline unsigned getSOImmValRot(unsigned Imm) {
127 return (Imm >> 8) * 2;
130 /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand,
131 /// computing the rotate amount to use. If this immediate value cannot be
132 /// handled with a single shifter-op, determine a good rotate amount that will
133 /// take a maximal chunk of bits out of the immediate.
134 static inline unsigned getSOImmValRotate(unsigned Imm) {
135 // 8-bit (or less) immediates are trivially shifter_operands with a rotate
137 if ((Imm & ~255U) == 0) return 0;
139 // Use CTZ to compute the rotate amount.
140 unsigned TZ = CountTrailingZeros_32(Imm);
142 // Rotate amount must be even. Something like 0x200 must be rotated 8 bits,
144 unsigned RotAmt = TZ & ~1;
146 // If we can handle this spread, return it.
147 if ((rotr32(Imm, RotAmt) & ~255U) == 0)
148 return (32-RotAmt)&31; // HW rotates right, not left.
150 // For values like 0xF000000F, we should skip the first run of ones, then
153 unsigned TrailingOnes = CountTrailingZeros_32(~Imm);
154 if (TrailingOnes != 32) { // Avoid overflow on 0xFFFFFFFF
155 // Restart the search for a high-order bit after the initial seconds of
157 unsigned TZ2 = CountTrailingZeros_32(Imm & ~((1 << TrailingOnes)-1));
159 // Rotate amount must be even.
160 unsigned RotAmt2 = TZ2 & ~1;
162 // If this fits, use it.
163 if (RotAmt2 != 32 && (rotr32(Imm, RotAmt2) & ~255U) == 0)
164 return (32-RotAmt2)&31; // HW rotates right, not left.
168 // Otherwise, we have no way to cover this span of bits with a single
169 // shifter_op immediate. Return a chunk of bits that will be useful to
171 return (32-RotAmt)&31; // HW rotates right, not left.
174 /// getSOImmVal - Given a 32-bit immediate, if it is something that can fit
175 /// into an shifter_operand immediate operand, return the 12-bit encoding for
176 /// it. If not, return -1.
177 static inline int getSOImmVal(unsigned Arg) {
178 // 8-bit (or less) immediates are trivially shifter_operands with a rotate
180 if ((Arg & ~255U) == 0) return Arg;
182 unsigned RotAmt = getSOImmValRotate(Arg);
184 // If this cannot be handled with a single shifter_op, bail out.
185 if (rotr32(~255U, RotAmt) & Arg)
188 // Encode this correctly.
189 return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8);
192 /// isSOImmTwoPartVal - Return true if the specified value can be obtained by
193 /// or'ing together two SOImmVal's.
194 static inline bool isSOImmTwoPartVal(unsigned V) {
195 // If this can be handled with a single shifter_op, bail out.
196 V = rotr32(~255U, getSOImmValRotate(V)) & V;
200 // If this can be handled with two shifter_op's, accept.
201 V = rotr32(~255U, getSOImmValRotate(V)) & V;
205 /// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal,
206 /// return the first chunk of it.
207 static inline unsigned getSOImmTwoPartFirst(unsigned V) {
208 return rotr32(255U, getSOImmValRotate(V)) & V;
211 /// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal,
212 /// return the second chunk of it.
213 static inline unsigned getSOImmTwoPartSecond(unsigned V) {
214 // Mask out the first hunk.
215 V = rotr32(~255U, getSOImmValRotate(V)) & V;
218 assert(V == (rotr32(255U, getSOImmValRotate(V)) & V));
222 /// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed
223 /// by a left shift. Returns the shift amount to use.
224 static inline unsigned getThumbImmValShift(unsigned Imm) {
225 // 8-bit (or less) immediates are trivially immediate operand with a shift
227 if ((Imm & ~255U) == 0) return 0;
229 // Use CTZ to compute the shift amount.
230 return CountTrailingZeros_32(Imm);
233 /// isThumbImmShiftedVal - Return true if the specified value can be obtained
234 /// by left shifting a 8-bit immediate.
235 static inline bool isThumbImmShiftedVal(unsigned V) {
236 // If this can be handled with
237 V = (~255U << getThumbImmValShift(V)) & V;
241 /// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed
242 /// by a left shift. Returns the shift amount to use.
243 static inline unsigned getThumbImm16ValShift(unsigned Imm) {
244 // 16-bit (or less) immediates are trivially immediate operand with a shift
246 if ((Imm & ~65535U) == 0) return 0;
248 // Use CTZ to compute the shift amount.
249 return CountTrailingZeros_32(Imm);
252 /// isThumbImm16ShiftedVal - Return true if the specified value can be
253 /// obtained by left shifting a 16-bit immediate.
254 static inline bool isThumbImm16ShiftedVal(unsigned V) {
255 // If this can be handled with
256 V = (~65535U << getThumbImm16ValShift(V)) & V;
260 /// getThumbImmNonShiftedVal - If V is a value that satisfies
261 /// isThumbImmShiftedVal, return the non-shiftd value.
262 static inline unsigned getThumbImmNonShiftedVal(unsigned V) {
263 return V >> getThumbImmValShift(V);
267 /// getT2SOImmValSplat - Return the 12-bit encoded representation
268 /// if the specified value can be obtained by splatting the low 8 bits
269 /// into every other byte or every byte of a 32-bit value. i.e.,
270 /// 00000000 00000000 00000000 abcdefgh control = 0
271 /// 00000000 abcdefgh 00000000 abcdefgh control = 1
272 /// abcdefgh 00000000 abcdefgh 00000000 control = 2
273 /// abcdefgh abcdefgh abcdefgh abcdefgh control = 3
274 /// Return -1 if none of the above apply.
275 /// See ARM Reference Manual A6.3.2.
276 static inline int getT2SOImmValSplatVal(unsigned V) {
279 if ((V & 0xffffff00) == 0)
282 // If the value is zeroes in the first byte, just shift those off
283 Vs = ((V & 0xff) == 0) ? V >> 8 : V;
284 // Any passing value only has 8 bits of payload, splatted across the word
286 // Likewise, any passing values have the payload splatted into the 3rd byte
287 u = Imm | (Imm << 16);
291 return (((Vs == V) ? 1 : 2) << 8) | Imm;
294 if (Vs == (u | (u << 8)))
295 return (3 << 8) | Imm;
300 /// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the
301 /// specified value is a rotated 8-bit value. Return -1 if no rotation
302 /// encoding is possible.
303 /// See ARM Reference Manual A6.3.2.
304 static inline int getT2SOImmValRotateVal(unsigned V) {
305 unsigned RotAmt = CountLeadingZeros_32(V);
309 // If 'Arg' can be handled with a single shifter_op return the value.
310 if ((rotr32(0xff000000U, RotAmt) & V) == V)
311 return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7);
316 /// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit
317 /// into a Thumb-2 shifter_operand immediate operand, return the 12-bit
318 /// encoding for it. If not, return -1.
319 /// See ARM Reference Manual A6.3.2.
320 static inline int getT2SOImmVal(unsigned Arg) {
321 // If 'Arg' is an 8-bit splat, then get the encoded value.
322 int Splat = getT2SOImmValSplatVal(Arg);
326 // If 'Arg' can be handled with a single shifter_op return the value.
327 int Rot = getT2SOImmValRotateVal(Arg);
334 static inline unsigned getT2SOImmValRotate(unsigned V) {
335 if ((V & ~255U) == 0) return 0;
336 // Use CTZ to compute the rotate amount.
337 unsigned RotAmt = CountTrailingZeros_32(V);
338 return (32 - RotAmt) & 31;
341 static inline bool isT2SOImmTwoPartVal (unsigned Imm) {
343 // Passing values can be any combination of splat values and shifter
344 // values. If this can be handled with a single shifter or splat, bail
345 // out. Those should be handled directly, not with a two-part val.
346 if (getT2SOImmValSplatVal(V) != -1)
348 V = rotr32 (~255U, getT2SOImmValRotate(V)) & V;
352 // If this can be handled as an immediate, accept.
353 if (getT2SOImmVal(V) != -1) return true;
355 // Likewise, try masking out a splat value first.
357 if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
359 else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
361 // If what's left can be handled as an immediate, accept.
362 if (getT2SOImmVal(V) != -1) return true;
364 // Otherwise, do not accept.
368 static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm) {
369 assert (isT2SOImmTwoPartVal(Imm) &&
370 "Immedate cannot be encoded as two part immediate!");
371 // Try a shifter operand as one part
372 unsigned V = rotr32 (~255, getT2SOImmValRotate(Imm)) & Imm;
373 // If the rest is encodable as an immediate, then return it.
374 if (getT2SOImmVal(V) != -1) return V;
376 // Try masking out a splat value first.
377 if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
378 return Imm & 0xff00ff00U;
380 // The other splat is all that's left as an option.
381 assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1);
382 return Imm & 0x00ff00ffU;
385 static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) {
386 // Mask out the first hunk
387 Imm ^= getT2SOImmTwoPartFirst(Imm);
388 // Return what's left
389 assert (getT2SOImmVal(Imm) != -1 &&
390 "Unable to encode second part of T2 two part SO immediate");
395 //===--------------------------------------------------------------------===//
396 // Addressing Mode #2
397 //===--------------------------------------------------------------------===//
399 // This is used for most simple load/store instructions.
401 // addrmode2 := reg +/- reg shop imm
402 // addrmode2 := reg +/- imm12
404 // The first operand is always a Reg. The second operand is a reg if in
405 // reg/reg form, otherwise it's reg#0. The third field encodes the operation
406 // in bit 12, the immediate in bits 0-11, and the shift op in 13-15.
408 // If this addressing mode is a frame index (before prolog/epilog insertion
409 // and code rewriting), this operand will have the form: FI#, reg0, <offs>
410 // with no shift amount for the frame offset.
412 static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO) {
413 assert(Imm12 < (1 << 12) && "Imm too large!");
414 bool isSub = Opc == sub;
415 return Imm12 | ((int)isSub << 12) | (SO << 13);
417 static inline unsigned getAM2Offset(unsigned AM2Opc) {
418 return AM2Opc & ((1 << 12)-1);
420 static inline AddrOpc getAM2Op(unsigned AM2Opc) {
421 return ((AM2Opc >> 12) & 1) ? sub : add;
423 static inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) {
424 return (ShiftOpc)(AM2Opc >> 13);
428 //===--------------------------------------------------------------------===//
429 // Addressing Mode #3
430 //===--------------------------------------------------------------------===//
432 // This is used for sign-extending loads, and load/store-pair instructions.
434 // addrmode3 := reg +/- reg
435 // addrmode3 := reg +/- imm8
437 // The first operand is always a Reg. The second operand is a reg if in
438 // reg/reg form, otherwise it's reg#0. The third field encodes the operation
439 // in bit 8, the immediate in bits 0-7.
441 /// getAM3Opc - This function encodes the addrmode3 opc field.
442 static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset) {
443 bool isSub = Opc == sub;
444 return ((int)isSub << 8) | Offset;
446 static inline unsigned char getAM3Offset(unsigned AM3Opc) {
447 return AM3Opc & 0xFF;
449 static inline AddrOpc getAM3Op(unsigned AM3Opc) {
450 return ((AM3Opc >> 8) & 1) ? sub : add;
453 //===--------------------------------------------------------------------===//
454 // Addressing Mode #4
455 //===--------------------------------------------------------------------===//
457 // This is used for load / store multiple instructions.
459 // addrmode4 := reg, <mode>
461 // The four modes are:
462 // IA - Increment after
463 // IB - Increment before
464 // DA - Decrement after
465 // DB - Decrement before
467 static inline AMSubMode getAM4SubMode(unsigned Mode) {
468 return (AMSubMode)(Mode & 0x7);
471 static inline unsigned getAM4ModeImm(AMSubMode SubMode) {
475 //===--------------------------------------------------------------------===//
476 // Addressing Mode #5
477 //===--------------------------------------------------------------------===//
479 // This is used for coprocessor instructions, such as FP load/stores.
481 // addrmode5 := reg +/- imm8*4
483 // The first operand is always a Reg. The second operand encodes the
484 // operation in bit 8 and the immediate in bits 0-7.
486 // This is also used for FP load/store multiple ops. The second operand
487 // encodes the number of registers (or 2 times the number of registers
488 // for DPR ops) in bits 0-7. In addition, bits 8-10 encode one of the
489 // following two sub-modes:
491 // IA - Increment after
492 // DB - Decrement before
494 /// getAM5Opc - This function encodes the addrmode5 opc field.
495 static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) {
496 bool isSub = Opc == sub;
497 return ((int)isSub << 8) | Offset;
499 static inline unsigned char getAM5Offset(unsigned AM5Opc) {
500 return AM5Opc & 0xFF;
502 static inline AddrOpc getAM5Op(unsigned AM5Opc) {
503 return ((AM5Opc >> 8) & 1) ? sub : add;
506 /// getAM5Opc - This function encodes the addrmode5 opc field for VLDM and
507 /// VSTM instructions.
508 static inline unsigned getAM5Opc(AMSubMode SubMode, unsigned char Offset) {
509 assert((SubMode == ia || SubMode == db) &&
510 "Illegal addressing mode 5 sub-mode!");
511 return ((int)SubMode << 8) | Offset;
513 static inline AMSubMode getAM5SubMode(unsigned AM5Opc) {
514 return (AMSubMode)((AM5Opc >> 8) & 0x7);
517 //===--------------------------------------------------------------------===//
518 // Addressing Mode #6
519 //===--------------------------------------------------------------------===//
521 // This is used for NEON load / store instructions.
523 // addrmode6 := reg with optional writeback and alignment
525 // This is stored in four operands [regaddr, regupdate, opc, align]. The
526 // first is the address register. The second register holds the value of
527 // a post-access increment for writeback or reg0 if no writeback or if the
528 // writeback increment is the size of the memory access. The third
529 // operand encodes whether there is writeback to the address register. The
530 // fourth operand is the value of the alignment specifier to use or zero if
531 // no explicit alignment.
533 static inline unsigned getAM6Opc(bool WB = false) {
537 static inline bool getAM6WBFlag(unsigned Mode) {
541 } // end namespace ARM_AM
542 } // end namespace llvm