1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMAddressingModes.h"
12 #include "ARMFixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCDirectives.h"
16 #include "llvm/MC/MCELFObjectWriter.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCMachObjectWriter.h"
19 #include "llvm/MC/MCObjectFormat.h"
20 #include "llvm/MC/MCObjectWriter.h"
21 #include "llvm/MC/MCSectionELF.h"
22 #include "llvm/MC/MCSectionMachO.h"
23 #include "llvm/Object/MachOFormat.h"
24 #include "llvm/Support/ELF.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/Target/TargetAsmBackend.h"
28 #include "llvm/Target/TargetRegistry.h"
32 class ARMMachObjectWriter : public MCMachObjectTargetWriter {
34 ARMMachObjectWriter(bool Is64Bit, uint32_t CPUType,
36 : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype,
37 /*UseAggressiveSymbolFolding=*/true) {}
40 class ARMELFObjectWriter : public MCELFObjectTargetWriter {
42 ARMELFObjectWriter() : MCELFObjectTargetWriter() {}
45 class ARMAsmBackend : public TargetAsmBackend {
46 bool isThumbMode; // Currently emitting Thumb code.
48 ARMAsmBackend(const Target &T) : TargetAsmBackend(), isThumbMode(false) {}
50 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
52 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
53 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
54 // This table *must* be in the order that the fixup_* kinds are defined in
57 // Name Offset (bits) Size (bits) Flags
58 { "fixup_arm_ldst_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
59 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
60 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
61 { "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
62 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
63 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
64 { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel |
65 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
66 { "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
67 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
68 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
69 { "fixup_arm_branch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
70 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
71 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
72 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
73 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
74 { "fixup_arm_thumb_blx", 7, 21, MCFixupKindInfo::FKF_IsPCRel },
75 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
76 { "fixup_arm_thumb_cp", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
77 { "fixup_arm_thumb_bcc", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
78 { "fixup_arm_movt_hi16", 0, 16, 0 },
79 { "fixup_arm_movw_lo16", 0, 16, 0 },
82 if (Kind < FirstTargetFixupKind)
83 return TargetAsmBackend::getFixupKindInfo(Kind);
85 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
87 return Infos[Kind - FirstTargetFixupKind];
90 bool MayNeedRelaxation(const MCInst &Inst) const;
92 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
94 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
96 void HandleAssemblerFlag(MCAssemblerFlag Flag) {
108 unsigned getPointerSize() const { return 4; }
109 bool isThumb() const { return isThumbMode; }
110 void setIsThumb(bool it) { isThumbMode = it; }
112 } // end anonymous namespace
114 bool ARMAsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
115 // FIXME: Thumb targets, different move constant targets..
119 void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
120 assert(0 && "ARMAsmBackend::RelaxInstruction() unimplemented");
124 bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
126 assert (((Count & 1) == 0) && "Unaligned Nop data fragment!");
127 // FIXME: 0xbf00 is the ARMv7 value. For v6 and before, we'll need to
128 // use 0x46c0 (which is a 'mov r8, r8' insn).
130 for (uint64_t i = 0; i != Count; ++i)
136 for (uint64_t i = 0; i != Count; ++i)
137 OW->Write32(0xe1a00000);
141 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
144 llvm_unreachable("Unknown fixup kind!");
149 case ARM::fixup_arm_movt_hi16:
150 case ARM::fixup_arm_movw_lo16: {
151 unsigned Hi4 = (Value & 0xF000) >> 12;
152 unsigned Lo12 = Value & 0x0FFF;
153 // inst{19-16} = Hi4;
154 // inst{11-0} = Lo12;
155 Value = (Hi4 << 16) | (Lo12);
158 case ARM::fixup_arm_ldst_pcrel_12:
159 // ARM PC-relative values are offset by 8.
162 case ARM::fixup_t2_ldst_pcrel_12: {
163 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
166 if ((int64_t)Value < 0) {
170 assert ((Value < 4096) && "Out of range pc-relative fixup value!");
171 Value |= isAdd << 23;
173 // Same addressing mode as fixup_arm_pcrel_10,
174 // but with 16-bit halfwords swapped.
175 if (Kind == ARM::fixup_t2_ldst_pcrel_12) {
176 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
177 swapped |= (Value & 0x0000FFFF) << 16;
183 case ARM::fixup_thumb_adr_pcrel_10:
184 return ((Value - 4) >> 2) & 0xff;
185 case ARM::fixup_arm_adr_pcrel_12: {
186 // ARM PC-relative values are offset by 8.
188 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
189 if ((int64_t)Value < 0) {
193 assert(ARM_AM::getSOImmVal(Value) != -1 &&
194 "Out of range pc-relative fixup value!");
195 // Encode the immediate and shift the opcode into place.
196 return ARM_AM::getSOImmVal(Value) | (opc << 21);
199 case ARM::fixup_t2_adr_pcrel_12: {
202 if ((int64_t)Value < 0) {
207 uint32_t out = (opc << 21);
208 out |= (Value & 0x800) << 14;
209 out |= (Value & 0x700) << 4;
210 out |= (Value & 0x0FF);
212 uint64_t swapped = (out & 0xFFFF0000) >> 16;
213 swapped |= (out & 0x0000FFFF) << 16;
217 case ARM::fixup_arm_branch:
218 // These values don't encode the low two bits since they're always zero.
219 // Offset by 8 just as above.
220 return 0xffffff & ((Value - 8) >> 2);
221 case ARM::fixup_t2_uncondbranch: {
223 Value >>= 1; // Low bit is not encoded.
226 bool I = Value & 0x800000;
227 bool J1 = Value & 0x400000;
228 bool J2 = Value & 0x200000;
232 out |= I << 26; // S bit
233 out |= !J1 << 13; // J1 bit
234 out |= !J2 << 11; // J2 bit
235 out |= (Value & 0x1FF800) << 5; // imm6 field
236 out |= (Value & 0x0007FF); // imm11 field
238 uint64_t swapped = (out & 0xFFFF0000) >> 16;
239 swapped |= (out & 0x0000FFFF) << 16;
242 case ARM::fixup_t2_condbranch: {
244 Value >>= 1; // Low bit is not encoded.
247 out |= (Value & 0x80000) << 7; // S bit
248 out |= (Value & 0x40000) >> 7; // J2 bit
249 out |= (Value & 0x20000) >> 4; // J1 bit
250 out |= (Value & 0x1F800) << 5; // imm6 field
251 out |= (Value & 0x007FF); // imm11 field
253 uint32_t swapped = (out & 0xFFFF0000) >> 16;
254 swapped |= (out & 0x0000FFFF) << 16;
257 case ARM::fixup_arm_thumb_bl: {
258 // The value doesn't encode the low bit (always zero) and is offset by
259 // four. The value is encoded into disjoint bit positions in the destination
260 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit
262 // BL: xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII
264 // Note that the halfwords are stored high first, low second; so we need
265 // to transpose the fixup value here to map properly.
266 unsigned isNeg = (int64_t(Value) < 0) ? 1 : 0;
268 Value = 0x3fffff & ((Value - 4) >> 1);
269 Binary = (Value & 0x7ff) << 16; // Low imm11 value.
270 Binary |= (Value & 0x1ffc00) >> 11; // High imm10 value.
271 Binary |= isNeg << 10; // Sign bit.
274 case ARM::fixup_arm_thumb_blx: {
275 // The value doesn't encode the low two bits (always zero) and is offset by
276 // four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit
277 // positions in the destination opcode. x = unchanged, I = immediate value
278 // bit, S = sign extension bit, 0 = zero.
280 // BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0
282 // Note that the halfwords are stored high first, low second; so we need
283 // to transpose the fixup value here to map properly.
284 unsigned isNeg = (int64_t(Value) < 0) ? 1 : 0;
286 Value = 0xfffff & ((Value - 2) >> 2);
287 Binary = (Value & 0x3ff) << 17; // Low imm10L value.
288 Binary |= (Value & 0xffc00) >> 10; // High imm10H value.
289 Binary |= isNeg << 10; // Sign bit.
292 case ARM::fixup_arm_thumb_cp:
293 // Offset by 4, and don't encode the low two bits. Two bytes of that
294 // 'off by 4' is implicitly handled by the half-word ordering of the
295 // Thumb encoding, so we only need to adjust by 2 here.
296 return ((Value - 2) >> 2) & 0xff;
297 case ARM::fixup_arm_thumb_cb: {
298 // Offset by 4 and don't encode the lower bit, which is always 0.
299 uint32_t Binary = (Value - 4) >> 1;
300 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
302 case ARM::fixup_arm_thumb_br:
303 // Offset by 4 and don't encode the lower bit, which is always 0.
304 return ((Value - 4) >> 1) & 0x7ff;
305 case ARM::fixup_arm_thumb_bcc:
306 // Offset by 4 and don't encode the lower bit, which is always 0.
307 return ((Value - 4) >> 1) & 0xff;
308 case ARM::fixup_arm_pcrel_10:
309 Value = Value - 4; // ARM fixups offset by an additional word and don't
310 // need to adjust for the half-word ordering.
312 case ARM::fixup_t2_pcrel_10: {
313 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
316 if ((int64_t)Value < 0) {
320 // These values don't encode the low two bits since they're always zero.
322 assert ((Value < 256) && "Out of range pc-relative fixup value!");
323 Value |= isAdd << 23;
325 // Same addressing mode as fixup_arm_pcrel_10,
326 // but with 16-bit halfwords swapped.
327 if (Kind == ARM::fixup_t2_pcrel_10) {
328 uint32_t swapped = (Value & 0xFFFF0000) >> 16;
329 swapped |= (Value & 0x0000FFFF) << 16;
340 // FIXME: This should be in a separate file.
341 // ELF is an ELF of course...
342 class ELFARMAsmBackend : public ARMAsmBackend {
343 MCELFObjectFormat Format;
346 Triple::OSType OSType;
347 ELFARMAsmBackend(const Target &T, Triple::OSType _OSType)
348 : ARMAsmBackend(T), OSType(_OSType) { }
350 virtual const MCObjectFormat &getObjectFormat() const {
354 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
355 uint64_t Value) const;
357 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
358 return createELFObjectWriter(new ARMELFObjectWriter(), OS,
361 /*IsLittleEndian=*/true,
362 /*HasRelocationAddend=*/false);
366 // FIXME: Raise this to share code between Darwin and ELF.
367 void ELFARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
368 unsigned DataSize, uint64_t Value) const {
369 unsigned NumBytes = 4; // FIXME: 2 for Thumb
370 Value = adjustFixupValue(Fixup.getKind(), Value);
371 if (!Value) return; // Doesn't change encoding.
373 unsigned Offset = Fixup.getOffset();
374 assert(Offset % NumBytes == 0 && "Offset mod NumBytes is nonzero!");
376 // For each byte of the fragment that the fixup touches, mask in the bits from
377 // the fixup value. The Value has been "split up" into the appropriate
379 for (unsigned i = 0; i != NumBytes; ++i)
380 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
383 // FIXME: This should be in a separate file.
384 class DarwinARMAsmBackend : public ARMAsmBackend {
385 MCMachOObjectFormat Format;
387 DarwinARMAsmBackend(const Target &T) : ARMAsmBackend(T) { }
389 virtual const MCObjectFormat &getObjectFormat() const {
393 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
394 uint64_t Value) const;
396 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
397 // FIXME: Subtarget info should be derived. Force v7 for now.
398 return createMachObjectWriter(new ARMMachObjectWriter(
400 object::mach::CTM_ARM,
401 object::mach::CSARM_V7),
403 /*IsLittleEndian=*/true);
406 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
411 /// getFixupKindNumBytes - The number of bytes the fixup may change.
412 static unsigned getFixupKindNumBytes(unsigned Kind) {
415 llvm_unreachable("Unknown fixup kind!");
418 case ARM::fixup_arm_thumb_bcc:
419 case ARM::fixup_arm_thumb_cp:
420 case ARM::fixup_thumb_adr_pcrel_10:
424 case ARM::fixup_arm_thumb_br:
425 case ARM::fixup_arm_thumb_cb:
428 case ARM::fixup_arm_ldst_pcrel_12:
429 case ARM::fixup_arm_pcrel_10:
430 case ARM::fixup_arm_adr_pcrel_12:
431 case ARM::fixup_arm_branch:
435 case ARM::fixup_t2_ldst_pcrel_12:
436 case ARM::fixup_t2_condbranch:
437 case ARM::fixup_t2_uncondbranch:
438 case ARM::fixup_t2_pcrel_10:
439 case ARM::fixup_t2_adr_pcrel_12:
440 case ARM::fixup_arm_thumb_bl:
441 case ARM::fixup_arm_thumb_blx:
446 void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
447 unsigned DataSize, uint64_t Value) const {
448 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
449 Value = adjustFixupValue(Fixup.getKind(), Value);
450 if (!Value) return; // Doesn't change encoding.
452 unsigned Offset = Fixup.getOffset();
453 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
455 // For each byte of the fragment that the fixup touches, mask in the
456 // bits from the fixup value.
457 for (unsigned i = 0; i != NumBytes; ++i)
458 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
461 } // end anonymous namespace
463 TargetAsmBackend *llvm::createARMAsmBackend(const Target &T,
464 const std::string &TT) {
465 switch (Triple(TT).getOS()) {
467 return new DarwinARMAsmBackend(T);
468 case Triple::MinGW32:
471 assert(0 && "Windows not supported on ARM");
473 return new ELFARMAsmBackend(T, Triple(TT).getOS());