1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Target/TargetAsmBackend.h"
12 #include "ARMFixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCObjectFormat.h"
17 #include "llvm/MC/MCObjectWriter.h"
18 #include "llvm/MC/MCSectionELF.h"
19 #include "llvm/MC/MCSectionMachO.h"
20 #include "llvm/Object/MachOFormat.h"
21 #include "llvm/Support/ELF.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Target/TargetRegistry.h"
28 class ARMAsmBackend : public TargetAsmBackend {
30 ARMAsmBackend(const Target &T) : TargetAsmBackend() {}
32 bool MayNeedRelaxation(const MCInst &Inst) const;
34 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
36 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
38 unsigned getPointerSize() const {
42 } // end anonymous namespace
44 bool ARMAsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
45 // FIXME: Thumb targets, different move constant targets..
49 void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
50 assert(0 && "ARMAsmBackend::RelaxInstruction() unimplemented");
54 bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
55 // if ((Count % 4) != 0) {
56 // // Fixme: % 2 for Thumb?
59 // FIXME: Zero fill for now. That's not right, but at least will get the
60 // section size right.
61 for (uint64_t i = 0; i != Count; ++i)
67 // FIXME: This should be in a separate file.
68 // ELF is an ELF of course...
69 class ELFARMAsmBackend : public ARMAsmBackend {
70 MCELFObjectFormat Format;
73 Triple::OSType OSType;
74 ELFARMAsmBackend(const Target &T, Triple::OSType _OSType)
75 : ARMAsmBackend(T), OSType(_OSType) {
76 HasScatteredSymbols = true;
79 virtual const MCObjectFormat &getObjectFormat() const {
83 void ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
84 uint64_t Value) const;
86 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
87 return createELFObjectWriter(OS, /*Is64Bit=*/false,
89 /*IsLittleEndian=*/true,
90 /*HasRelocationAddend=*/false);
94 // Fixme: can we raise this to share code between Darwin and ELF?
95 void ELFARMAsmBackend::ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
96 uint64_t Value) const {
97 assert(0 && "ELFARMAsmBackend::ApplyFixup() unimplemented");
101 // FIXME: This should be in a separate file.
102 class DarwinARMAsmBackend : public ARMAsmBackend {
103 MCMachOObjectFormat Format;
105 DarwinARMAsmBackend(const Target &T) : ARMAsmBackend(T) {
106 HasScatteredSymbols = true;
109 virtual const MCObjectFormat &getObjectFormat() const {
113 void ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
114 uint64_t Value) const;
116 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
117 // FIXME: Subtarget info should be derived. Force v7 for now.
118 return createMachObjectWriter(OS, /*Is64Bit=*/false,
119 object::mach::CTM_ARM,
120 object::mach::CSARM_V7,
121 /*IsLittleEndian=*/true);
124 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
128 } // end anonymous namespace
130 static unsigned getFixupKindNumBytes(unsigned Kind) {
132 default: llvm_unreachable("Unknown fixup kind!");
133 case FK_Data_4: return 4;
134 case ARM::fixup_arm_pcrel_12: return 3;
135 case ARM::fixup_arm_vfp_pcrel_12: return 3;
136 case ARM::fixup_arm_branch: return 3;
140 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
143 llvm_unreachable("Unknown fixup kind!");
146 case ARM::fixup_arm_pcrel_12: {
148 // ARM PC-relative values are offset by 8.
150 if ((int64_t)Value < 0) {
154 assert ((Value < 4096) && "Out of range pc-relative fixup value!");
155 Value |= isAdd << 23;
158 case ARM::fixup_arm_branch:
159 // These values don't encode the low two bits since they're always zero.
160 // Offset by 8 just as above.
161 return (Value - 8) >> 2;
162 case ARM::fixup_arm_vfp_pcrel_12: {
163 // Offset by 8 just as above.
166 if ((int64_t)Value < 0) {
170 // These values don't encode the low two bits since they're always zero.
172 assert ((Value < 256) && "Out of range pc-relative fixup value!");
173 Value |= isAdd << 23;
179 void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
180 uint64_t Value) const {
181 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
182 Value = adjustFixupValue(Fixup.getKind(), Value);
184 assert(Fixup.getOffset() + NumBytes <= DF.getContents().size() &&
185 "Invalid fixup offset!");
186 // For each byte of the fragment that the fixup touches, mask in the
187 // bits from the fixup value.
188 for (unsigned i = 0; i != NumBytes; ++i)
189 DF.getContents()[Fixup.getOffset() + i] |= uint8_t(Value >> (i * 8));
191 } // end anonymous namespace
193 TargetAsmBackend *llvm::createARMAsmBackend(const Target &T,
194 const std::string &TT) {
195 switch (Triple(TT).getOS()) {
197 return new DarwinARMAsmBackend(T);
198 case Triple::MinGW32:
201 assert(0 && "Windows not supported on ARM");
203 return new ELFARMAsmBackend(T, Triple(TT).getOS());