1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMAddressingModes.h"
12 #include "ARMFixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCObjectFormat.h"
17 #include "llvm/MC/MCObjectWriter.h"
18 #include "llvm/MC/MCSectionELF.h"
19 #include "llvm/MC/MCSectionMachO.h"
20 #include "llvm/Object/MachOFormat.h"
21 #include "llvm/Support/ELF.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Target/TargetAsmBackend.h"
25 #include "llvm/Target/TargetRegistry.h"
29 class ARMAsmBackend : public TargetAsmBackend {
31 ARMAsmBackend(const Target &T) : TargetAsmBackend() {}
33 bool MayNeedRelaxation(const MCInst &Inst) const;
35 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
37 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
39 unsigned getPointerSize() const {
43 } // end anonymous namespace
45 bool ARMAsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
46 // FIXME: Thumb targets, different move constant targets..
50 void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
51 assert(0 && "ARMAsmBackend::RelaxInstruction() unimplemented");
55 bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
56 // FIXME: Zero fill for now. That's not right, but at least will get the
57 // section size right.
58 for (uint64_t i = 0; i != Count; ++i)
63 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
66 llvm_unreachable("Unknown fixup kind!");
69 case ARM::fixup_arm_movt_hi16:
70 case ARM::fixup_arm_movw_lo16: {
71 unsigned Hi4 = (Value & 0xF000) >> 12;
72 unsigned Lo12 = Value & 0x0FFF;
75 Value = (Hi4 << 16) | (Lo12);
78 case ARM::fixup_arm_ldst_pcrel_12: {
80 // ARM PC-relative values are offset by 8.
82 if ((int64_t)Value < 0) {
86 assert ((Value < 4096) && "Out of range pc-relative fixup value!");
90 case ARM::fixup_arm_adr_pcrel_12: {
91 // ARM PC-relative values are offset by 8.
93 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
94 if ((int64_t)Value < 0) {
98 assert(ARM_AM::getSOImmVal(Value) != -1 &&
99 "Out of range pc-relative fixup value!");
100 // Encode the immediate and shift the opcode into place.
101 return ARM_AM::getSOImmVal(Value) | (opc << 21);
103 case ARM::fixup_arm_branch:
104 // These values don't encode the low two bits since they're always zero.
105 // Offset by 8 just as above.
106 return 0xffffff & ((Value - 8) >> 2);
107 case ARM::fixup_arm_thumb_bl: {
108 // The value doesn't encode the low bit (always zero) and is offset by
109 // four. The value is encoded into disjoint bit positions in the destination
110 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit
111 // xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII
112 // Note that the halfwords are stored high first, low second; so we need
113 // to transpose the fixup value here to map properly.
114 uint32_t Binary = 0x3fffff & ((Value - 4) >> 1);
115 Binary = ((Binary & 0x7ff) << 16) | (Binary >> 11);
118 case ARM::fixup_t2_pcrel_10:
119 case ARM::fixup_arm_pcrel_10: {
120 // Offset by 8 just as above.
123 if ((int64_t)Value < 0) {
127 // These values don't encode the low two bits since they're always zero.
129 assert ((Value < 256) && "Out of range pc-relative fixup value!");
130 Value |= isAdd << 23;
132 // Same addressing mode as fixup_arm_pcrel_10, but with the bytes reordered.
133 if (Kind == ARM::fixup_t2_pcrel_10) {
134 uint64_t swapped = (Value & 0x00FF0000) >> 16;
135 swapped |= (Value & 0xFF000000) >> 16;
136 swapped |= (Value & 0x000000FF) << 16;
137 swapped |= (Value & 0x0000FF00) << 16;
148 // FIXME: This should be in a separate file.
149 // ELF is an ELF of course...
150 class ELFARMAsmBackend : public ARMAsmBackend {
151 MCELFObjectFormat Format;
154 Triple::OSType OSType;
155 ELFARMAsmBackend(const Target &T, Triple::OSType _OSType)
156 : ARMAsmBackend(T), OSType(_OSType) {
157 HasScatteredSymbols = true;
160 virtual const MCObjectFormat &getObjectFormat() const {
164 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
165 uint64_t Value) const;
167 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
168 return createELFObjectWriter(OS, /*Is64Bit=*/false,
170 /*IsLittleEndian=*/true,
171 /*HasRelocationAddend=*/false);
175 // FIXME: Raise this to share code between Darwin and ELF.
176 void ELFARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
177 unsigned DataSize, uint64_t Value) const {
178 unsigned NumBytes = 4; // FIXME: 2 for Thumb
179 Value = adjustFixupValue(Fixup.getKind(), Value);
180 if (!Value) return; // Doesn't change encoding.
182 unsigned Offset = Fixup.getOffset();
183 assert(Offset % NumBytes == 0 && "Offset mod NumBytes is nonzero!");
185 // For each byte of the fragment that the fixup touches, mask in the bits from
186 // the fixup value. The Value has been "split up" into the appropriate
188 for (unsigned i = 0; i != NumBytes; ++i)
189 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
192 // FIXME: This should be in a separate file.
193 class DarwinARMAsmBackend : public ARMAsmBackend {
194 MCMachOObjectFormat Format;
196 DarwinARMAsmBackend(const Target &T) : ARMAsmBackend(T) {
197 HasScatteredSymbols = true;
200 virtual const MCObjectFormat &getObjectFormat() const {
204 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
205 uint64_t Value) const;
207 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
208 // FIXME: Subtarget info should be derived. Force v7 for now.
209 return createMachObjectWriter(OS, /*Is64Bit=*/false,
210 object::mach::CTM_ARM,
211 object::mach::CSARM_V7,
212 /*IsLittleEndian=*/true);
215 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
220 /// getFixupKindNumBytes - The number of bytes the fixup may change.
221 static unsigned getFixupKindNumBytes(unsigned Kind) {
224 llvm_unreachable("Unknown fixup kind!");
227 case ARM::fixup_arm_ldst_pcrel_12:
228 case ARM::fixup_arm_pcrel_10:
229 case ARM::fixup_arm_adr_pcrel_12:
230 case ARM::fixup_arm_branch:
232 case ARM::fixup_t2_pcrel_10:
233 case ARM::fixup_arm_thumb_bl:
238 void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
239 unsigned DataSize, uint64_t Value) const {
240 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
241 Value = adjustFixupValue(Fixup.getKind(), Value);
242 if (!Value) return; // Doesn't change encoding.
244 unsigned Offset = Fixup.getOffset();
245 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
247 // For each byte of the fragment that the fixup touches, mask in the
248 // bits from the fixup value.
249 for (unsigned i = 0; i != NumBytes; ++i)
250 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
253 } // end anonymous namespace
255 TargetAsmBackend *llvm::createARMAsmBackend(const Target &T,
256 const std::string &TT) {
257 switch (Triple(TT).getOS()) {
259 return new DarwinARMAsmBackend(T);
260 case Triple::MinGW32:
263 assert(0 && "Windows not supported on ARM");
265 return new ELFARMAsmBackend(T, Triple(TT).getOS());