1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMAddressingModes.h"
12 #include "ARMFixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCDirectives.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCObjectFormat.h"
18 #include "llvm/MC/MCObjectWriter.h"
19 #include "llvm/MC/MCSectionELF.h"
20 #include "llvm/MC/MCSectionMachO.h"
21 #include "llvm/Object/MachOFormat.h"
22 #include "llvm/Support/ELF.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include "llvm/Target/TargetAsmBackend.h"
26 #include "llvm/Target/TargetRegistry.h"
30 class ARMAsmBackend : public TargetAsmBackend {
31 bool isThumbMode; // Currently emitting Thumb code.
33 ARMAsmBackend(const Target &T) : TargetAsmBackend(), isThumbMode(false) {}
35 bool MayNeedRelaxation(const MCInst &Inst) const;
37 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
39 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
41 void HandleAssemblerFlag(MCAssemblerFlag Flag) {
53 unsigned getPointerSize() const { return 4; }
54 bool isThumb() const { return isThumbMode; }
55 void setIsThumb(bool it) { isThumbMode = it; }
57 } // end anonymous namespace
59 bool ARMAsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
60 // FIXME: Thumb targets, different move constant targets..
64 void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
65 assert(0 && "ARMAsmBackend::RelaxInstruction() unimplemented");
69 bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
71 assert (((Count & 1) == 0) && "Unaligned Nop data fragment!");
72 // FIXME: 0xbf00 is the ARMv7 value. For v6 and before, we'll need to
73 // use 0x46c0 (which is a 'mov r8, r8' insn).
75 for (uint64_t i = 0; i != Count; ++i)
81 for (uint64_t i = 0; i != Count; ++i)
82 OW->Write32(0xe1a00000);
86 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
89 llvm_unreachable("Unknown fixup kind!");
92 case ARM::fixup_arm_movt_hi16:
93 case ARM::fixup_arm_movw_lo16: {
94 unsigned Hi4 = (Value & 0xF000) >> 12;
95 unsigned Lo12 = Value & 0x0FFF;
98 Value = (Hi4 << 16) | (Lo12);
101 case ARM::fixup_arm_ldst_pcrel_12:
102 // ARM PC-relative values are offset by 8.
105 case ARM::fixup_t2_ldst_pcrel_12: {
106 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
109 if ((int64_t)Value < 0) {
113 assert ((Value < 4096) && "Out of range pc-relative fixup value!");
114 Value |= isAdd << 23;
116 // Same addressing mode as fixup_arm_pcrel_10,
117 // but with 16-bit halfwords swapped.
118 if (Kind == ARM::fixup_t2_ldst_pcrel_12) {
119 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
120 swapped |= (Value & 0x0000FFFF) << 16;
126 case ARM::fixup_arm_adr_pcrel_12: {
127 // ARM PC-relative values are offset by 8.
129 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
130 if ((int64_t)Value < 0) {
134 assert(ARM_AM::getSOImmVal(Value) != -1 &&
135 "Out of range pc-relative fixup value!");
136 // Encode the immediate and shift the opcode into place.
137 return ARM_AM::getSOImmVal(Value) | (opc << 21);
139 case ARM::fixup_arm_branch:
140 // These values don't encode the low two bits since they're always zero.
141 // Offset by 8 just as above.
142 return 0xffffff & ((Value - 8) >> 2);
143 case ARM::fixup_t2_uncondbranch: {
145 Value >>= 1; // Low bit is not encoded.
148 bool I = Value & 0x800000;
149 bool J1 = Value & 0x400000;
150 bool J2 = Value & 0x200000;
154 out |= I << 26; // S bit
155 out |= !J1 << 13; // J1 bit
156 out |= !J2 << 11; // J2 bit
157 out |= (Value & 0x1FF800) << 5; // imm6 field
158 out |= (Value & 0x0007FF); // imm11 field
160 uint64_t swapped = (out & 0xFFFF0000) >> 16;
161 swapped |= (out & 0x0000FFFF) << 16;
164 case ARM::fixup_t2_condbranch: {
166 Value >>= 1; // Low bit is not encoded.
169 out |= (Value & 0x80000) << 7; // S bit
170 out |= (Value & 0x40000) >> 7; // J2 bit
171 out |= (Value & 0x20000) >> 4; // J1 bit
172 out |= (Value & 0x1F800) << 5; // imm6 field
173 out |= (Value & 0x007FF); // imm11 field
175 uint32_t swapped = (out & 0xFFFF0000) >> 16;
176 swapped |= (out & 0x0000FFFF) << 16;
179 case ARM::fixup_arm_thumb_bl: {
180 // The value doesn't encode the low bit (always zero) and is offset by
181 // four. The value is encoded into disjoint bit positions in the destination
182 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit
184 // BL: xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII
186 // Note that the halfwords are stored high first, low second; so we need
187 // to transpose the fixup value here to map properly.
188 unsigned isNeg = (int64_t(Value) < 0) ? 1 : 0;
190 Value = 0x3fffff & ((Value - 4) >> 1);
191 Binary = (Value & 0x7ff) << 16; // Low imm11 value.
192 Binary |= (Value & 0x1ffc00) >> 11; // High imm10 value.
193 Binary |= isNeg << 10; // Sign bit.
196 case ARM::fixup_arm_thumb_blx: {
197 // The value doesn't encode the low two bits (always zero) and is offset by
198 // four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit
199 // positions in the destination opcode. x = unchanged, I = immediate value
200 // bit, S = sign extension bit, 0 = zero.
202 // BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0
204 // Note that the halfwords are stored high first, low second; so we need
205 // to transpose the fixup value here to map properly.
206 unsigned isNeg = (int64_t(Value) < 0) ? 1 : 0;
208 Value = 0xfffff & ((Value - 2) >> 2);
209 Binary = (Value & 0x3ff) << 17; // Low imm10L value.
210 Binary |= (Value & 0xffc00) >> 10; // High imm10H value.
211 Binary |= isNeg << 10; // Sign bit.
214 case ARM::fixup_arm_thumb_cp:
215 // Offset by 4, and don't encode the low two bits. Two bytes of that
216 // 'off by 4' is implicitly handled by the half-word ordering of the
217 // Thumb encoding, so we only need to adjust by 2 here.
218 return ((Value - 2) >> 2) & 0xff;
219 case ARM::fixup_arm_thumb_cb: {
220 // Offset by 4 and don't encode the lower bit, which is always 0.
221 uint32_t Binary = (Value - 4) >> 1;
222 return ((Binary & 0x20) << 9) | ((Binary & 0x1f) << 3);
224 case ARM::fixup_arm_thumb_br:
225 // Offset by 4 and don't encode the lower bit, which is always 0.
226 return ((Value - 4) >> 1) & 0x7ff;
227 case ARM::fixup_arm_thumb_bcc:
228 // Offset by 4 and don't encode the lower bit, which is always 0.
229 return ((Value - 4) >> 1) & 0xff;
230 case ARM::fixup_arm_pcrel_10:
231 Value = Value - 4; // ARM fixups offset by an additional word and don't
232 // need to adjust for the half-word ordering.
234 case ARM::fixup_t2_pcrel_10: {
235 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
238 if ((int64_t)Value < 0) {
242 // These values don't encode the low two bits since they're always zero.
244 assert ((Value < 256) && "Out of range pc-relative fixup value!");
245 Value |= isAdd << 23;
247 // Same addressing mode as fixup_arm_pcrel_10,
248 // but with 16-bit halfwords swapped.
249 if (Kind == ARM::fixup_t2_pcrel_10) {
250 uint32_t swapped = (Value & 0xFFFF0000) >> 16;
251 swapped |= (Value & 0x0000FFFF) << 16;
262 // FIXME: This should be in a separate file.
263 // ELF is an ELF of course...
264 class ELFARMAsmBackend : public ARMAsmBackend {
265 MCELFObjectFormat Format;
268 Triple::OSType OSType;
269 ELFARMAsmBackend(const Target &T, Triple::OSType _OSType)
270 : ARMAsmBackend(T), OSType(_OSType) {
271 HasScatteredSymbols = true;
274 virtual const MCObjectFormat &getObjectFormat() const {
278 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
279 uint64_t Value) const;
281 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
282 return createELFObjectWriter(OS, /*Is64Bit=*/false,
284 /*IsLittleEndian=*/true,
285 /*HasRelocationAddend=*/false);
289 // FIXME: Raise this to share code between Darwin and ELF.
290 void ELFARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
291 unsigned DataSize, uint64_t Value) const {
292 unsigned NumBytes = 4; // FIXME: 2 for Thumb
293 Value = adjustFixupValue(Fixup.getKind(), Value);
294 if (!Value) return; // Doesn't change encoding.
296 unsigned Offset = Fixup.getOffset();
297 assert(Offset % NumBytes == 0 && "Offset mod NumBytes is nonzero!");
299 // For each byte of the fragment that the fixup touches, mask in the bits from
300 // the fixup value. The Value has been "split up" into the appropriate
302 for (unsigned i = 0; i != NumBytes; ++i)
303 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
306 // FIXME: This should be in a separate file.
307 class DarwinARMAsmBackend : public ARMAsmBackend {
308 MCMachOObjectFormat Format;
310 DarwinARMAsmBackend(const Target &T) : ARMAsmBackend(T) {
311 HasScatteredSymbols = true;
314 virtual const MCObjectFormat &getObjectFormat() const {
318 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
319 uint64_t Value) const;
321 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
322 // FIXME: Subtarget info should be derived. Force v7 for now.
323 return createMachObjectWriter(OS, /*Is64Bit=*/false,
324 object::mach::CTM_ARM,
325 object::mach::CSARM_V7,
326 /*IsLittleEndian=*/true);
329 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
334 /// getFixupKindNumBytes - The number of bytes the fixup may change.
335 static unsigned getFixupKindNumBytes(unsigned Kind) {
338 llvm_unreachable("Unknown fixup kind!");
340 case ARM::fixup_arm_thumb_bcc:
341 case ARM::fixup_arm_thumb_cp:
344 case ARM::fixup_arm_thumb_br:
345 case ARM::fixup_arm_thumb_cb:
348 case ARM::fixup_arm_ldst_pcrel_12:
349 case ARM::fixup_arm_pcrel_10:
350 case ARM::fixup_arm_adr_pcrel_12:
351 case ARM::fixup_arm_branch:
355 case ARM::fixup_t2_ldst_pcrel_12:
356 case ARM::fixup_t2_condbranch:
357 case ARM::fixup_t2_uncondbranch:
358 case ARM::fixup_t2_pcrel_10:
359 case ARM::fixup_arm_thumb_bl:
360 case ARM::fixup_arm_thumb_blx:
365 void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
366 unsigned DataSize, uint64_t Value) const {
367 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
368 Value = adjustFixupValue(Fixup.getKind(), Value);
369 if (!Value) return; // Doesn't change encoding.
371 unsigned Offset = Fixup.getOffset();
372 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
374 // For each byte of the fragment that the fixup touches, mask in the
375 // bits from the fixup value.
376 for (unsigned i = 0; i != NumBytes; ++i)
377 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
380 } // end anonymous namespace
382 TargetAsmBackend *llvm::createARMAsmBackend(const Target &T,
383 const std::string &TT) {
384 switch (Triple(TT).getOS()) {
386 return new DarwinARMAsmBackend(T);
387 case Triple::MinGW32:
390 assert(0 && "Windows not supported on ARM");
392 return new ELFARMAsmBackend(T, Triple(TT).getOS());