1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMAddressingModes.h"
12 #include "ARMFixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCDirectives.h"
16 #include "llvm/MC/MCELFObjectWriter.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCMachObjectWriter.h"
19 #include "llvm/MC/MCObjectWriter.h"
20 #include "llvm/MC/MCSectionELF.h"
21 #include "llvm/MC/MCSectionMachO.h"
22 #include "llvm/Object/MachOFormat.h"
23 #include "llvm/Support/ELF.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Target/TargetAsmBackend.h"
27 #include "llvm/Target/TargetRegistry.h"
31 class ARMMachObjectWriter : public MCMachObjectTargetWriter {
33 ARMMachObjectWriter(bool Is64Bit, uint32_t CPUType,
35 : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype,
36 /*UseAggressiveSymbolFolding=*/true) {}
39 class ARMELFObjectWriter : public MCELFObjectTargetWriter {
41 ARMELFObjectWriter(Triple::OSType OSType)
42 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSType, ELF::EM_ARM,
43 /*HasRelocationAddend*/ false) {}
46 class ARMAsmBackend : public TargetAsmBackend {
47 bool isThumbMode; // Currently emitting Thumb code.
49 ARMAsmBackend(const Target &T) : TargetAsmBackend(), isThumbMode(false) {}
51 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
53 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
54 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
55 // This table *must* be in the order that the fixup_* kinds are defined in
58 // Name Offset (bits) Size (bits) Flags
59 { "fixup_arm_ldst_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
60 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
61 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
62 { "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
63 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
64 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
65 { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel |
66 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
67 { "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
68 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
69 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
70 { "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
71 { "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
72 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
73 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
74 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
75 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
76 { "fixup_arm_thumb_blx", 7, 21, MCFixupKindInfo::FKF_IsPCRel },
77 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
78 { "fixup_arm_thumb_cp", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
79 { "fixup_arm_thumb_bcc", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
80 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19.
81 { "fixup_arm_movt_hi16", 0, 20, 0 },
82 { "fixup_arm_movw_lo16", 0, 20, 0 },
83 { "fixup_t2_movt_hi16", 0, 20, 0 },
84 { "fixup_t2_movw_lo16", 0, 20, 0 },
85 { "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
86 { "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
87 { "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
88 { "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
91 if (Kind < FirstTargetFixupKind)
92 return TargetAsmBackend::getFixupKindInfo(Kind);
94 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
96 return Infos[Kind - FirstTargetFixupKind];
99 bool MayNeedRelaxation(const MCInst &Inst) const;
101 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
103 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
105 void HandleAssemblerFlag(MCAssemblerFlag Flag) {
117 unsigned getPointerSize() const { return 4; }
118 bool isThumb() const { return isThumbMode; }
119 void setIsThumb(bool it) { isThumbMode = it; }
121 } // end anonymous namespace
123 bool ARMAsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
124 // FIXME: Thumb targets, different move constant targets..
128 void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
129 assert(0 && "ARMAsmBackend::RelaxInstruction() unimplemented");
133 bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
135 // FIXME: 0xbf00 is the ARMv7 value. For v6 and before, we'll need to
136 // use 0x46c0 (which is a 'mov r8, r8' insn).
137 uint64_t NumNops = Count / 2;
138 for (uint64_t i = 0; i != NumNops; ++i)
145 uint64_t NumNops = Count / 4;
146 for (uint64_t i = 0; i != NumNops; ++i)
147 OW->Write32(0xe1a00000);
149 default: break; // No leftover bytes to write
150 case 1: OW->Write8(0); break;
151 case 2: OW->Write16(0); break;
152 case 3: OW->Write16(0); OW->Write8(0xa0); break;
158 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
161 llvm_unreachable("Unknown fixup kind!");
166 case ARM::fixup_arm_movt_hi16:
167 case ARM::fixup_arm_movt_hi16_pcrel:
170 case ARM::fixup_arm_movw_lo16:
171 case ARM::fixup_arm_movw_lo16_pcrel: {
172 unsigned Hi4 = (Value & 0xF000) >> 12;
173 unsigned Lo12 = Value & 0x0FFF;
174 // inst{19-16} = Hi4;
175 // inst{11-0} = Lo12;
176 Value = (Hi4 << 16) | (Lo12);
179 case ARM::fixup_t2_movt_hi16:
180 case ARM::fixup_t2_movt_hi16_pcrel:
183 case ARM::fixup_t2_movw_lo16:
184 case ARM::fixup_t2_movw_lo16_pcrel: {
185 unsigned Hi4 = (Value & 0xF000) >> 12;
186 unsigned i = (Value & 0x800) >> 11;
187 unsigned Mid3 = (Value & 0x700) >> 8;
188 unsigned Lo8 = Value & 0x0FF;
189 // inst{19-16} = Hi4;
191 // inst{14-12} = Mid3;
193 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
195 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
196 swapped |= (Value & 0x0000FFFF) << 16;
199 case ARM::fixup_arm_ldst_pcrel_12:
200 // ARM PC-relative values are offset by 8.
203 case ARM::fixup_t2_ldst_pcrel_12: {
204 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
207 if ((int64_t)Value < 0) {
211 assert ((Value < 4096) && "Out of range pc-relative fixup value!");
212 Value |= isAdd << 23;
214 // Same addressing mode as fixup_arm_pcrel_10,
215 // but with 16-bit halfwords swapped.
216 if (Kind == ARM::fixup_t2_ldst_pcrel_12) {
217 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
218 swapped |= (Value & 0x0000FFFF) << 16;
224 case ARM::fixup_thumb_adr_pcrel_10:
225 return ((Value - 4) >> 2) & 0xff;
226 case ARM::fixup_arm_adr_pcrel_12: {
227 // ARM PC-relative values are offset by 8.
229 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
230 if ((int64_t)Value < 0) {
234 assert(ARM_AM::getSOImmVal(Value) != -1 &&
235 "Out of range pc-relative fixup value!");
236 // Encode the immediate and shift the opcode into place.
237 return ARM_AM::getSOImmVal(Value) | (opc << 21);
240 case ARM::fixup_t2_adr_pcrel_12: {
243 if ((int64_t)Value < 0) {
248 uint32_t out = (opc << 21);
249 out |= (Value & 0x800) << 15;
250 out |= (Value & 0x700) << 4;
251 out |= (Value & 0x0FF);
253 uint64_t swapped = (out & 0xFFFF0000) >> 16;
254 swapped |= (out & 0x0000FFFF) << 16;
258 case ARM::fixup_arm_condbranch:
259 case ARM::fixup_arm_uncondbranch:
260 // These values don't encode the low two bits since they're always zero.
261 // Offset by 8 just as above.
262 return 0xffffff & ((Value - 8) >> 2);
263 case ARM::fixup_t2_uncondbranch: {
265 Value >>= 1; // Low bit is not encoded.
268 bool I = Value & 0x800000;
269 bool J1 = Value & 0x400000;
270 bool J2 = Value & 0x200000;
274 out |= I << 26; // S bit
275 out |= !J1 << 13; // J1 bit
276 out |= !J2 << 11; // J2 bit
277 out |= (Value & 0x1FF800) << 5; // imm6 field
278 out |= (Value & 0x0007FF); // imm11 field
280 uint64_t swapped = (out & 0xFFFF0000) >> 16;
281 swapped |= (out & 0x0000FFFF) << 16;
284 case ARM::fixup_t2_condbranch: {
286 Value >>= 1; // Low bit is not encoded.
289 out |= (Value & 0x80000) << 7; // S bit
290 out |= (Value & 0x40000) >> 7; // J2 bit
291 out |= (Value & 0x20000) >> 4; // J1 bit
292 out |= (Value & 0x1F800) << 5; // imm6 field
293 out |= (Value & 0x007FF); // imm11 field
295 uint32_t swapped = (out & 0xFFFF0000) >> 16;
296 swapped |= (out & 0x0000FFFF) << 16;
299 case ARM::fixup_arm_thumb_bl: {
300 // The value doesn't encode the low bit (always zero) and is offset by
301 // four. The value is encoded into disjoint bit positions in the destination
302 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit
304 // BL: xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII
306 // Note that the halfwords are stored high first, low second; so we need
307 // to transpose the fixup value here to map properly.
308 unsigned isNeg = (int64_t(Value) < 0) ? 1 : 0;
310 Value = 0x3fffff & ((Value - 4) >> 1);
311 Binary = (Value & 0x7ff) << 16; // Low imm11 value.
312 Binary |= (Value & 0x1ffc00) >> 11; // High imm10 value.
313 Binary |= isNeg << 10; // Sign bit.
316 case ARM::fixup_arm_thumb_blx: {
317 // The value doesn't encode the low two bits (always zero) and is offset by
318 // four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit
319 // positions in the destination opcode. x = unchanged, I = immediate value
320 // bit, S = sign extension bit, 0 = zero.
322 // BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0
324 // Note that the halfwords are stored high first, low second; so we need
325 // to transpose the fixup value here to map properly.
326 unsigned isNeg = (int64_t(Value) < 0) ? 1 : 0;
328 Value = 0xfffff & ((Value - 2) >> 2);
329 Binary = (Value & 0x3ff) << 17; // Low imm10L value.
330 Binary |= (Value & 0xffc00) >> 10; // High imm10H value.
331 Binary |= isNeg << 10; // Sign bit.
334 case ARM::fixup_arm_thumb_cp:
335 // Offset by 4, and don't encode the low two bits. Two bytes of that
336 // 'off by 4' is implicitly handled by the half-word ordering of the
337 // Thumb encoding, so we only need to adjust by 2 here.
338 return ((Value - 2) >> 2) & 0xff;
339 case ARM::fixup_arm_thumb_cb: {
340 // Offset by 4 and don't encode the lower bit, which is always 0.
341 uint32_t Binary = (Value - 4) >> 1;
342 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
344 case ARM::fixup_arm_thumb_br:
345 // Offset by 4 and don't encode the lower bit, which is always 0.
346 return ((Value - 4) >> 1) & 0x7ff;
347 case ARM::fixup_arm_thumb_bcc:
348 // Offset by 4 and don't encode the lower bit, which is always 0.
349 return ((Value - 4) >> 1) & 0xff;
350 case ARM::fixup_arm_pcrel_10:
351 Value = Value - 4; // ARM fixups offset by an additional word and don't
352 // need to adjust for the half-word ordering.
354 case ARM::fixup_t2_pcrel_10: {
355 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
358 if ((int64_t)Value < 0) {
362 // These values don't encode the low two bits since they're always zero.
364 assert ((Value < 256) && "Out of range pc-relative fixup value!");
365 Value |= isAdd << 23;
367 // Same addressing mode as fixup_arm_pcrel_10,
368 // but with 16-bit halfwords swapped.
369 if (Kind == ARM::fixup_t2_pcrel_10) {
370 uint32_t swapped = (Value & 0xFFFF0000) >> 16;
371 swapped |= (Value & 0x0000FFFF) << 16;
382 // FIXME: This should be in a separate file.
383 // ELF is an ELF of course...
384 class ELFARMAsmBackend : public ARMAsmBackend {
386 Triple::OSType OSType;
387 ELFARMAsmBackend(const Target &T, Triple::OSType _OSType)
388 : ARMAsmBackend(T), OSType(_OSType) { }
390 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
391 uint64_t Value) const;
393 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
394 return createELFObjectWriter(new ARMELFObjectWriter(OSType), OS,
395 /*IsLittleEndian*/ true);
399 // FIXME: Raise this to share code between Darwin and ELF.
400 void ELFARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
401 unsigned DataSize, uint64_t Value) const {
402 unsigned NumBytes = 4; // FIXME: 2 for Thumb
403 Value = adjustFixupValue(Fixup.getKind(), Value);
404 if (!Value) return; // Doesn't change encoding.
406 unsigned Offset = Fixup.getOffset();
407 assert(Offset % NumBytes == 0 && "Offset mod NumBytes is nonzero!");
409 // For each byte of the fragment that the fixup touches, mask in the bits from
410 // the fixup value. The Value has been "split up" into the appropriate
412 for (unsigned i = 0; i != NumBytes; ++i)
413 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
416 // FIXME: This should be in a separate file.
417 class DarwinARMAsmBackend : public ARMAsmBackend {
419 DarwinARMAsmBackend(const Target &T) : ARMAsmBackend(T) { }
421 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
422 uint64_t Value) const;
424 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
425 // FIXME: Subtarget info should be derived. Force v7 for now.
426 return createMachObjectWriter(new ARMMachObjectWriter(
428 object::mach::CTM_ARM,
429 object::mach::CSARM_V7),
431 /*IsLittleEndian=*/true);
434 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
439 /// getFixupKindNumBytes - The number of bytes the fixup may change.
440 static unsigned getFixupKindNumBytes(unsigned Kind) {
443 llvm_unreachable("Unknown fixup kind!");
446 case ARM::fixup_arm_thumb_bcc:
447 case ARM::fixup_arm_thumb_cp:
448 case ARM::fixup_thumb_adr_pcrel_10:
452 case ARM::fixup_arm_thumb_br:
453 case ARM::fixup_arm_thumb_cb:
456 case ARM::fixup_arm_ldst_pcrel_12:
457 case ARM::fixup_arm_pcrel_10:
458 case ARM::fixup_arm_adr_pcrel_12:
459 case ARM::fixup_arm_condbranch:
460 case ARM::fixup_arm_uncondbranch:
464 case ARM::fixup_t2_ldst_pcrel_12:
465 case ARM::fixup_t2_condbranch:
466 case ARM::fixup_t2_uncondbranch:
467 case ARM::fixup_t2_pcrel_10:
468 case ARM::fixup_t2_adr_pcrel_12:
469 case ARM::fixup_arm_thumb_bl:
470 case ARM::fixup_arm_thumb_blx:
471 case ARM::fixup_arm_movt_hi16:
472 case ARM::fixup_arm_movw_lo16:
473 case ARM::fixup_arm_movt_hi16_pcrel:
474 case ARM::fixup_arm_movw_lo16_pcrel:
475 case ARM::fixup_t2_movt_hi16:
476 case ARM::fixup_t2_movw_lo16:
477 case ARM::fixup_t2_movt_hi16_pcrel:
478 case ARM::fixup_t2_movw_lo16_pcrel:
483 void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
484 unsigned DataSize, uint64_t Value) const {
485 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
486 Value = adjustFixupValue(Fixup.getKind(), Value);
487 if (!Value) return; // Doesn't change encoding.
489 unsigned Offset = Fixup.getOffset();
490 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
492 // For each byte of the fragment that the fixup touches, mask in the
493 // bits from the fixup value.
494 for (unsigned i = 0; i != NumBytes; ++i)
495 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
498 } // end anonymous namespace
500 TargetAsmBackend *llvm::createARMAsmBackend(const Target &T,
501 const std::string &TT) {
502 switch (Triple(TT).getOS()) {
504 return new DarwinARMAsmBackend(T);
505 case Triple::MinGW32:
508 assert(0 && "Windows not supported on ARM");
510 return new ELFARMAsmBackend(T, Triple(TT).getOS());