1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMAddressingModes.h"
12 #include "ARMFixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCObjectFormat.h"
17 #include "llvm/MC/MCObjectWriter.h"
18 #include "llvm/MC/MCSectionELF.h"
19 #include "llvm/MC/MCSectionMachO.h"
20 #include "llvm/Object/MachOFormat.h"
21 #include "llvm/Support/ELF.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Target/TargetAsmBackend.h"
25 #include "llvm/Target/TargetRegistry.h"
29 class ARMAsmBackend : public TargetAsmBackend {
31 ARMAsmBackend(const Target &T) : TargetAsmBackend() {}
33 bool MayNeedRelaxation(const MCInst &Inst) const;
35 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
37 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
39 unsigned getPointerSize() const {
43 } // end anonymous namespace
45 bool ARMAsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
46 // FIXME: Thumb targets, different move constant targets..
50 void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
51 assert(0 && "ARMAsmBackend::RelaxInstruction() unimplemented");
55 bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
56 // FIXME: Zero fill for now. That's not right, but at least will get the
57 // section size right.
58 for (uint64_t i = 0; i != Count; ++i)
63 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
66 llvm_unreachable("Unknown fixup kind!");
68 case ARM::fixup_arm_movt_hi16:
69 case ARM::fixup_arm_movw_lo16:
71 case ARM::fixup_arm_ldst_pcrel_12: {
73 // ARM PC-relative values are offset by 8.
75 if ((int64_t)Value < 0) {
79 assert ((Value < 4096) && "Out of range pc-relative fixup value!");
83 case ARM::fixup_arm_adr_pcrel_12: {
84 // ARM PC-relative values are offset by 8.
86 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
87 if ((int64_t)Value < 0) {
91 assert(ARM_AM::getSOImmVal(Value) != -1 &&
92 "Out of range pc-relative fixup value!");
93 // Encode the immediate and shift the opcode into place.
94 return ARM_AM::getSOImmVal(Value) | (opc << 21);
96 case ARM::fixup_arm_branch:
97 // These values don't encode the low two bits since they're always zero.
98 // Offset by 8 just as above.
99 return (Value - 8) >> 2;
100 case ARM::fixup_arm_pcrel_10: {
101 // Offset by 8 just as above.
104 if ((int64_t)Value < 0) {
108 // These values don't encode the low two bits since they're always zero.
110 assert ((Value < 256) && "Out of range pc-relative fixup value!");
111 Value |= isAdd << 23;
118 // FIXME: This should be in a separate file.
119 // ELF is an ELF of course...
120 class ELFARMAsmBackend : public ARMAsmBackend {
121 MCELFObjectFormat Format;
124 Triple::OSType OSType;
125 ELFARMAsmBackend(const Target &T, Triple::OSType _OSType)
126 : ARMAsmBackend(T), OSType(_OSType) {
127 HasScatteredSymbols = true;
130 virtual const MCObjectFormat &getObjectFormat() const {
134 void ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
135 uint64_t Value) const;
137 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
138 return createELFObjectWriter(OS, /*Is64Bit=*/false,
140 /*IsLittleEndian=*/true,
141 /*HasRelocationAddend=*/false);
145 // Fixme: can we raise this to share code between Darwin and ELF?
146 void ELFARMAsmBackend::ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
147 uint64_t Value) const {
149 // Fixme: 2 for Thumb
150 unsigned NumBytes = 4;
151 Value = adjustFixupValue(Fixup.getKind(), Value);
153 switch (Fixup.getKind()) {
154 default: assert(0 && "Unsupported Fixup kind"); break;
155 case ARM::fixup_arm_branch: {
156 unsigned Lo24 = Value & 0xFFFFFF;
160 case ARM::fixup_arm_movt_hi16:
161 case ARM::fixup_arm_movw_lo16: {
162 unsigned Hi4 = (Value & 0xF000) >> 12;
163 unsigned Lo12 = Value & 0x0FFF;
164 // inst{19-16} = Hi4;
165 // inst{11-0} = Lo12;
166 Value = (Hi4 << 16) | (Lo12);
171 assert((Fixup.getOffset() % NumBytes == 0)
172 && "Offset mod NumBytes is nonzero!");
173 // For each byte of the fragment that the fixup touches, mask in the
174 // bits from the fixup value.
175 // The Value has been "split up" into the appropriate bitfields above.
176 // Fixme: how to share code with the .td generated code?
177 for (unsigned i = 0; i != NumBytes; ++i) {
178 DF.getContents()[Fixup.getOffset() + i] &= uint8_t(Mask >> (i * 8));
179 DF.getContents()[Fixup.getOffset() + i] |= uint8_t(Value >> (i * 8));
184 // FIXME: This should be in a separate file.
185 class DarwinARMAsmBackend : public ARMAsmBackend {
186 MCMachOObjectFormat Format;
188 DarwinARMAsmBackend(const Target &T) : ARMAsmBackend(T) {
189 HasScatteredSymbols = true;
192 virtual const MCObjectFormat &getObjectFormat() const {
196 void ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
197 uint64_t Value) const;
199 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
200 // FIXME: Subtarget info should be derived. Force v7 for now.
201 return createMachObjectWriter(OS, /*Is64Bit=*/false,
202 object::mach::CTM_ARM,
203 object::mach::CSARM_V7,
204 /*IsLittleEndian=*/true);
207 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
211 } // end anonymous namespace
213 static unsigned getFixupKindNumBytes(unsigned Kind) {
215 default: llvm_unreachable("Unknown fixup kind!");
216 case FK_Data_4: return 4;
217 case ARM::fixup_arm_ldst_pcrel_12: return 3;
218 case ARM::fixup_arm_pcrel_10: return 3;
219 case ARM::fixup_arm_adr_pcrel_12: return 3;
220 case ARM::fixup_arm_branch: return 3;
224 void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
225 uint64_t Value) const {
226 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
227 Value = adjustFixupValue(Fixup.getKind(), Value);
229 assert(Fixup.getOffset() + NumBytes <= DF.getContents().size() &&
230 "Invalid fixup offset!");
231 // For each byte of the fragment that the fixup touches, mask in the
232 // bits from the fixup value.
233 for (unsigned i = 0; i != NumBytes; ++i)
234 DF.getContents()[Fixup.getOffset() + i] |= uint8_t(Value >> (i * 8));
236 } // end anonymous namespace
238 TargetAsmBackend *llvm::createARMAsmBackend(const Target &T,
239 const std::string &TT) {
240 switch (Triple(TT).getOS()) {
242 return new DarwinARMAsmBackend(T);
243 case Triple::MinGW32:
246 assert(0 && "Windows not supported on ARM");
248 return new ELFARMAsmBackend(T, Triple(TT).getOS());